KR20010005124A - Method for forming feram capable of preventing hydrogen diffusion - Google Patents

Method for forming feram capable of preventing hydrogen diffusion Download PDF

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KR20010005124A
KR20010005124A KR1019990025921A KR19990025921A KR20010005124A KR 20010005124 A KR20010005124 A KR 20010005124A KR 1019990025921 A KR1019990025921 A KR 1019990025921A KR 19990025921 A KR19990025921 A KR 19990025921A KR 20010005124 A KR20010005124 A KR 20010005124A
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film
hydrogen diffusion
forming
hydrogen
memory device
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KR1019990025921A
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김영중
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김영환
현대전자산업 주식회사
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B65CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B65CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
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    • BPERFORMING OPERATIONS; TRANSPORTING
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    • BPERFORMING OPERATIONS; TRANSPORTING
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Abstract

PURPOSE: A method for fabricating a ferroelectric memory device having a barrier to hydrogen diffusion is provided to prevent degradation in polarization characteristics of a ferroelectric capacitor. CONSTITUTION: A transistor having a gate electrode(14) and a source/drain(15), a capacitor having lower and upper electrodes(20,22) and a ferroelectric layer(21), the first and the second metallization layers(26,28), and the like are formed on a semiconductor substrate(11). Then, an insulating layer(29) is formed on the entire resultant structure, and a barrier to hydrogen diffusion is formed thereon. Particularly, the hydrogen diffusion barrier is composed of a titanium layer(30) and a titanium oxide layer(31). Thereafter, a passivation layer(32) is formed on the hydrogen diffusion barrier(30,31). The hydrogen diffusion barrier can trap hydrogen produced during the formation of the passivation layer(32) to the interface between the titanium layer(30) and the titanium oxide layer(31).

Description

수소 확산을 방지할 수 있는 강유전체 메모리 소자 제조 방법{METHOD FOR FORMING FERAM CAPABLE OF PREVENTING HYDROGEN DIFFUSION}Method for manufacturing ferroelectric memory device that can prevent hydrogen diffusion {METHOD FOR FORMING FERAM CAPABLE OF PREVENTING HYDROGEN DIFFUSION}

본 발명은 반도체 메모리 소자 제조 방법에 관한 것으로, 특히 수소 확산에 의한 강유전체 특성 저하를 방지할 수 있는 강유전체 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a ferroelectric memory device capable of preventing a decrease in ferroelectric properties due to hydrogen diffusion.

반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.

FeRAM 소자의 축전물질로는 SrBi2Ta2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.As the storage material of the FeRAM device, SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) thin films are mainly used. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .

FeRAM 소자에서 캐패시터의 강유전체 재료로서 PZT, SBT, SrxBiy(TaiNbj)2O9(이하 SBTN) 등의 페롭스카이트(perovskite) 구조를 갖는 강유전체를 사용하는 경우 통상적으로 Pt, Ir, Ru, Pt 합금 등의 금속으로 상부전극을 형성한다.As the ferroelectric material of the capacitor in the FeRAM element PZT, SBT, Sr x Bi y (Ta i Nb j) 2 O 9 in the conventional case of using a ferroelectric having a perovskite (perovskite) structure, such as (the SBTN) Pt, Ir The upper electrode is formed of a metal such as Ru, Pt alloy, or the like.

이와 같이 FeRAM 소자는 SBT 등과 같은 강유전체막의 분극 특성을 이용하는 메모리 소자이다. FeRAM의 특성상 소자의 수명이 다할 때까지 수많은 분극 과정이 반복되어야만 신뢰성 있는 소자로서 사용할 수 있다. 따라서, 분극특성의 향상과 저하 방지는 FeRAM 소자의 기본적인 요구 조건이 된다. 그러나, FeRAM 소자 제조 공정 중 분극특성 저하가 발생하여 FeRAM 소자의 신뢰성 확보에 결정적이 단점이 된다.As described above, the FeRAM device is a memory device that uses polarization characteristics of a ferroelectric film such as SBT. Due to the characteristics of FeRAM, many polarization processes have to be repeated until the lifetime of the device can be used as a reliable device. Therefore, improvement in polarization characteristics and prevention of deterioration are basic requirements for FeRAM devices. However, deterioration in polarization characteristics occurs during the FeRAM device manufacturing process, which is a critical disadvantage in securing the reliability of the FeRAM device.

금속 배선 공정 후 소자 보호를 위해 소자보호(passivation)층으로 SiO2/Si3N4의 이중막을 증착하는데, 분극특성 저하는 이러한 소자보호층 형성 과정에서 발생하는 수소에 의해 나타나는 것으로 알려져 있다. 소자보호층 형성 과정에서 발생하는 수소의 확산을 방지하기 위하여 Ti계 단일막으로 이루어지는 수소확산방지막(covering layer)을 형성하고 있으나 분극특성 저하를 효과적으로 억제하지 못하고 있다.In order to protect the device after the metallization process, a double layer of SiO 2 / Si 3 N 4 is deposited as a passivation layer, and the decrease in polarization characteristics is known to be caused by hydrogen generated during the formation of the device protection layer. In order to prevent the diffusion of hydrogen generated in the process of forming a device protection layer, a hydrogen diffusion preventing layer (Ti) -based single layer is formed, but the polarization characteristic is not effectively suppressed.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 소자 보호를 위한 산화막 및 질화막 형성과정에서 발생하는 수소로 인한 강유전체 캐패시터의 분극 특성 저하를 방지할 수 있는, 강유전체 메모리 소자의 수소 확산방지막 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is a method of forming a hydrogen diffusion barrier of a ferroelectric memory device, which can prevent the degradation of polarization characteristics of the ferroelectric capacitor due to hydrogen generated in the oxide film and nitride film forming process for device protection The purpose is to provide.

도1은 본 발명의 일실시예에 따른 강유전체 메모리 소자 제조 공정 단면도,1 is a cross-sectional view of a ferroelectric memory device manufacturing process according to an embodiment of the present invention;

도2는 패드가 노출된 상태를 보이는 공정 단면도.2 is a process sectional view showing a state where the pad is exposed.

*도면의 주요 부분에 대한 도면부호의 설명** Description of reference numerals for the main parts of the drawings *

20: 하부전극 21: 강유전체막20: lower electrode 21: ferroelectric film

22: 상부전극 26: 제1 금속배선22: upper electrode 26: first metal wiring

28: 제1 금속배선 및 패드 29: 절연막28: first metal wiring and pad 29: insulating film

30: Ti막 31: TiO230: Ti film 31: TiO 2 film

32: 소자보호막32: element protection film

상기와 같은 목적을 달성하기 위한 본 발명은 트랜지스터, 강유전체 캐패시터 및 금속배선 형성이 완료된 전체 구조 상에 절연막을 형성하는 제1 단계; 상기 절연막 상에 차례로 증착된 티타늄막 및 산화티타늄막으로 이루어지는 수소확산방지막을 형성하는 제2 단계; 및 상기 수소확산방지막 상에 소자보호막을 형성하는 제3 단계를 포함하는 강유전체 메모리 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming an insulating film on the entire structure of the transistor, the ferroelectric capacitor and the metal wiring is completed; A second step of forming a hydrogen diffusion prevention film formed of a titanium film and a titanium oxide film sequentially deposited on the insulating film; And a third step of forming a device protection film on the hydrogen diffusion prevention film.

본 발명은 소자 보호를 위한 산화막 및 질화막 형성 과정에서 발생하는 수소에 의한 강유전체 특성 저하를 방지하기 위하여, 금속배선 및 패드 형성이 완료된 기판 상에 수소가 함유되지 않은 소스를 이용하여 절연막을 형성하고, Ti막 및 TiO2막으로 이루어지는 2층 구조의 수소 확산방지막을 형성하고, TiO2막을 산소 플라즈마 처리한 다음, 소자보호를 위한 SiO2막 및 Si3N4막을 증착하는데 특징이 있다.The present invention forms an insulating film using a source containing no hydrogen on a substrate on which metal wiring and pad formation are completed, in order to prevent degradation of ferroelectric properties due to hydrogen generated during the formation of an oxide film and a nitride film for protecting the device. It is characterized by forming a hydrogen diffusion barrier film having a two-layer structure consisting of a Ti film and a TiO 2 film, subjecting the TiO 2 film to oxygen plasma treatment, and then depositing a SiO 2 film and a Si 3 N 4 film for device protection.

이후, 패드(PAD) 마스크를 사용하여 Si3N4막, SiO2막, TiO2막 및 Ti막을 선택적으로 식각하여 패드를 노출시키는 콘택홀을 형성한 후, 콘택홀 측벽에 노출된 Ti막을 산소 플라즈마로 처리하여 와이어(wire)와 Ti막의 단락을 방지한다.Subsequently, the Si 3 N 4 film, the SiO 2 film, the TiO 2 film, and the Ti film are selectively etched using a pad (PAD) mask to form a contact hole exposing the pad, and then the Ti film exposed on the contact hole sidewall is oxygenated. Treatment with plasma prevents shorting of the wire and the Ti film.

이하, 첨부된 도면 도1 및 도2를 참조하여 본 발명의 일실시예에 따른 강유전체 메모리 소자 제조 방법을 상세히 설명한다.Hereinafter, a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

도1에 도시한 바와 같이 소자분리막(12) 그리고 게이트 절연막(13), 게이트 전극(12) 및 소오스·드레인(13)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(11) 상부에 BPSG 등으로 제1 층간절연막(16)을 형성하고, 상기 제1 층간절연막(16) 내에 형성된 콘택홀을 통하여 상기 트랜지스터의 소오스·드레인(15)과 연결되는 비트라인(17)을 형성한다.As shown in FIG. 1, the first interlayer is formed on the semiconductor substrate 11 on which the transistor formation, which consists of the device isolation film 12, the gate insulating film 13, the gate electrode 12, and the source and drain 13, is completed. An insulating film 16 is formed, and a bit line 17 connected to the source and drain 15 of the transistor is formed through a contact hole formed in the first interlayer insulating film 16.

이어서, 비트라인(17) 형성이 완료된 전체 구조 상에 제2 층간절연막(18)을 형성하고, 제2 층간절연막(18) 상에 접착층(19)을 형성하고, 하부전극(20), 강유전체막(21) 및 상부전극(22)으로 이루어지는 캐패시터를 형성한다.Subsequently, a second interlayer insulating film 18 is formed on the entire structure where the bit line 17 is formed, an adhesive layer 19 is formed on the second interlayer insulating film 18, and the lower electrode 20 and the ferroelectric film are formed. The capacitor which consists of 21 and the upper electrode 22 is formed.

다음으로, 캐패시터 형성이 완료된 전체 구조 상에 제3 층간절연막(23)을 형성하고, 제3 층간절연막(23)을 선택적으로 식각하여 상부전극(22)을 노출시키는 콘택홀을 형성하고, 층간절연막(23), 제2 층간절연막(18) 및 제1 층간절연막(16)을 선택적으로 식각하여 반도체 기판(10)에 형성된 소오스·드레인(14)을 노출시키는 콘택홀을 형성한다.Next, a third interlayer insulating film 23 is formed on the entire structure of the capacitor formation, the third interlayer insulating film 23 is selectively etched to form a contact hole for exposing the upper electrode 22, and the interlayer insulating film (23), the second interlayer insulating film 18 and the first interlayer insulating film 16 are selectively etched to form contact holes for exposing the source and drain 14 formed in the semiconductor substrate 10.

다음으로, 이후의 금속 배선 및 확산방지막 형성 공정시 캐패시터의 특성이 저하되는 것을 방지하기 위하여 상부전극막과 접하는 제1 확산방지막(24) 패턴을 형성한다.Next, in order to prevent deterioration of the characteristics of the capacitor during the subsequent metal wiring and diffusion barrier formation process, a first diffusion barrier layer 24 is formed to contact the upper electrode layer.

이어서, 제2 확산방지막(25), 제1 금속배선(26) 및 금속배선간 절연막(27)을 형성하고, 금속배선간 절연막을 선택적으로 식각하여 제1 금속배선(26)과 제2 금속배선의 연결을 위한 콘택홀(도시하지 않음)을 형성하고, 입출력 및 전원 공급을 위한 제2 금속배선 및 패드(28)를 형성한다.Subsequently, the second diffusion barrier 25, the first metal wiring 26, and the intermetallic insulating film 27 are formed, and the intermetallic insulating film is selectively etched to form the first metal wiring 26 and the second metal wiring. Contact holes (not shown) for connection of the second and second metal wires and pads 28 for input / output and power supply are formed.

이와 같이 제2 금속배선 및 패드(28) 형성이 완료된 전체 구조 상에 수소를 사용하지 않는 소스(source)를 사용하여 1000 Å 내지 5000 Å 두께의 절연막(29)을 03-TEOS(tetraethyl orthosilicate) 등으로 형성하고, 절연막(29) 상에 수소 확산방지막으로서 100 Å 내지 1000 Å 두께의 Ti막(20) 및 100Å 내지 1500 Å 두께의 TiO2막(31)을 스퍼터링(sputtering) 방법으로 형성한다. 이어서, 산소 플라즈마 처리를 실시하여 TiO2막이 TiOx(도시하지 않음)의 준안정상이 되도록 한 후, SiO2및 Si3N4등으로 이루어지는 소자보호막(32)을 형성한다.As described above, the insulating film 29 having a thickness of 1000 to 5000 kW is used to form 0 3 -TEOS (tetraethyl orthosilicate) by using a source that does not use hydrogen on the entire structure where the second metal wiring and the pad 28 are completed. The Ti film 20 having a thickness of 100 kPa to 1000 kPa and the TiO 2 film 31 having a thickness of 100 kPa to 1500 kPa are formed on the insulating film 29 by sputtering. Subsequently, oxygen plasma treatment is performed to make the TiO 2 film metastable in TiO x (not shown), and then an element protective film 32 made of SiO 2 , Si 3 N 4, or the like is formed.

전술한 바와 같이 수소확산방지막으로서 Ti막(30)/TiO2막(31)의 이중막을 형성함으로써 소자보호막(32) 형성 과정에서 발생하는 수소를 Ti/TiO2의 계면에 포획(trap)할 수 있다. 또한, 산소 플라즈마 처리로 TiO2막 표면을 준안정상의 TiOx로 형성하여 TiOx의 비결합손(broken bond)이 수소를 포획하도록 함으로써 수소 확산을 보다 효과적으로 방지할 수 있다. 이와 같이 먼저 포획된 수소는 이중 보호막 증착 공정중 추가로 발생되는 수소의 침투를 방지하게 되어 소자의 분극특성 저하를 억제하게 된다.As described above, by forming a double film of the Ti film 30 / TiO 2 film 31 as the hydrogen diffusion prevention film, hydrogen generated in the process of forming the device protection film 32 can be trapped at the interface of Ti / TiO 2 . have. In addition, the oxygen plasma treatment forms the surface of the TiO 2 film as metastable TiO x so that a broken bond of TiO x captures hydrogen, thereby more effectively preventing hydrogen diffusion. Thus, the first trapped hydrogen prevents the penetration of hydrogen that is additionally generated during the double passivation layer deposition process, thereby suppressing a decrease in polarization characteristics of the device.

한편, 도2에 도시한 바와 같이 소자보호막(32) 형성 후 와이어링(wiring)을 위해 소자보호막(32), TiO2막(31), Ti막(30), 절연막(29)을 선택적으로 식각하여 패드(28)를 노출시키는 콘택홀을 형성한다. 이때, 콘택홀 측벽에 노출된 Ti막(30)의 절연을 위해 산소 플라즈마 처리를 실시한다. 이와 같이 산소 플라즈마 처리에 의해 노출된 Ti막(30) 부분이 TiOx로 바뀌어 와이어링 형성시 발생할 수 있는 단락(short)을 예방하게 된다.Meanwhile, as shown in FIG. 2, the device protection film 32, the TiO 2 film 31, the Ti film 30, and the insulating film 29 are selectively etched for wiring after the device protection film 32 is formed. As a result, a contact hole exposing the pad 28 is formed. At this time, oxygen plasma treatment is performed to insulate the Ti film 30 exposed on the sidewalls of the contact hole. As such, the portion of the Ti film 30 exposed by the oxygen plasma treatment is changed to TiO x to prevent shorts that may occur during wiring formation.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 강유전체 메모리 소자 제조 공정에서 금속배선 형성이 완료된 전체 구조 상에 Ti막 및 TiO2막으로 이루어지는 이중막 구조의 수소확산방지막을 형성하여, SiO2및 Si3N4등과 같은 소자보호막 형성 과정에서 발생하는 수소를 Ti막과 TiO2막의 계면에 포획하여 강유전체 캐패시터로 수소가 확산되는 것을 효과적으로 방지할 수 있다. 또한, TiO2막을 산소 플라즈마 처리하여 준안정상의 TiOx를 형성함으로써 TiOx의 비결합손에 수소를 포획할 수 있어 수소 확산을 보다 효과적으로 방지할 수 있다.According to the present invention made as described above, a hydrogen diffusion prevention film having a double film structure consisting of a Ti film and a TiO 2 film is formed on the entire structure of the metal wire formation in the ferroelectric memory device manufacturing process, such as SiO 2 and Si 3 N 4 . Hydrogen generated during the device protection film formation process may be trapped at the interface between the Ti film and the TiO 2 film, thereby effectively preventing hydrogen from diffusing into the ferroelectric capacitor. In addition, TiO 2 film by forming a TiO x on the quasi-stable to oxygen plasma treatment can be trapped in the non-hydrogen bonding hands of TiO x can be more effectively prevented the hydrogen diffusion.

Claims (6)

강유전체 메모리 소자 제조 방법에 있어서,In the ferroelectric memory device manufacturing method, 트랜지스터, 강유전체 캐패시터 및 금속배선 형성이 완료된 전체 구조 상에 절연막을 형성하는 제1 단계;A first step of forming an insulating film on the entire structure of the transistor, the ferroelectric capacitor, and the metal wirings are completed; 상기 절연막 상에 차례로 증착된 티타늄막 및 산화티타늄막으로 이루어지는 수소확산방지막을 형성하는 제2 단계; 및A second step of forming a hydrogen diffusion prevention film formed of a titanium film and a titanium oxide film sequentially deposited on the insulating film; And 상기 수소확산방지막 상에 소자보호막을 형성하는 제3 단계A third step of forming an element protection film on the hydrogen diffusion prevention film 를 포함하는 강유전체 메모리 소자 제조 방법.Ferroelectric memory device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제2 단계는,The second step, 상기 절연막 상에 Ti막을 형성하는 제4 단계; 및Forming a Ti film on the insulating film; And 상기 Ti막 상에 TiO2막을 형성하는 제5 단계A fifth step of forming a TiO 2 film on the Ti film 를 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.A ferroelectric memory device manufacturing method comprising a. 제 2 항에 있어서,The method of claim 2, 상기 제5 단계 후,After the fifth step, 상기 TiO2막을 산소플라즈마 처리하는 제6 단계를 더 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.And a sixth step of subjecting the TiO 2 film to oxygen plasma treatment. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 제3 단계 후,After the third step, 상기 소자보호막, 상기 수소확산방지막 및 상기 절연막을 선택적으로 식각하여 상기 금속배선과 연결된 패드를 노출시키는 콘택홀을 형성하는 제7 단계; 및A seventh step of selectively etching the device protection film, the hydrogen diffusion prevention film, and the insulating film to form a contact hole exposing a pad connected to the metal wiring; And 상기 콘택홀 측벽에 노출된 상기 티타늄막을 산소플라즈마 처리하는 제8 단계를 더 포함하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.And an eighth step of subjecting the titanium film exposed to the sidewalls of the contact hole to oxygen plasma treatment. 제 4 항에 있어서,The method of claim 4, wherein 상기 절연막을 수소를 포함하지 않는 소스로 형성하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.A method for manufacturing a ferroelectric memory device, characterized in that the insulating film is formed from a source containing no hydrogen. 제 5 항에 있어서,The method of claim 5, 상기 소자보호막을The device protective film SiO2막 및 Si3N4막으로 형성하는 것을 특징으로 하는 강유전체 메모리 소자 제조 방법.A method of manufacturing a ferroelectric memory device, characterized in that it is formed of a SiO 2 film and a Si 3 N 4 film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020035748A (en) * 2000-11-07 2002-05-15 다카노 야스아키 Semiconductor device and manufacturing method thereof
KR100604663B1 (en) * 1999-12-28 2006-07-25 주식회사 하이닉스반도체 FeRAM having double CLD and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604663B1 (en) * 1999-12-28 2006-07-25 주식회사 하이닉스반도체 FeRAM having double CLD and method for forming the same
KR20020035748A (en) * 2000-11-07 2002-05-15 다카노 야스아키 Semiconductor device and manufacturing method thereof

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