JPH1197647A - Capacitor and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration due to manufacturing process and simultaneously prevent deterioration, even in a subsequent reducing atmosphere by completely covering the upper part, side part and lower part of a capacitor with any nitride film of Si, Al, Ti. SOLUTION: A capacitor lower inter-layer insulating film 6 is formed, for example, in a shape such that a plate wire 25 is embedded. Next, a groove is formed in the capacitor lower inter-layer insulating film 6, a plate 25 is partially exposed and thereafter SiN 22 is formed over the entire part. Next, after SiN 22 has been partially etched in the groove and a lower electrode 26 of ferroelectric material capacitor is etched back after it has been formed over the entire surface, leaving it only at the groove. Moreover, a ferroelectric material 10 is formed and is also etched back nevertheless. Next, an upper electrode 1 and a TiN 23 are continuously formed. Thereafter, a SiN film 24 is further formed thereon. In this way, since the side surface, upper surface of capacitor are covered with the first to third cover films, deterioration due to reducing atmosphere can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a ferroelectric or high dielectric capacitor mounted on a semiconductor memory, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, non-volatile memories using a ferroelectric as an insulating film for a storage capacitor and memories using a high dielectric constant film as an insulating film for a capacitor in order to compensate for the reduction in the absolute value of the storage capacity accompanying the miniaturization of DRAM. The development of is very active. In these cases, applying a ferroelectric or high dielectric to a silicon LSI process is a major issue. Since the basic structures of a nonvolatile memory using a ferroelectric and a DRAM using a high dielectric are similar, the prior art of the former will be introduced below.

Semiconductors and ferroelectrics, for example, zirconium titanate
Lead (Pb (Zr_x Ti_1- ) O _Three , Hereinafter, with PZT
Abbreviated name), a so-called ferroelectric
Mori uses the remanent polarization of ferroelectrics to create "1" and "0".
Remember. Because this information is retained even if the power is turned off
Is known to operate as a non-volatile memory.
You. FIG. 7 shows the basic configuration of the unit cell.
FIG. In this case, the unit cell is one cell
Transistor (usually n-channel MOSFET) Tr
The configuration is such that electric capacity Cf is combined. bit
Line (abbreviated as BL), word line (abbreviated as WL), plate line
(Abbreviated as PL) by controlling the voltage applied to
r on and off, and change the polarity of the voltage applied to Cf.
This determines the sign of the remanent polarization of Cf.

In the memory cell of FIG. 7, a ferroelectric capacitor Cf and a cell transistor Tr are formed on the same chip.
Needless to say, both Cf and Tr need to operate normally. In particular, in this case, in order for the Tr to operate normally, its threshold voltage and the like must be constant in all cells. This is not limited to memory cells. For example, a memory chip includes a peripheral circuit composed of a large number of transistors in addition to the memory cells. The same operation is required for normal operation. It is known that the variation in the threshold voltage of a transistor increases due to process damage during various LSI processes. In order to recover this, it is known that a step of annealing at 400 ° C. in hydrogen after the completion of the Al wiring process is effective. That is, through this step, the characteristics of all the transistors in the memory become uniform, and normal memory operation becomes possible. This is particularly important when the integration scale of the memory is increased.

In the hydrogen annealing step, the characteristics of Tr are improved, while the characteristics of ferroelectric capacitor Cf are deteriorated. This is because the ferroelectric capacitor is generally an oxide such as lead zirconate titanate (PZT), and when exposed to such a reducing atmosphere, oxygen in the crystal is desorbed and defects are generated. . As a result, phenomena such as a decrease in remanent polarization, deterioration in fatigue characteristics, and an increase in leak current occur, and it is difficult to obtain a normal operation as a memory after all. In addition, the deterioration due to such a reducing atmosphere is not limited to the hydrogen annealing.
It also occurs during VD.

For this reason, a structure in which the ferroelectric capacitor is covered with a material having a barrier property against hydrogen is particularly effective. As a material for this, Japanese Patent Application Laid-Open No. H7-111318
As described above, SiN, TiN, AlN and the like are effective. FIG. 8 is a structural sectional view of an example in which SiN and AlN are used for the cover film. FIG. 9 shows a structural cross-sectional view particularly around the ferroelectric capacitor.

In the figure, 1 is a silicon substrate, 2 is an element isolation region (SiO ₂ ), 3 is a diffusion layer, 4 is a gate insulating film, 5 is a gate, 6 is an interlayer insulating film under capacitance (BPSG),
7 denotes an Al wiring (laminated structure of Al / TiN / Ti), 8 denotes an interlayer insulating film (NSG) on the capacitor, and 9 denotes a capacitor lower electrode (Pt).
/ Ti laminated structure), 10 is ferroelectric (PZT), 11
Is an upper electrode (Pt), and 12 is a first cover film (Al
N) and 13 are second cover films (SiN). For example, during hydrogen annealing, hydrogen is applied to the ferroelectric 10
Since the ferroelectric capacitor Cf formed by 9 to 11 is covered by the hydrogen cover film 12 on the upper side and 13 by the side, a reducing atmosphere is formed. No deterioration due to On the other hand, the cell transistor Tr is formed by 3 to 5. In this case, if the effect of hydrogen annealing on the recovery of the transistor characteristics becomes insufficient with this structure, for example, the SiN 12 on the gate 4 is partially removed. May be
As a result, sufficient characteristics can be obtained for both Cf and Tr. Here, two types of cover films, SiN and AlN, are used.
This is because SiN cannot be used as a cover film on the upper electrode because it is an insulator, whereas AlN cannot be used for a cover film other than on the upper electrode because it is conductive.

[0008]

Problems of the present structure will be described below. In this structure, SiN is formed as a second cover film on the entire surface after a ferroelectric capacitor composed of 9 to 11 and a first cover film 12 (AlN) is formed. Here, in general, as a method of forming a SiN film, there are methods such as reduced pressure CVD and plasma CVD, and all of these methods use a gas such as silane (SiH ₄ ) or ammonia (NH ₃ ) as a reaction gas. It is usual to do. Each of these gases contains hydrogen, and a reaction in which hydrogen desorbed by a reaction for forming SiN reduces a ferroelectric substance occurs during film formation. Although the upper part of the capacitor is covered with the cover film 12, since there is no cover film especially on the side and lower surfaces of the capacitor, hydrogen enters from here and the ferroelectric material is deteriorated. The lower surface can be covered by a method such as forming a SiN film in advance, but the side surface cannot be covered. Therefore, before the reducing atmosphere after the capacity formation, the Si
The ferroelectric material deteriorates during N film formation. It is also possible to use another method, for example, an RF sputtering method, to form the SiN film. In this case, the deterioration by reduction does not occur, but the film quality of the SiN by this film forming method is lower than that of the CVD method. Since it is not dense, the effect as a hydrogen cover becomes extremely small.

On the other hand, AlN and TiN are, for example, Al and TiN.
Can be formed by reactive sputtering in which nitrogen is sputtered in a nitrogen gas, and in this case, deterioration by hydrogen does not occur.
However, since these materials are conductive as described above, forming them on almost the entire surface of the chip or on the side surface of the capacitor, such as SiN, requires a short circuit between this layer and the Al wiring, an upper electrode and a lower electrode. Is not possible because it causes a short circuit.

Therefore, the capacitance of the present structure has the disadvantage that it is very difficult to produce a device with its effectiveness.

It is an object of the present invention to provide a capacitor having a structure in which characteristics are not deteriorated by a reducing atmosphere after the formation of the capacitor and which are not deteriorated by the reducing atmosphere even in a manufacturing process thereof, and a method of manufacturing the same.

[0012]

The above object is achieved by the following means.

That is, according to the present invention, a first silicon, aluminum or titanium nitride film is formed in a groove formed in an interlayer insulating film on a base semiconductor substrate, and a lower electrode is formed in the groove. , Formed by embedding a dielectric film,
An upper electrode and a second silicon or aluminum or titanium nitride film are formed on the dielectric film. The capacitor and any one of the first silicon, aluminum and titanium on the underlying semiconductor substrate A nitride film is formed, a groove is formed in the nitride film, a lower electrode and a dielectric film are embedded in the groove, and an upper electrode and a second electrode are formed above the dielectric film. The present invention proposes a capacitor characterized by forming a nitride film of silicon, aluminum, or titanium, wherein the lower electrode is electrically connected to a wiring formed thereunder. the underlying semiconductor substrate to an integrated circuit is formed, the material used for the dielectric film _{Pb (Zr 1-x Ti x} ) O
₃ , SrBi ₂ Ta ₂ O ₉ , SrTiO ₃ , (Ba _1-x
Sr _x ) TiO ₃ .

Further, according to the present invention, an interlayer insulating film is formed on a base semiconductor substrate, and after forming a trench in the interlayer insulating film, a first silicon, aluminum or titanium nitride film is formed on the entire surface. , A lower electrode, and a dielectric layer are formed and etched so as to be embedded in the groove, and then an upper electrode, a second silicon, aluminum, or titanium nitride film is formed. A method for manufacturing the capacitor, wherein the trench is formed so that the wiring is partially exposed after the wiring is buried in the interlayer insulating film, and the first nitride layer is After the formation, this is partially etched to partially expose the wiring again, and then performing the steps after the formation of the lower electrode.

Further, according to the present invention, a first silicon, aluminum, or titanium nitride layer is formed on an interlayer insulating film on a base semiconductor substrate, and a groove is formed in the nitride layer.
After forming and etching the lower electrode and the dielectric layer so as to be embedded in the groove, the upper electrode,
A second silicon, aluminum, or titanium nitride film is formed, and the method for manufacturing the capacitor is proposed, wherein the wiring is formed by embedding the wiring in the interlayer insulating film. Forming the nitride layer so that the wiring is partially exposed;
After the wiring is partially exposed, a step after the formation of the lower electrode is performed.

In the present invention, a lower electrode and a dielectric are buried in a trench (groove) previously covered with the first SiN to form a film, and an upper electrode and TiN are formed thereon.
In this structure, the upper, side and lower portions of the capacitor are Ti
Since it is completely covered with N and SiN, and in particular, SiN is formed before the formation of the dielectric, no deterioration due to the SiN film formation occurs, and no deterioration occurs even in the subsequent reducing atmosphere.

[0017]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of the ferroelectric capacitor of the present invention.
Shown in In the drawing, 2 is an element isolation region, 6 is a lower interlayer insulating film, 7 is an Al wiring, 8 is an upper interlayer insulating film, 10
Is a ferroelectric, 11 is an upper electrode, 22 is a first cover film (SiN), 23 is a second cover film (TiN), 24 is a third cover film (SiN), 25 is a plate line, and 26 is a plate line. It is a lower electrode.

FIGS. 2A to 2H and 3I to 3N are sectional views showing the structure of an embodiment of the method for manufacturing a capacitor according to the present invention. First, at a, the interlayer insulating film 6 under the capacitance is formed with the plate line 25 embedded. Next, a trench (trench) is formed in the interlayer insulating film 6 under the capacitance, and after partially exposing the plate line 25, SiN 22 is formed on the entire surface by c. Next, after the SiN 22 is partially etched in the groove by d, the lower electrode 26 of the ferroelectric capacitor is formed on the entire surface by e, and this is etched back by f, and this remains only in the trench portion. Like Further, a film of the ferroelectric substance 10 is formed in the same manner as in step g, and the film is etched back in the same manner as in step h. Next, the upper electrode 1 and TiN 23 are successively formed by i, and etched by using a photoresist or the like as a mask in j, and patterned to cover the ferroelectric 10. In the case of k, a SiN 24 is further formed thereon, in the case of l, a capacitive interlayer insulating film is further formed thereon, and in the case of m, a contact hole to the upper electrode 11 and the plate line 25 is formed. Finally, an Al wiring is formed with n.

[0020]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Example 1 In FIG. 1, 2 is an element isolation region (SiO ₂ ), 6 is an interlayer insulating film under capacitance (BPSG), and 7 is an Al wiring (Al / T
iN / Ti laminated structure), 8 is an interlayer insulating film on a capacitor (NS
G), 10 is a ferroelectric (PZT), 11 is an upper electrode (PZT).
t), 22 is a first cover film (SiN), 23 is a second cover film (TiN), and 24 is a third cover film (SiN).
N), 25 are plate lines (Pt / Ti laminated structure), 2
Reference numeral 6 denotes a capacitance lower electrode (Pt). In this structure, the side surface and the top surface of the ferroelectric capacitor composed of the lower electrode, the ferroelectric, and the upper electrode are covered with the first to third cover films. There is no.

FIGS. 2A to 2H and 3I to 3N are sectional views showing the steps of the manufacturing method according to this embodiment. First, in a,
The lower interlayer insulating film 6 (BPSG) is formed with the plate line (Pt / Ti) 25 embedded. This means, for example, that Pt 200 nm and Ti 20 nm are formed on BPSG,
This is processed by a method such as ion milling and then BP
This is achieved by forming SG. At this time, the thickness of the BPSG on the plate line is about 400 nm. b, a photoresist was used as a mask in the BPSG 6, and CHF ₃ was used as a gas. I. A groove (trench) is formed by a method such as E (reactive ion etching) so that Pt of the plate line is exposed. The width of the groove corresponds to the size of the ferroelectric capacitor. For example, in the case of a ferroelectric memory of about 1 Mbit, it is about 2 μm square. c, SiN
Reference numeral 22 denotes LPCVD (low-pressure CVD) using SiH ₄ and NH _3, which can provide both good step coverage and dense film.
After 50nm approximately deposited on the entire surface by the method equal to the masked photoresist again d, CHF ₃ was used as the gas R. I. Using a method such as E (reactive ion etching), the SiN 22 is partially removed in the groove to expose the Pt of the plate line again. Next, reactive ion etching (e.g., Cl ₂ to this using the resist as a mask, f after 200nm deposited become Pt lower electrode 26 on the entire surface by a method such as DC sputtering of the ferroelectric capacitor in e as a gas ) Or ion milling (using Ar) so that this remains only in the trench portion. g, PZT10 is similarly formed to a thickness of 200 nm by RF sputtering. I. This is etched back by a method such as E. FIGS. 1 and 2 show a shape in which PZT 10 is almost buried in the groove.
Since 0 is entirely removed, it is not always necessary to embed. However, if at least PZT 10 remains on the entire surface of the wafer, it interferes with parts other than the capacity of the device. Therefore, it is necessary to remove PZT 10 from parts other than the predetermined capacity (2 μm square in the above example). In this case, PZT1
A step of forming a mask for etching 0 and then etching the mask is required. Next, at i, Pt11
And TiN23 are each 200 nm, 1
A film is continuously formed to a thickness of 00 nm, and is etched in the same manner as in the lower electrode using a photoresist or the like as a mask in j, and is patterned into a shape covering the PZT 10. At this time, since the size of Pt11 and TiN23 needs to completely cover PZT10, for example, if the groove is 2 μm square,
It is about 2.5 μm square. In k, furthermore, S
iN24 is formed to a thickness of 50 nm by a method such as plasma CVD using SiH ₄ and NH ₃ , and furthermore, NSG8 is further formed thereon.
To C using O ₃ and TEOS (tetraethoxysilane)
VD was deposited to a thickness of 500 nm, and in m, contact holes to the upper and lower electrodes were formed using a resist mask.
R. the F ₃ was used as an etching gas I. E is formed.
Finally, Ti in n, TiN, DC sputtering continuously Al, or after forming by a method such as CVD, using Cl ₂ in a resist mask which R. I. E forms an Al wiring. As described above, the ferroelectric capacitor of this structure is not deteriorated by a reducing atmosphere such as hydrogen annealing. However, in the manufacturing process, it is particularly i that the reducing atmosphere becomes the reducing atmosphere after the ferroelectric is formed. This is a step of forming a SiN film.
covered by iN22, with T
Covered by iN23. Therefore, no deterioration occurs in this step.

Accordingly, in the present embodiment, the deterioration due to reduction does not occur in the manufacturing process, and the deterioration does not occur even in the reducing atmosphere after the capacity is manufactured. For example, even by hydrogen annealing for restoring the characteristics of the cell transistor, no deterioration in the ferroelectric capacitance, for example, a decrease in the remanent polarization or an increase in the leak current occurred at all.

In this embodiment, k is SiN2
After the film No. 4 is formed, the barrier property against the reducing atmosphere becomes particularly high. For example, even when a CVD method using DMAH (dimethyl aluminum hydride) with hydrogen as a carrier gas was used, no capacity deterioration occurred. Therefore, the contact resistance was small for the wiring to the contact hole for the upper electrode and the plate line formed by m, and the defect could be reduced.

Embodiment 2 FIG. 4 is a structural sectional view of another embodiment of the present invention. In this case, the structure is such that SiN 22 is formed on BPSG 8 to a thickness of about 400 nm thicker than in the above-described embodiment, and a trench is formed therein. In this case, there is an effect that the ferroelectric capacitor can be further prevented from undergoing a reduction reaction from the lower part and the side part.

In the present embodiment, unlike the manufacturing method of the first embodiment, a plate line 25 is formed on the BPSG 6, processed, a SiN 22 is formed, and the SiN 22 is partially etched to form a Pt of the plate line 25. To expose.
Subsequent steps can be performed in exactly the same steps as in FIG.

Embodiment 3 FIG. 5 is a structural sectional view of another embodiment of the present invention. In this case, although there is no SiN 24, the effect of the cover in the reducing atmosphere after the capacity formation is inferior to that of the first embodiment due to SiN 22 and TiN 23, but the effect is present. This structure is also effective depending on the degree of the reducing atmosphere in the step after forming the capacitor. Needless to say, the absence of SiN 24 facilitates production.

Embodiment 4 FIG. 6 is a structural sectional view of another embodiment of the present invention. TiN
22 has a shape wider than Pt11. To realize this, in Example 1, Pt11 and TiN22 were used.
Are formed and processed all at once, but the film formation and processing are performed using another mask. In the first to third embodiments, Pt1
Hydrogen may enter from one side, but in this case is completely covered by TiN22. Therefore, the capacity is less deteriorated. A similar structure is also possible in the structures of the second and third embodiments.

[0029]

As described in the above embodiment, according to the capacitor of the present invention and the method of manufacturing the same, a ferroelectric capacitor can be obtained without deterioration due to a reducing atmosphere. Further, the capacity is not deteriorated by the reducing atmosphere after the capacity is formed. Accordingly, a high-performance and highly-reliable memory can be obtained. In the embodiments, the case where a ferroelectric material is used has been described, but it goes without saying that the present invention is also effective when a high dielectric material is used.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of a capacitor structure according to the present invention.

FIGS. 2A to 2H are cross-sectional views illustrating steps of a method for manufacturing a capacitor according to an embodiment of the present invention.

FIGS. 3i to 3n are cross-sectional views showing steps of an embodiment of the method of manufacturing a capacitor according to the present invention.

FIG. 4 is a sectional view of another embodiment of the capacitor structure of the present invention.

FIG. 5 is a cross-sectional view of another embodiment of the capacitor structure of the present invention.

FIG. 6 is a sectional view of another embodiment of the capacitor structure of the present invention.

FIG. 7 is a circuit diagram of an example of a unit cell of a semiconductor memory using a ferroelectric substance.

FIG. 8 is a cross-sectional view of an example of a structure of a conventional semiconductor memory using a capacitor.

FIG. 9 is a cross-sectional view of an example of a conventional capacitor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation region (SiO ₂ ) 3 diffusion layer 4 gate insulating film (SiO ₂ ) 5 gate (polysilicon) 6 capacitive lower interlayer insulating film (BPSG) 7 Al wiring (lamination of Al / TiN / Ti from above) Structure 8 Interlayer insulating film on capacitor (NSG) 9 Lower electrode (Pt / Ti laminated structure from above) (conventional example) 10 Ferroelectric (PZT) 11 Upper electrode (Pt) 12 First cover film (AlN) (Conventional example) 13 Second cover film (SiN) (Conventional example) 22 First cover film (SiN) (Invention) 23 Second cover film (TiN) (Invention) 24 Third cover film (Invention) SiN) (Invention) 25 Plate line (Pt / Ti laminated structure from above) 26 Lower electrode (Pt) (Invention)

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (9)

[Claims] A first silicon, aluminum, or titanium nitride film is formed in a groove formed in the interlayer insulating film on the base semiconductor substrate; and a lower electrode is formed in the groove.
A capacitor formed by burying a dielectric film, wherein an upper electrode and a second silicon, or aluminum or titanium nitride film are formed on the dielectric film. 2. A first nitride film of any of silicon, aluminum and titanium is formed on a base semiconductor substrate, a groove is formed in the nitride film, and a lower electrode and a dielectric film are formed in the groove. A capacitor formed by being buried, wherein an upper electrode and a second silicon, aluminum, or titanium nitride film are formed on the dielectric film. 3. The capacitor according to claim 1, wherein the lower electrode is electrically connected to a wiring formed below the lower electrode. 4. The capacitor according to claim 1, wherein an integrated circuit is formed on the base semiconductor substrate. 5. The material used for the dielectric layer is Pb
(Zr_1-x Ti_x ) O _Three , SrBi_Two Ta_Two O₉ , Sr
TiO_Three , (Ba_1-x Sr_x ) TiO_Three Including any of
The capacity according to any one of claims 1 to 3. 6. An interlayer insulating film is formed on a base semiconductor substrate, a trench is formed in the interlayer insulating film, and then a first silicon, aluminum, or titanium nitride film is formed on the entire surface, and then a lower electrode is formed. Forming the upper electrode and the second silicon, aluminum, or titanium nitride film after forming and etching each of the dielectric layers so as to be embedded in the groove. Method. 7. The method according to claim 1, wherein the first insulating film is formed on the interlayer insulating film on the underlying semiconductor substrate.
A nitride layer of any one of silicon, aluminum and titanium was formed, a groove was formed in the nitride layer, and a lower electrode and a dielectric layer were formed and etched so as to be embedded in the groove. 4. The method according to claim 2, wherein an upper electrode, a second silicon, aluminum or titanium nitride film is formed thereafter. 8. After the wiring is embedded in the interlayer insulating film, the trench is formed so that the wiring is partially exposed, and the trench is partially formed after the first nitride layer is formed. 7. A step subsequent to the formation of the lower electrode is performed after the wiring is partially exposed and the wiring is partially exposed again.
Manufacturing method of the described capacity. 9. The method according to claim 9, further comprising: forming the wiring by embedding the wiring in the interlayer insulating film; forming the first nitride layer; forming the groove so that the wiring is partially exposed; 8. The method for manufacturing a capacitor according to claim 7, wherein the steps subsequent to the formation of the lower electrode are performed after the partial exposure.