KR20010113271A - Method for forming ferroelectric capacitor capable of preventing the short fail between the upper electrode and bottom electrode - Google Patents
Method for forming ferroelectric capacitor capable of preventing the short fail between the upper electrode and bottom electrode Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000003990 capacitor Substances 0.000 title claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910020177 SiOF Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000002425 crystallisation Methods 0.000 abstract description 4
- 230000008025 crystallization Effects 0.000 abstract description 4
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- 238000005498 polishing Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 68
- 239000010410 layer Substances 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
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- 239000003595 mist Substances 0.000 description 1
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
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Abstract
본 발명은 강유전체막의 결정화 공정에 따른 표면 거칠기 증가에 의해 캐패시터 상하부 전극간의 단락이 발생하는 것을 효과적으로 방지할 수 있는 강유전체 캐패시터 제조 방법에 관한 것으로, 하부전극을 이루는 전도층 상에 강유전체막을 형성하고, 열처리를 실시한 다음 평탄화용 유전막을 형성한 다음, 평탄화용 유전막을 건식식각, 습식식각 및 화학기계적 연마 등의 방법으로 제거하여 열처리에 의해 표면이 거칠어진 강유전체막 표면을 보상하는데 특징이 있다. 즉, 강유전 특성 확보를 위한 열처리 과정에서 거칠어진 강유전체막 표면에 평탄화용 유전막을 형성하여 강유전체막 표면의 취약한 부분인 홈을 채움으로써 상하부 전극간의 단락 발생을 방지한다.The present invention relates to a method of manufacturing a ferroelectric capacitor that can effectively prevent the occurrence of a short circuit between the upper and lower electrodes of the capacitor due to the increase in the surface roughness according to the crystallization process of the ferroelectric film. Next, the planarization dielectric film is formed, and then the planarization dielectric film is removed by dry etching, wet etching, and chemical mechanical polishing to compensate for the surface of the ferroelectric film whose surface is roughened by heat treatment. That is, a planarization dielectric film is formed on the roughened ferroelectric film surface during the heat treatment process to secure ferroelectric properties, thereby filling a groove, which is a weak portion of the ferroelectric film surface, to prevent a short circuit between the upper and lower electrodes.
Description
본 발명은 강유전체 메모리 소자 제조 방법에 관한 것으로, 특히 강유전체 메모리 소자의 결정화에 따른 상하부 전극간의 단락 발생을 방지할 수 있는 강유전체 메모리 소자 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a ferroelectric memory device, and more particularly, to a method of manufacturing a ferroelectric memory device capable of preventing a short circuit between upper and lower electrodes caused by crystallization of a ferroelectric memory device.
반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.
FeRAM의 축전물질로는 SriBijTa2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.As the storage material of FeRAM, Sr i Bi j Ta 2 O 9 (hereinafter SBT) and Pb (Zr, Ti) O 3 (hereinafter PZT) thin films are mainly used. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
첨부된 도면 도1은 종래 기술에 따른 FeRAM 소자 제조 공정 단면도로서, 게이트 절연막(12)과 게이트 전극(13) 그리고 소오스·드레인(14)으로 이루어지는 트랜지스터 형성이 완료된 반도체 기판(10)을 덮는 제1 층간절연막(15) 내에 콘택홀을 형성하고, 상기 콘택홀을 통하여 트랜지스터의 소오스·드레인(14)과 연결되는 비트라인(16)을 형성한 다음, 비트라인(16) 형성이 완료된 전체 구조 상에 제2 층간절연막(17)을 형성하고, 제2 층간절연막(17) 상에 접착층(18)을 형성하고, 접착층(18) 상에 하부전극(19), 강유전체막(20)) 및 상부전극(21)으로 이루어지는 캐패시터를 형성하고, 전체 구조 상에 캐패시터를 덮는 제3 층간절연막(22)을 형성하고, 캐패시터의 상부전극을 노출시키는 콘택홀과 반도체 기판(10)에 형성된 소오스·드레인(14)을 노출시키는 콘택홀을 형성한 후, 캐패시터와 트랜지스터를 연결하는 금속배선 및 캐패시터와 플레이트 라인(도시하지 않음)을 연결하는 금속배선(23)을 형성한 상태를 보이고 있다.1 is a cross-sectional view of a manufacturing process of a FeRAM device according to the prior art, and includes a first semiconductor layer 10 covering a transistor formed of a gate insulating film 12, a gate electrode 13, and a source drain 14. A contact hole is formed in the interlayer insulating film 15, and a bit line 16 connected to the source and drain 14 of the transistor is formed through the contact hole, and then on the entire structure where the bit line 16 is formed. A second interlayer insulating film 17 is formed, an adhesive layer 18 is formed on the second interlayer insulating film 17, and a lower electrode 19, a ferroelectric film 20, and an upper electrode (on the adhesive layer 18) are formed. A capacitor formed of 21), a third interlayer insulating film 22 covering the capacitor on the entire structure, and a contact hole for exposing the upper electrode of the capacitor and a source drain 14 formed in the semiconductor substrate 10; Forming a contact hole exposing the , Showing a state of forming a capacitor with metal wirings and the capacitor plate and the line connecting the transistor (not shown), the metal wire 23 connecting the.
전술한 바와 같은 FeRAM 소자 제조 공정에서는 캐패시터의 강유전체 재료로서 PZT, SBT 등이 사용되는데, 이들 재료의 강유전 특성을 얻기 위해서는 증착 후 고온 열처리 공정이 필수적으로 수반되어야 한다. 그런데, 상기 고온 열처리 공정 중에 입자의 성장이 함께 일어나 도 1의 'A' 부분 확대도인 도 2에서 보이는 바와 같이 표면 거칠기가 크게 증가한다. 이와 같이 표면 거칠기가 증가한다는 것은 강유전체 막에서 국부적으로 두께가 매우 얇은 부분이 발생하거나, 심할 때에는 하부전극이 드러나는 경우가 발생한다는 것을 의미한다. 따라서, 상부전극과 하부전극이 연결되는 단락 불량(short fail)이 유발되거나, 낮은 동작 전압에서도 누설전류가 매우 커지는 현상이 발생한다. 즉, 소자 제조시 캐패시터의 신뢰성을 저하시키고 수율을 감소시키는 중요한 요인으로 작용한다.In the FeRAM device fabrication process as described above, PZT, SBT, and the like are used as ferroelectric materials of the capacitor. In order to obtain ferroelectric properties of these materials, a high temperature heat treatment process after deposition must be accompanied. However, as the particles grow together during the high temperature heat treatment process, the surface roughness is greatly increased as shown in FIG. This increase in surface roughness means that a locally thin portion of the ferroelectric film is generated or, in severe cases, a lower electrode is exposed. Accordingly, a short fail between the upper electrode and the lower electrode is caused, or a leakage current becomes very large even at a low operating voltage. That is, the device serves as an important factor in reducing the reliability of the capacitor and reducing the yield.
상기와 같은 문제점을 해결하기 위한 본 발명은 강유전체막의 결정화 공정에 따른 표면 거칠기 증가에 의해 캐패시터 상하부 전극간의 단락이 발생하는 것을 효과적으로 방지할 수 있는 강유전체 캐패시터 제조 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems is to provide a method of manufacturing a ferroelectric capacitor that can effectively prevent the occurrence of a short circuit between the upper and lower electrodes of the capacitor due to the increase in the surface roughness according to the crystallization process of the ferroelectric film.
도 1은 종래 기술에 따른 강유전체 메모리 소자 제조 공정 단면도,1 is a cross-sectional view of a ferroelectric memory device manufacturing process according to the prior art;
도 2는 도 1의 'A' 부분 확대 단면도,2 is an enlarged cross-sectional view 'A' of FIG.
도 3a 내지 도 3d는 본 발명의 실시 예에 따른 강유전체 캐패시터 형성 공정 단면도.3A to 3D are cross-sectional views of a ferroelectric capacitor forming process according to an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
33: 제1 전도막 33A: 하부전극 패턴33: first conductive film 33A: lower electrode pattern
34: 강유전체막 34A: 강유전체막 패턴34: Ferroelectric film 34A: Ferroelectric film pattern
35: 유전막 36: 상부전극35: dielectric layer 36: upper electrode
상기와 같은 목적을 달성하기 위한 본 발명은 하부전극을 이루는 제1 전도막을 형성하는 제1 단계; 상기 하부전극 상에 강유전체막을 형성하는 제2 단계; 상기 강유전체막의 결정화를 위한 열처리를 실시하는 제3 단계; 상기 강유전체막 상에 유전막을 형성하는 제4 단계; 상기 강유전체막이 노출될 때까지 상기 유전막을 제거하여 상기 강유전체막 표면의 홈 내에 상기 유전막을 잔류시켜 상기 강유전체막 표면을 평탄화시키는 제5 단계; 및 상기 제5 단계가 완료된 상기 강유전체막 상에 상부전극을 이루는 제2 전도막을 형성하는 제6 단계를 포함하는 강유전체 캐패시터 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a first conductive film forming a lower electrode; Forming a ferroelectric film on the lower electrode; A third step of performing a heat treatment for crystallizing the ferroelectric film; Forming a dielectric film on the ferroelectric film; Removing the dielectric film until the ferroelectric film is exposed, thereby leaving the dielectric film in the groove of the ferroelectric film surface to planarize the ferroelectric film surface; And a sixth step of forming a second conductive film forming an upper electrode on the ferroelectric film in which the fifth step is completed.
본 발명은 하부전극을 이루는 전도층 상에 강유전체막을 형성하고, 열처리를 실시한 다음 평탄화용 유전막을 형성한 후, 평탄화용 유전막을 건식식각, 습식식각 및 화학기계적 연마 등의 방법으로 제거하여 열처리에 의해 표면이 거칠어진 강유전체막 표면을 보상하는데 특징이 있다. 즉, 강유전 성질 확보를 위한 열처리 과정에서 거칠어진 강유전체막 표면에 평탄화용 유전막을 형성하여 강유전체막 표면의 취약한 부분인 홈을 채움으로써 상하부 전극간의 단락 발생을 방지한다.The present invention forms a ferroelectric film on the conductive layer forming the lower electrode, heat treatment, and then forming a planarization dielectric film, and then removing the planarization dielectric film by dry etching, wet etching, chemical mechanical polishing, or the like by heat treatment. It is characterized by compensating the surface of the ferroelectric film whose surface is rough. That is, a flattening dielectric film is formed on the roughened ferroelectric film surface during the heat treatment process to secure ferroelectric properties, thereby filling a groove, which is a weak portion of the ferroelectric film surface, to prevent short circuit between the upper and lower electrodes.
상기 평탄화용 유전막은 수소에 의한 캐패시터의 전기적 특성 열화를 발생시키지 않는 SiOx산화막, SiOF, Al2O3또는 BPSG(borophosphosilicate glass) 등으로 형성한다.The planarization dielectric film is formed of SiO x oxide film, SiOF, Al 2 O 3, or borophosphosilicate glass (BPSG) which does not cause deterioration of the electrical characteristics of the capacitor by hydrogen.
이하, 첨부된 도면 도 3a 내지 도 3d를 참조하여 본 발명의 실시예에 따른 강유전체 캐패시터 형성 방법을 상세하게 설명한다.Hereinafter, a method of forming a ferroelectric capacitor according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3D.
먼저 도 3a에 도시한 바와 같이 트랜지스터 등의 하부구조(도시하지 않음) 형성이 완료된 반도체 기판(30) 상에 층간절연막(31)을 형성하고, 상기 층간절연막(31) 상에 접착층(32)을 형성하고, 접착층(32) 상에 하부전극을 이룰 제1 전도막(33)을 형성하고, 제1 전도막(33) 상에 SBT(SrBi2Ta2O9), SBTN(SrxBi2-y(Ta1-zNbz)2O9), PZT(Pb(ZrxTi1-x)O3) 또는 BLT(Bi4-xLaxTi3O12)으로 100 Å 내지 5000 Å 두께의 강유전체막(34)을 형성한다. 이때, 강유전체막(34)은 화학기상증착법(chemical vapor deposition, CVD), 물리기상증착법(physical vapor deposition, PVD), LSMCD(liquid source mist chemical deposition), 스핀-온(spin-on) 또는 MOD(metal organic deposition) 방법을 이용하여 형성한다.First, as shown in FIG. 3A, an interlayer insulating layer 31 is formed on a semiconductor substrate 30 on which a substructure (not shown) such as a transistor is formed, and an adhesive layer 32 is formed on the interlayer insulating layer 31. A first conductive layer 33 to form a lower electrode on the adhesive layer 32, and SBT (SrBi 2 T a 2 O 9 ) and SBTN (Sr x Bi 2− ) formed on the first conductive layer 33. y (Ta 1-z Nb z ) 2 O 9 ), PZT (Pb (Zr x Ti 1-x ) O 3 ) or BLT (Bi 4-x La x Ti 3 O 12 ), 100 Å to 5000 Å thick A ferroelectric film 34 is formed. In this case, the ferroelectric film 34 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), liquid source mist chemical deposition (LSMCD), spin-on or MOD ( Form using metal organic deposition.
이어서, 강유전체상의 결정화를 위하여 O2, N2, Ar, O3, He, Ne 또는 Kr 분위기에서 500 ℃ 내지 800 ℃ 온도 조건으로 10분 내지 5시간 동안 열처리 공정을 실시한다. 이와 같은 열처리 공정에서 결정 성장이 일어나 도 3a에 보이는 바와 같이 강유전체막(34) 표면이 거칠어진다. 즉, 표면에 홈이 산재하게 된다.Subsequently, for the crystallization of the ferroelectric phase, a heat treatment process is performed for 10 minutes to 5 hours at a temperature of 500 ° C. to 800 ° C. in an O 2 , N 2 , Ar, O 3 , He, Ne, or Kr atmosphere. Crystal growth occurs in the heat treatment process, such that the surface of the ferroelectric film 34 becomes rough as shown in FIG. 3A. That is, grooves are scattered on the surface.
다음으로, 표면이 거칠어진 강유전체막(34)을 평탄화시키고 그 표면의 취약한 부분인 홈을 메우기 위해, 도 3b에 도시한 바와 같이 강유전체막(34) 상에 100 Å 내지 5000 Å 두께의 유전막(35)을 형성한다.Next, in order to planarize the roughened ferroelectric film 34 and fill the groove which is a weak portion of the surface thereof, as shown in FIG. 3B, the dielectric film 35 having a thickness of 100 to 5000 상 에 on the ferroelectric film 34 is shown. ).
상기 평탄화용 유전막은 O3-TEOS(tetraethyl orthosilicate glass)로 증착한 SiOx막, BPSG막, SiOF막, Al2O3막, Ta2O5막 또는 TiO2막과 같이 다양한 종류 막으로 이루어지며, 증착방법으로는 CVD, PVD 또는 스핀-온 방법을 이용한다. 특히, BPSG막을 이용하는 경우에는 BPSG막 형성 후 O2, N2, Ar, O3, He, Ne 또는 Kr 분위기에서 400 ℃ 내지 850 ℃ 온도로 5분 내지 2 시간 동안 열처리를 실시한다.The planarization dielectric film is made of various kinds of films such as SiO x film, BPSG film, SiOF film, Al 2 O 3 film, Ta 2 O 5 film or TiO 2 film deposited with O 3 -TEOS (tetraethyl orthosilicate glass). As the deposition method, a CVD, PVD or spin-on method is used. In particular, in the case of using the BPSG film, after the formation of the BPSG film, heat treatment is performed at 400 ° C. to 850 ° C. for 5 minutes to 2 hours in an O 2 , N 2 , Ar, O 3 , He, Ne, or Kr atmosphere.
이어서 건식식각, 습식식각 또는 산화막 식각제를 이용한 화학기계적 연마 공정으로 유전막(35)을 제거한다. 즉, 도 3c에 도시한 바와 같이 강유전체막(34) 표면의 홈 부분에만 유전막(35)이 잔류되도록 하여 강유전체막(34) 표면을 평탄화시킨다. 이러한 유전막(35) 제거 공정에서 너무 적게 유전막(35)을 제거하면 강유전 특성이 없는 유전막(35)이 강유전체막(34) 상에 과다하게 잔류하게 되어 캐패시터의 전기적 특성을 저하시키게 되고, 너무 많이 제거하면 강유전체막(35) 표면의 평탄화를 의도하는 본 발명의 목적을 이룰 수 없게 된다. 따라서, 본 발명은 강유전체막(34) 표면이 노출될 때까지 유전막(35)을 제거하여 거칠어진 강유전체막(34) 표면에 형성된 홈 내에 유전막(35)을 잔류시킴으로써 강유전체막(34) 표면을 평탄화시키고 취약한 부분을 보상하는데 그 특징이 있다.Subsequently, the dielectric layer 35 is removed by a chemical mechanical polishing process using dry etching, wet etching, or an oxide etchant. That is, as shown in FIG. 3C, the surface of the ferroelectric film 34 is planarized by allowing the dielectric film 35 to remain only in the groove portion of the surface of the ferroelectric film 34. When the dielectric film 35 is removed in such a process that the dielectric film 35 is removed, the dielectric film 35 having no ferroelectric property is excessively left on the ferroelectric film 34, thereby deteriorating the electrical characteristics of the capacitor. If the surface of the ferroelectric film 35 is planarized, the purpose of the present invention is not achieved. Accordingly, in the present invention, the surface of the ferroelectric film 34 is planarized by removing the dielectric film 35 until the surface of the ferroelectric film 34 is exposed to leave the dielectric film 35 in the groove formed on the roughened surface of the ferroelectric film 34. It is characteristic to make up for and to compensate for the weak points.
다음으로 도 3d에 도시한 바와 같이 강유전체막(34) 상에 캐패시터의 상부전극(36)을 형성하고, 이어서 강유전체막(34), 전도막(33) 및 접착층(32)을 식각하여 강유전체막 패턴(34A), 하부전극(34A) 및 접착층(32A) 패턴을 형성한다.Next, as shown in FIG. 3D, the upper electrode 36 of the capacitor is formed on the ferroelectric film 34, and then the ferroelectric film 34, the conductive film 33, and the adhesive layer 32 are etched to form a ferroelectric film pattern. A pattern 34A, a lower electrode 34A, and an adhesive layer 32A are formed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 유전막으로서 거칠어진 강유전체막의 표면을 채워 강유전체막 표면을 매립하고 그에 따라 평탄화시킴으로써 강유전체 캐패시터의 상부전극과 하부전극간의 단락을 효과적으로 방지할 수 있다. 이에 따라 강유전체 메모리 소자의 신뢰성 및 제조 수율 향상을 기대할 수 있다.The present invention as described above can fill the surface of the rough ferroelectric film as a dielectric film to fill the surface of the ferroelectric film and planarize accordingly, thereby effectively preventing a short circuit between the upper electrode and the lower electrode of the ferroelectric capacitor. Accordingly, the reliability and manufacturing yield of the ferroelectric memory device can be expected.
Claims (10)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010010169A (en) * | 1999-07-16 | 2001-02-05 | 윤종용 | Ferroelectric memory having a dielectric layer of SiOF and Method for fabricating the dielectric layer |
| KR100728146B1 (en) * | 2005-01-06 | 2007-06-13 | 후지쯔 가부시끼가이샤 | Method for fabricating semiconductor device |
| US7585683B2 (en) | 2006-07-18 | 2009-09-08 | Samsung Electronics Co., Ltd. | Methods of fabricating ferroelectric devices |
| KR101016950B1 (en) * | 2003-12-29 | 2011-02-25 | 주식회사 하이닉스반도체 | Fabricating method of ferroelectric capacitor in semiconductor device |
-
2000
- 2000-06-19 KR KR1020000033537A patent/KR20010113271A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010010169A (en) * | 1999-07-16 | 2001-02-05 | 윤종용 | Ferroelectric memory having a dielectric layer of SiOF and Method for fabricating the dielectric layer |
| KR101016950B1 (en) * | 2003-12-29 | 2011-02-25 | 주식회사 하이닉스반도체 | Fabricating method of ferroelectric capacitor in semiconductor device |
| KR100728146B1 (en) * | 2005-01-06 | 2007-06-13 | 후지쯔 가부시끼가이샤 | Method for fabricating semiconductor device |
| US7585683B2 (en) | 2006-07-18 | 2009-09-08 | Samsung Electronics Co., Ltd. | Methods of fabricating ferroelectric devices |
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