KR19990085671A - Etching method of metal wiring to prevent damage of ferroelectric capacitor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method for preventing damage to a capacitor generated when a metal wiring connected to a ferroelectric capacitor is formed by plasma etching. In the plasma etching method of forming a metal wiring connected to the ferroelectric capacitor, the plasma etching is a mixed gas of BCl ₃ and Cl ₂ , a flow rate of 30-70 sccm, a pressure of 10-30 mTorr, RF power of 60-80 watt And power and an ECR plasma etcher under conditions of Mg current in the range of 100-300 mA.

Description

Etching method of metal wiring to prevent damage of ferroelectric capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method for preventing damage to a capacitor generated when a metal wiring connected to a ferroelectric capacitor is formed by plasma etching.

As the integration and miniaturization of dynamic random access memory (DRAM) devices is progressing, the area of a capacitor storing information is gradually decreasing. In order to secure the required capacitance of the capacitor, the capacitor constituting the memory cell has been changed to a three-dimensional structure. Representative examples are trench capacitors, cylinder capacitors, fin capacitors, and the like. The three-dimensionalization of the memory capacitor structure increases the number of processes in the manufacturing process, and puts a huge burden on technology development.

The stacking capacitor of the DRAM memory cell capacitor is the most preferable form in consideration of various process conditions. However, since the area of the capacitor has already been reduced, the minimum capacitance is secured with a dielectric film of silicon dioxide (SiO ₂ ) or a laminate of silicon dioxide and nitride (SiO ₂ / Si ₃ N ₄ ). Can not.

In order to solve this problem, high dielectric constant materials (BST, STO) having a dielectric constant of 400 to 1000 times or more than those of the above dielectric films using silicon dioxide or nitride, or having a residual polarization even after the electric field is removed A method of using ferroelectric materials (PZT, YI, etc.) has been proposed. In particular, the device using the ferroelectric material has emerged as a next-generation memory device because it has a non-volatile that retains the charge even after removing the electric field after applying an electric field to the capacitor.

However, due to process induced damage occurring in a subsequent manufacturing process, the residual polarization characteristic of the capacitor deteriorates and the distribution thereof becomes worse. In particular, the current data processing scheme is a scheme that compares the residual polarization value Pr (Rement Polarization) of the capacitor in the reference cell and the capacitor in the memory cell and recognizes the difference. As the uniformity of Pr deteriorates, the sensing margin decreases, which significantly affects the yield of the device.

Among them, in order to solve the charging problem caused by the etching process for forming the metal wiring, in the case of a CMOS device, a method of recovering deterioration of the gate oxide film by performing heat treatment using hydrogen (H ₂ ) gas However, ferroelectrics such as PZT have a problem of deterioration due to heat treatment in a reducing atmosphere, and thus are difficult to apply. In addition, the increase of the process step also causes the problem of increased cost and air.

An object of the present invention is to optimize the etching process of the metal wiring connected to the electrode of the ferroelectric capacitor to improve the uniformity of the residual polarization value to prevent the damage of the capacitor generated when forming the metal wiring connected to the ferroelectric capacitor by plasma etching It is to provide a wiring forming method.

1 is a cross-sectional view illustrating a metal wiring connected to a ferroelectric capacitor.

FIG. 2 is a graph illustrating a distribution characteristic of a residual polarization value Pr according to a split of an etching element.

In order to achieve the above object, the metal wiring forming method according to the present invention is to form a metal wiring connected to the ferroelectric capacitor by a plasma etching method, the plasma etching is a mixed gas of BCl ₃ and Cl ₂ , 30-70 Characterized in an ECR plasma etch under conditions of flow rate of sccm, pressure of 10-30 mTorr, RF power and power of 60-80 watt and Mg current in the range of 100-300mA.

In this case, the ferroelectric capacitor is formed of any one of a platinum group metal composed of Pt, Ir, Rh and Ru and an oxide electrode composed of IrO ₂ , RuO ₂ and RhO ₂ , and the ferroelectric layer includes PZT, PLZT, and PNZT. And ferroelectric materials such as Y1.

In addition, the metal wiring is formed by a photolithography process using a photoresist. The metal wiring is an ohmic layer having a thickness of about 300 kPa to about 500 kPa of titanium (Ti), a barrier metal layer of about 900 kV to about 1,500 kPa of titanium nitride (TiN) D, and a thickness of about 4,000 kPa to 8,000 kPa. It is formed in a structure in which an antireflection film having a thickness of about 200 mW to 500 mW made of an aluminum layer and titanium nitride is laminated.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the etching method of the metal wiring to prevent damage to the ferroelectric capacitor according to the present invention.

In the case of a general CMOS process, it has been reported that the gate oxide film deteriorates V _TH shift, Qbd lowering, or CV characteristics due to process induced damage during subsequent processes. It is known that the main cause is charging by plasma during dry etching of the metal wiring connected to the gate electrode. If the plasma is not uniform, non-uniformity of ion current and electron current occurs locally in the wafer, and to compensate for this, current is generated in the form of FN tunneling through the gate oxide film. This damages the gate oxide film.

Therefore, in order to improve the reliability of the gate oxide film, the uniformity of the plasma through the modification of the etcher, that is, the hardware, is improved, and the protection diode is applied at the design stage of the device. The installation of the current path was made mainly.

From the viewpoint of improving the uniformity of the plasma, it can be said that process optimization within the range that does not lose the basic characteristics of the process conditions is essential.

1 is a cross-sectional view illustrating a metal wiring connected to a ferroelectric capacitor, in which reference numeral 10 denotes a semiconductor substrate, 12 denotes a lower electrode, 14 denotes a dielectric film, 16 denotes an upper electrode, and 18 Indicates a TiO ₂ insulating film, "20" indicates an interlayer insulating layer, and "22" indicates a metal wiring.

The lower electrode 12 and the upper electrode 16 are formed of a platinum group metal such as Pt, Ir, Rh or Ru, or an oxide electrode such as IrO ₂ , RuO _2, or RhO ₂ , and the dielectric layer 14 is formed of PZT, It is formed of a ferroelectric material such as PLZT, PNZT or Y1.

The metal wire 22 is formed by a photolithography process using a photoresist.

The metal wiring 22 is an ohmic layer having a thickness of about 300 kV to 500 kPa of titanium (Ti), a barrier metal layer of about 900 kV to about 1,500 kPa of titanium nitride (TiN) D, and 4,000 kPa to 8,000 kPa It is formed in a structure in which an aluminum layer having a thickness of about a thickness and an antireflection film having a thickness of about 200 kPa to 500 kPa of titanium nitride are laminated.

In the case of the FRAM, the upper electrode 16 of the capacitor is connected to the metal wire 22 through a metal contact or via contact. At this time, the metal wiring 22 is damaged by the plasma charging during dry etching. As mentioned above, in the case of the FRAM, a sensing configuration in which the residual polarization value Pr of the capacitor of the reference cell and the memory cell is compared is taken. The uniformity of is very important. Therefore, Pr uniformity is improved by optimizing the process conditions.

FIG. 2 is a graph illustrating a distribution characteristic of a residual polarization value Pr according to a split of an etching element.

Plasma charging effect of the ECR type plasma etcher was investigated by dividing the pressure, RF power and magnetic current parameters for the metal etching process through the distribution of Pr values. The mean value of Pr was not significantly different according to the change of each factor. However, the standard deviation is improved when the pressure and RF power are high and the magnetic current is low.

That is, the standard deviation is a condition of a mixed gas of BCl ₃ and Cl ₂ , flow rate of 30-70 sccm, pressure of 10-30 mTorr, RF power and power of 60-80 watt and Mg current in the range of 100-300mA, It can be seen that the most improved when performed in an ECR plasma etcher.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

According to the etching method of the metal wiring to prevent the damage of the ferroelectric capacitor according to the present invention, it is possible to prevent the damage of the capacitor generated when forming the metal wiring connected to the ferroelectric capacitor by plasma etching by adjusting the plasma etching conditions.

Claims (5)

In forming a metal wiring connected to the ferroelectric capacitor by a plasma etching method, The plasma etching is performed under the conditions of a mixed gas of BCl ₃ and Cl ₂ , a flow rate of 30-70 sccm, a pressure of 10-30 mTorr, RF power and power of 60-80 watt and a Mg current in the range of 100-300 mA. Etching method of metal wiring for preventing damage to ferroelectric capacitor, characterized in that performed in a plasma etcher. The method of claim 1, The ferroelectric capacitor is formed of any one of a platinum group metal composed of Pt, Ir, Rh, and Ru and an oxide electrode composed of IrO ₂ , RuO _2, and RhO ₂ , and the ferroelectric films include PZT, PLZT, PNZT, and Y1. Etching method of the metal wiring for preventing damage to the ferroelectric capacitor, characterized in that formed by any one of the ferroelectric materials. The method of claim 1, The metal wiring is an etching method of the metal wiring to prevent damage to the ferroelectric capacitor, characterized in that formed by a photolithography process using a photoresist. The method of claim 1, The metal wiring is formed of a structure in which an ohmic layer made of titanium (Ti), a barrier metal layer made of titanium nitride (TiN) D, and an antireflection film made of aluminum and titanium nitride are formed in a stacked structure. Etching method of metal wiring to prevent damage. The method of claim 4, wherein The ohmic layer has a thickness of about 300 kPa to 500 kPa, the barrier metal layer is about 900 kPa to about 1500 kPa, the aluminum layer is about 4,000 kPa to about 8,000 kPa, and the anti-reflection film is about 200 kPa to about 500 kPa. Etching method of metal wiring for preventing damage to the ferroelectric capacitor, characterized in that forming.