KR20040102403A - Method of manufacturing FeRAM device - Google Patents
Method of manufacturing FeRAM device Download PDFInfo
- Publication number
- KR20040102403A KR20040102403A KR1020030033770A KR20030033770A KR20040102403A KR 20040102403 A KR20040102403 A KR 20040102403A KR 1020030033770 A KR1020030033770 A KR 1020030033770A KR 20030033770 A KR20030033770 A KR 20030033770A KR 20040102403 A KR20040102403 A KR 20040102403A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- film
- gas
- etching
- interlayer insulating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 강유전성램 소자의 제조에 관한 것으로, 보다 상세하게는, 금속배선을 노출시키는 층간절연막 식각시에 유발되는 플라즈마 데미지를 방지하기 위한 강유전성램 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of ferroelectric ram devices, and more particularly, to a method of manufacturing ferroelectric ram devices for preventing plasma damage caused during etching of an interlayer insulating film exposing a metal wiring.
강유전성램(Ferroelectric RAM: 이하 FeRAM) 소자는 디램(DRAM) 소자와는 달리 전원의 온/오프(On/Off)에 관계없이 데이터를 저장하는 비휘발성(Non-Volatile) 메모리 소자이다. 이러한 FeRAM 소자는 캐패시터 형성시에 통상의 유전 물질 대신에 강유전성 물질을 이용하며, 아울러, 전극 물질 또한 디램 소자의 그것과는 다른물질을 사용한다. 예컨데, FeRAM 소자의 캐패시터에 있어서, 강유전성 물질로서는 SBT(SrBi2Ta2O9) 또는 BLT(Bi3.3La0.8Ti3O12) 등을 사용하며, 전극 물질로서는 Pt, Ir, IrO2, Ru 또는 RuO2 등을 사용한다.Ferroelectric RAM (FeRAM) devices, unlike DRAM devices, are non-volatile memory devices that store data regardless of whether the power is turned on or off. Such FeRAM devices use ferroelectric materials instead of conventional dielectric materials when forming capacitors, and in addition, electrode materials also use materials different from those of DRAM devices. For example, in the capacitor of the FeRAM device, SBT (SrBi 2 Ta 2 O 9 ) or BLT (Bi 3.3 La 0.8 Ti 3 O 12 ) or the like is used as the ferroelectric material, and Pt, Ir, IrO 2, Ru, or RuO 2 is used as the electrode material. Etc.
그런데, 상기 강유전성 물질인 SBT 또는 BLT는 디램 소자의 유전 물질인 ONO 또는 Ta2O5등 보다 플라즈마 데미지(plasma damage)에 매우 취약한 특성을 나타낸다. 이것은 FeRAM 소자의 강유전체로 사용되는 SBT 또는 BLT 등이 자발분극 특성을 나타내고, FeRAM 자체가 그러한 특성을 이용한 소자이기 때문이다.However, the ferroelectric material SBT or BLT is more susceptible to plasma damage than ONO or Ta 2 O 5 , which is a dielectric material of the DRAM device. This is because SBT or BLT used as ferroelectric for FeRAM devices exhibits spontaneous polarization characteristics, and FeRAM itself is a device using such characteristics.
이에 따라, FeRAM 소자를 제조함에 있어서, 식각 공정에서 유발되는 플라즈마 데미지, 특히, 전하 축적(charge build up)에 의한 전기적 데미지의 문제는 소자 특성 및 수율을 결정하는데 중요한 변수로 부각되고 있다.Accordingly, in manufacturing a FeRAM device, a problem of plasma damage caused by an etching process, in particular, electrical damage due to charge build up, has emerged as an important variable in determining device characteristics and yield.
한편, 식각 공정에서 유발된 플라즈마 데미지는 후속의 고온 열처리를 통해 회복(recovery)시킬 수 있으며, 그래서, 통상의 FeRAM 소자 제조시에는 식각 공정 후에 고온 열처리를 행하고 있다.On the other hand, the plasma damage caused in the etching process can be recovered through the subsequent high temperature heat treatment, and thus, in manufacturing a typical FeRAM device, the high temperature heat treatment is performed after the etching process.
그러나, 금속배선 공정 이전의 공정에서 유발된 플라즈마 데미지는 고온 열처리를 통하여 모두 회복시킬 수 있지만, 상기 금속배선 공정 이후의 식각 공정에서 금속배선이 노출되면서 발생된 플라즈마 데미지는 금속배선 재료인 알루미늄의 특성상 고온 열처리가 불가능한 것과 관련해서 실질적으로 그 회복이 어렵다.However, although the plasma damage caused in the process before the metal wiring process can be recovered through high temperature heat treatment, the plasma damage generated by the exposure of the metal wiring in the etching process after the metal wiring process is due to the characteristics of aluminum as the metal wiring material. It is practically difficult to recover in connection with the impossibility of high temperature heat treatment.
즉, 금속배선 형성 이후에 상기 금속배선이 노출된 상태로 고온 열처리를 행하면, 배선 재료인 알루미늄의 확산 및 산화반응 등이 일어나 배선 특성은 물론 소자 특성 저하가 초래되기 때문에 금속배선이 노출된 상태에서의 고온 열처리는 곤란하며, 그래서, 금속배선 형성시의 식각 공정에서 유발된 플라즈마 데미지를 회복시킴에 어려움이 있다.That is, if the high-temperature heat treatment is performed after the metal wiring is formed, the metal wiring is exposed in the exposed state, since diffusion and oxidation reaction of aluminum, which is a wiring material, occurs, resulting in deterioration of wiring characteristics and device characteristics. The high temperature heat treatment of is difficult, and therefore, it is difficult to recover the plasma damage caused in the etching process in forming the metal wiring.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 금속배선 형성시의 식각 공정에서 플라즈마 데미지가 유발되는 것을 방지할 수 있는 FeRAM 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a FeRAM device which can prevent plasma damage from being caused in an etching process when forming metal wirings.
또한, 본 발명은 플라즈마 데미지에 의한 소자 특성 및 수율 저하를 방지할 수 있는 FeRAM 소자의 제조방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method for manufacturing a FeRAM device capable of preventing device properties and yield degradation due to plasma damage.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 강유전성램 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1C are cross-sectional views of processes for describing a method of manufacturing a ferroelectric ram device according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 금속배선1 semiconductor substrate 2 metal wiring
3 : 층간절연막 4 : 감광막 패턴3: interlayer insulating film 4: photosensitive film pattern
5 : 콘택홀5: contact hole
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소정의 하지층이 형성된 반도체 기판 상에 금속배선을 형성하는 단계; 상기 금속배선을 덮도록 기판의 전면 상에 층간절연막을 증착하는 단계; 상기 층간절연막 상에 패드 형성 영역을 노출시키는 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 이용해서 노출된 층간절연막 부분의 소정 두께를 건식 식각하는 단계; 상기 건식 식각되고 잔류된 층간절연막 부분의 나머지 두께를 금속배선이 노출되도록 습식 식각하는 단계; 및 상기 감광막 패턴을 제거하는 단계를 포함하는 FeRAM 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention, forming a metal wiring on a semiconductor substrate on which a predetermined base layer is formed; Depositing an interlayer insulating film on the entire surface of the substrate to cover the metal wiring; Forming a photosensitive film pattern exposing a pad formation region on the interlayer insulating film; Dry etching a predetermined thickness of an exposed interlayer insulating film portion using the photosensitive film pattern; Wet etching the remaining thickness of the dry etched and remaining interlayer insulating film portion to expose metal wirings; And it provides a method of manufacturing a FeRAM device comprising the step of removing the photosensitive film pattern.
여기서, 상기 층간절연막은 PSG막이며, 건식 식각은 전체 두께 대비 70∼80%의 두께를 식각한다.Here, the interlayer insulating film is a PSG film, and the dry etching etches the thickness of 70 to 80% of the total thickness.
상기 층간절연막은 두 종류 산화막의 적층 구조로 이루어질 수 있으며, 이때, 하부 산화막은 습식식각률이 우수한 PSG막을 적용한다.The interlayer insulating layer may be formed of a laminated structure of two kinds of oxide layers, and the lower oxide layer may be a PSG layer having excellent wet etching rate.
상기 층간절연막은 두 종류 절연막의 적층 구조로 이루어질 수 있으며, 이때, 하부 절연막은 질화막이고 상부 절연막은 산화막이거나, 또는, 하부 절연막은 산화막이고 상부 절연막은 질화막이다.The interlayer insulating film may have a stacked structure of two kinds of insulating films, wherein the lower insulating film is a nitride film and the upper insulating film is an oxide film, or the lower insulating film is an oxide film and the upper insulating film is a nitride film.
상기 산화막의 건식 식각은 Ar, CF4 및 O2 혼합가스를 사용하여 수행하며, 이때, 상기 Ar 가스와 CF4 가스 및 O2 가스는 각각 100∼200sccm과 10∼20sccm 및 5∼10sccm을 사용한다.Dry etching of the oxide film is performed using a mixed gas of Ar, CF4 and O2, wherein the Ar gas, CF4 gas and O2 gas is used 100 ~ 200sccm, 10-20sccm and 5-10sccm, respectively.
상기 질화막의 건식 식각은 Ar, CF4, CHF3 및 O2 혼합가스를 사용하여 수행하며, 이때 상기 Ar 가스와 CF4 가스와 CHF3 가스 및 O2 가스는 각각 100∼200sccm과 10∼20sccm과 10∼20sccm 및 5∼10sccm을 사용한다.Dry etching of the nitride film is performed using a mixture of Ar, CF4, CHF3 and O2, wherein the Ar gas, CF4 gas, CHF3 gas and O2 gas are 100 to 200 sccm, 10 to 20 sccm, 10 to 20 sccm and 5 to 5, respectively. Use 10 sccm.
상기 층간절연막의 습식 식각은 BOE 용액을 사용하여 수행한다.Wet etching of the interlayer insulating film is performed using a BOE solution.
본 발명에 따르면, 층간절연막의 식각시에 건식식각과 습식식각을 혼용하여 사용함으로써 금속배선이 노출되면서 유발되는 플라즈마 데미지를 효과적으로 억제 또는 방지할 수 있다.According to the present invention, by using a combination of dry etching and wet etching during the etching of the interlayer insulating film it is possible to effectively suppress or prevent the plasma damage caused by the exposure of the metal wiring.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 FeRAM 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1C are cross-sectional views illustrating processes for manufacturing a FeRAM device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 소정의 하부 구조물이 형성된 반도체 기판(1) 상에 최종금속배선(2)을 형성한 후, 상기 금속배선(2) 상에 층간절연막(3)을 증착한다. 그런다음, 상기 층간절연막(3) 상에 패드 형성 영역을 노출시키는 감광막 패턴(4)을 형성한다.Referring to FIG. 1A, after forming the final metal wiring 2 on the semiconductor substrate 1 on which a predetermined lower structure is formed, an interlayer insulating film 3 is deposited on the metal wiring 2. Then, a photoresist pattern 4 is formed on the interlayer insulating film 3 to expose the pad formation region.
여기서, 상기 층간절연막(3)으로서는 습식식각율이 우수한 PSG막을 적용할 수 있다. 또한, 상기 층간절연막(3)으로서는 서로 다른 두 종류의 산화막을 적용할 수도 있으며, 이 경우, 하부 산화막은 습식식각률이 우수한 PSG막을 적용함이 바람직하다. 게다가, 상기 층간절연막(3)으로서는 두 종류 절연막을 적용할 수 있으며, 이때, 하부 절연막은 질화막을, 그리고, 상부 절연막은 산화막을 적용하거나, 반대로, 하부 절연막은 산화막을, 그리고, 상부 절연막은 질화막을 적용할 수 있다.Here, as the interlayer insulating film 3, a PSG film having excellent wet etching rate can be used. In addition, two different types of oxide films may be used as the interlayer insulating film 3, and in this case, it is preferable to apply a PSG film having excellent wet etching rate to the lower oxide film. In addition, two kinds of insulating films may be used as the interlayer insulating film 3, wherein the lower insulating film is applied to the nitride film, and the upper insulating film is applied to the oxide film, or, on the contrary, the lower insulating film is to the oxide film, and the upper insulating film is to the nitride film. Can be applied.
도 1b를 참조하면, 감광막 패턴(4)을 이용해서 노출된 층간절연막 부분을 건식 식각한다. 이때, 상기 층간절연막(3)의 식각은 전체 두께를 모두 식각하는 것이 아니라, 일부 두께가 남겨지도록 수행한다. 예컨데, 상기 층간절연막(3)으로서 단일 산화막이 적용된 경우, 즉, PSG막인 적용된 경우, 이 PSG막의 식각은 전체 두께 대비 70∼80% 정도만 수행한다.Referring to FIG. 1B, the exposed interlayer insulating film portion is dry-etched using the photosensitive film pattern 4. At this time, the etching of the interlayer insulating film 3 is performed not to etch the entire thickness, but to leave some thickness. For example, when a single oxide film is applied as the interlayer insulating film 3, that is, a PSG film is applied, etching of the PSG film is performed only about 70 to 80% of the total thickness.
한편, 상기 층간절연막(3)으로서 서로 다른 두 종류의 산화막을 적용한 경우에는 건식 식각으로 상부절연막만을 식각한다. 또한, 상기 층간절연막(3)으로서 산화막과 절연막을 적용한 경우에는 어느 하나의 막만을 건식 식각으로 식각한다. 특히, 하부 절연막으로 질화막을 적용하고 상부 절연막으로 산화막을 적용한 경우에는 상기 질화막을 식각정지막으로서 이용함으로써 기판 위치별 식각률 차이에 기인하는 식각 불균일이 방지되도록 함이 바람직하다.On the other hand, when two different types of oxide films are applied as the interlayer insulating film 3, only the upper insulating film is etched by dry etching. In addition, when an oxide film and an insulating film are applied as the interlayer insulating film 3, only one film is etched by dry etching. In particular, when the nitride film is applied as the lower insulating film and the oxide film is applied as the upper insulating film, it is preferable to use the nitride film as an etch stop film to prevent the etching irregularity caused by the difference in the etching rate for each substrate position.
또한, 상기 층간절연막(3)을 건식 식각함에 있어서, 산화막 식각시에는 식각 가스로서 Ar, CF4 및 O2 혼합가스를 사용하며, 이때, 상기 Ar 가스와 CF4 가스 및 O2 가스는 각각 100∼200sccm과 10∼20sccm 및 5∼10sccm을 사용한다. 반면, 질화막 식각시에는 식각 가스로서 Ar, CF4, CHF3 및 O2 혼합가스를 사용하며, 이때 상기 Ar 가스와 CF4 가스와 CHF3 가스 및 O2 가스는 각각 100∼200sccm과 10∼20sccm과 10∼20sccm 및 5∼10sccm을 사용한다.In the dry etching of the interlayer insulating film 3, a mixed gas of Ar, CF4, and O2 is used as an etching gas when the oxide layer is etched, wherein the Ar gas, CF4 gas, and O2 gas are 100 to 200 sccm and 10, respectively. 20 sccm and 5-10 sccm are used. On the other hand, when the nitride film is etched, Ar, CF4, CHF3 and O2 gas mixtures are used as etching gases, wherein the Ar gas, CF4 gas, CHF3 gas and O2 gas are 100 to 200 sccm, 10 to 20 sccm, 10 to 20 sccm and 5, respectively. 10 sccm is used.
도 1c를 참조하면, 상기 건식 식각시에 제거되지 않고 잔류된 패드 형성 영역 상의 나머지 층간절연막 부분을 BOE(Buffered Oxide Etchant) 용액을 이용한 습식 식각으로 제거한다.Referring to FIG. 1C, the remaining portion of the interlayer insulating layer on the pad forming region which is not removed during the dry etching is removed by wet etching using a buffered oxide etchant (BOE) solution.
이후, 식각 장벽으로 사용된 감광막 패턴을 제거한 상태에서 금속막의 증착 및 패터닝을 통해 금속배선과 연결되는 패드를 형성한 후, 공지의 후속 공정을 진행하여 본 발명의 FeRAM 소자를 완성한다.Subsequently, after forming the pad connected to the metal wiring through the deposition and patterning of the metal film while removing the photoresist pattern used as the etch barrier, the well-known subsequent process is performed to complete the FeRAM device of the present invention.
전술한 바와 같이, 본 발명에 따른 FeRAM 소자의 제조방법은 금속배선을 노출시키는 층간절연막의 식각시에 건식 식각과 습식 식각을 혼용하여 사용함으로써 전하 축적 현상을 현저히 감소시킬 수 있으며, 그래서, 플라즈마 데미지를 효과적으로 억제 또는 방지할 수 있다.As described above, the method of manufacturing the FeRAM device according to the present invention can significantly reduce the charge accumulation phenomenon by using a combination of dry etching and wet etching in the etching of the interlayer insulating film exposing the metal wiring, so that the plasma damage Can be effectively suppressed or prevented.
자세하게, 금속배선 형성시의 금속막 식각 또는 하부 금속배선을 노출시키는 층간절연막 식각시의 금속배선에 유발되는 플라즈마 데미지는 전하 축적(charge build up) 한 전기적 데미지가 가장 유력하다. 또한, FeRAM 소자의 강유전체는 물질 자체의 자발분극을 소자에 응용하였기 때문에 플라즈마 공정에서의 차아징 데미지(charging damage)는 심각한 영향을 미칠 수 있다.In detail, the plasma damage caused to the metal wiring during the interlayer insulating film etching exposing the metal film etching or the lower metal wiring during the metal wiring formation is most likely the electrical damage caused by the charge build up. In addition, since the ferroelectric material of the FeRAM device applies the spontaneous polarization of the material itself to the device, charging damage in the plasma process may have a serious effect.
즉, 건식 식각 공정에서는 일반적으로 기판의 포텐셜(potential)이 플라즈마의 포텐셜 보다 낮아서 초기에는 전자가 감광막 마스크에 축적(charge up)될 가능성이 많고, 실제 건식식각이 진행되고 금속막이 노출되는 순간에는 스퍼터링되는 이온에 의하여 포지티브 축적(positive charge up)될 가능성이 많다. 그런데, 이렇게 비대칭적으로 축적된 전하 파티클은 강유전성 물질의 도메인을 한쪽 방향으로 고정(pinning)시키며, 이것은 결국 히스테리시스 루프(hysterisis loop)의 X축 방향으로의 쉬프트(shift)를 가져오며, 이는 결국 편광성(polarization)의 감소를 의미한다.That is, in the dry etching process, the potential of the substrate is generally lower than that of the plasma, so that electrons are likely to accumulate in the photoresist mask in the early stage, and sputtering is performed when the actual dry etching is performed and the metal film is exposed. There is a high possibility of positive charge up by the ions which become. This asymmetrically accumulated charge particle, however, pins the domain of the ferroelectric material in one direction, which in turn results in a shift in the X-axis direction of the hysterisis loop, which in turn It means a decrease in polarization.
그런데, 본 발명은 플라즈마를 이용한 건식 식각시, 건식 식각과 습식 식각을 혼용하여 사용하기 때문에, 즉, 건식 식각시에는 금속배선이 노출되지 않을 정도로만 수행하며, 이후, 습식 식각으로 금속배선이 노출되도록 층간절연막을 식각하기 때문에, 플라즈마에 의한 금속배선 표면에서의 전하 축적은 일어나지 않거나 최소화되며, 따라서, 플라즈마 데미지에 의한 소자 특성 및 수율 저하는 초래되지 않게 된다.However, the present invention uses dry and wet etching in combination with the dry etching using plasma, that is, the dry etching is performed only to the extent that the metal wiring is not exposed, so that the metal wiring is exposed by wet etching. Since the interlayer insulating film is etched, charge accumulation on the surface of the metal wiring by plasma does not occur or is minimized, and therefore, deterioration of device characteristics and yield due to plasma damage is not caused.
이상에서와 같이, 본 발명은 층간절연막을 식각함에 있어서 건식식각을 통하여 대부분의 두께를 식각한 후에 습식 식각으로 나머지 잔류 두께를 식각함으로써, 금속배선이 노출되면서 유발되는 플라즈마 데미지를 효과적으로 방지할 수 있으며, 이에 따라, FeRAM 소자의 특성 및 수율을 향상시킬 수 있다.As described above, the present invention can effectively prevent the plasma damage caused by the exposure of the metal wiring by etching the remaining thickness in the wet etching after etching most of the thickness through the dry etching in etching the interlayer insulating film. Accordingly, the characteristics and the yield of the FeRAM device can be improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030033770A KR20040102403A (en) | 2003-05-27 | 2003-05-27 | Method of manufacturing FeRAM device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030033770A KR20040102403A (en) | 2003-05-27 | 2003-05-27 | Method of manufacturing FeRAM device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040102403A true KR20040102403A (en) | 2004-12-08 |
Family
ID=37378659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030033770A KR20040102403A (en) | 2003-05-27 | 2003-05-27 | Method of manufacturing FeRAM device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040102403A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101161666B1 (en) * | 2006-10-31 | 2012-07-03 | 에스케이하이닉스 주식회사 | FeRAM device and method of manufacturing the same |
-
2003
- 2003-05-27 KR KR1020030033770A patent/KR20040102403A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101161666B1 (en) * | 2006-10-31 | 2012-07-03 | 에스케이하이닉스 주식회사 | FeRAM device and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6338994B1 (en) | Semiconductor device and method of fabricating thereof | |
| US6054391A (en) | Method for etching a platinum layer in a semiconductor device | |
| US6573167B2 (en) | Using a carbon film as an etch hardmask for hard-to-etch materials | |
| KR20010109610A (en) | A method for forming ferroelectric capacitor in semiconductor device | |
| US20020076936A1 (en) | Method of fabricating semiconductor integrated circuit device and the semiconductor integrated circuit device | |
| JP2001036024A (en) | Capacitor and manufacture thereof | |
| KR20040102403A (en) | Method of manufacturing FeRAM device | |
| KR20090022809A (en) | Method for fabricating semiconductor device | |
| KR100353805B1 (en) | A method for forming capacitor in semiconductor device | |
| KR100798789B1 (en) | Method for fabricating semiconductor device | |
| KR100859254B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100333660B1 (en) | Method for forming ferroelectric capacitor | |
| KR100801314B1 (en) | Method for fabricating capacitor in semiconductor device | |
| JP2003282839A (en) | Method of manufacturing ferroelectric memory device | |
| KR100979231B1 (en) | Method of manufacturing FeRAM device | |
| KR20030054310A (en) | Method for fabricating capacitor in semiconductor device | |
| KR19990085671A (en) | Etching method of metal wiring to prevent damage of ferroelectric capacitor | |
| KR100583113B1 (en) | A method for forming a memory cell | |
| KR20020003067A (en) | Method for forming semiconductor memory device capable of preventing loss of glue layer during wet cleaning process | |
| KR100329784B1 (en) | Method for preventing degradation of ferroelectric layer in metal wire formation process by using polymer | |
| KR20010004293A (en) | Method for forming ferroelectric capacitor capable of preventing short between top and bottom electrode | |
| KR20020014229A (en) | Method for forming capacitor having Pt electrode | |
| KR20010038612A (en) | Method for etching a hydrogen barrier layer of capacitor | |
| KR20000004526A (en) | Method of manufacturing charge storing electrode of semiconductor device | |
| KR20020045683A (en) | Method for fabricating capacitor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |