KR20020014229A - Method for forming capacitor having Pt electrode - Google Patents

Abstract

PURPOSE: A method for forming a capacitor having a platinum electrode is provided to simplify a fabricating process, by etching a Pt upper electrode, a ferroelectric layer and a Pt lower electrode while one etch mask is used. CONSTITUTION: The first Pt layer(14), a dielectric layer(15) and the second Pt layer(16) are sequentially stacked on a substrate(10). The first etch mask is formed on the second Pt layer. A part of the second Pt layer not covered with the first etch mask is etched. The second Pt layer is etched to form an upper electrode pattern. The first etch mask and etch byproducts are etched to form the second etch mask smaller than the first etch mask. The dielectric layer not covered with the second etch mask is etched to form a dielectric layer pattern. The second etch mask and etch byproducts are etched to form the third etch mask smaller than the second etch mask. A part of the first Pt layer not covered with the third etch mask is etched. The third etch mask and etch byproducts deposited on the sidewall of the third etch mask are etched to form the fourth etch mask smaller than the third etch mask. The first Pt layer not covered with the fourth etch mask is etched to form a lower electrode pattern. The fourth etch mask and etch byproducts deposited on the sidewall of the fourth etch mask are etched to form the fifth etch mask smaller than the fourth etch mask.

Description

A method for forming a capacitor having a platinum electrode {Method for forming capacitor having Pt electrode}

TECHNICAL FIELD The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of forming a capacitor.

A memory device refers to a device that stores data and can be ejected when needed. In particular, semiconductor memory devices, mainly DRAM (Dynamic Random Access Memory), have been developed and disseminated very rapidly because of their small size, high reliability, and low cost, and relatively high speed operation.

Meanwhile, by using ferroelectric materials in capacitors in semiconductor memory devices, development of devices capable of using a large-capacity memory while overcoming the limitation of refresh required in conventional DRAM (Dynamic Random Access Memory) devices has been in progress. . A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.

As the storage material of FeRAM, Sr _i Bi _j Ta ₂ O ₉ (hereinafter SBT) and Pb (Zr, Ti) O ₃ (hereinafter PZT) thin films are mainly used. Ferroelectrics have hundreds to thousands of dielectric constants at room temperature and have two stable residual polarization states, making them thin and applying them to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .

On the other hand, the relationship of the memory cell area to the minimum machining dimension of FeRAM developed so far is almost five times compared to the DRAM cell area for the same minimum machining dimension. Since FeRAM has a larger cell area than DRAM, it is necessary to reduce the FeRAM memory cell area in order to improve the price competitiveness of the product.

In addition, in the process of forming a ferroelectric capacitor of a conventional FeRAM device, each of the upper electrode, the ferroelectric film, and the lower electrode is patterned using a separate mask, or the lower electrode and the ferroelectric film are patterned using the same mask and the upper electrode is a separate mask. Patterning is done using. Therefore, it is not easy to reduce the cell area because the lower electrode must be larger than the upper electrode.

As the electrode of the ferroelectric capacitor, Pt having advantages of small mismatch between the ferroelectric material and lattice constant, low reactivity, excellent high temperature resistance, and strong self-orientation is used. In the case where the Pt upper electrode, the ferroelectric layer and the Pt lower electrode are etched using a single photoresist pattern as an etching mask, Pt is re-depositioned on the sidewalls of the photoresist pattern to form a fence. There is a problem in that an electrical short between the electrodes occurs or an excessive leakage current is generated thereby. Therefore, the fence formed by redeposition of Pt should be removed.

The Pt film is mainly etched by a physical method, that is, sputtering, but since the vapor pressure of the halogen compound of Pt is very low, it is difficult to remove the fence through dry etching or wet etching.

In the present invention for solving the above problems, in the method of forming a capacitor having a Pt upper electrode, a dielectric layer, and a Pt lower electrode, the Pt upper electrode, the dielectric layer, and the Pt lower electrode may be etched using a single etching mask. It is an object of the present invention to provide a method for forming a capacitor capable of preventing a short circuit between electrodes due to redeposition of Pt.

1 to 6 are cross-sectional views of a capacitor forming process according to an embodiment of the present invention.

* Description of reference numerals for the main parts of the drawings *

14: first Pt film 15: ferroelectric film

16: second Pt film M1, M2, M3, M4, M5: photoresist pattern

The present invention for achieving the above object, the first step of sequentially stacking a first Pt film, a dielectric film and a second Pt film to form an upper electrode on the substrate; Forming a first etching mask on the second Pt layer; Etching a portion of the second Pt layer not covered with the first etching mask; The second Pt layer is etched until the dielectric layer is exposed to form an upper electrode pattern, and the etch by-products deposited on sidewalls of the first etch mask and the first etch mask are etched to have a smaller size than the first etch mask. Forming a second etching mask; The dielectric layer not covered with the second etching mask may be etched to form a dielectric layer pattern, and the second etching mask and the etching by-products deposited on the sidewalls of the second etching mask may be etched to reduce the size of the dielectric layer. A fifth step of forming an etching mask; A fourth etching having a smaller size than the third etching mask by etching the portion of the first Pt layer not covered with the third etching mask and etching the etching by-products deposited on the sidewalls of the third etching mask and the third etching mask. A sixth step of forming a mask; And etching the first Pt layer not covered with the fourth etching mask to form a lower electrode pattern, and etching the fourth etching mask and the etching by-products deposited on the sidewalls of the fourth etching mask to be larger than the fourth etching mask. It provides a method of forming a capacitor comprising a seventh step of forming a small fifth etching mask.

The present invention is characterized in that the Pt upper electrode, the dielectric layer, and the Pt lower electrode are etched using one etching mask to collectively integrate a capacitor using Pt as an electrode material, such as FeRAM. That is, a capacitor is formed by etching sidewalls of the etch mask during the Pt upper electrode and the Pt lower electrode to remove the etch byproducts deposited on the etch mask sidewalls, thereby reducing the size of the etch mask and increasing the width from the upper electrode to the lower electrode. By forming the pattern, short circuit between the electrodes can be prevented while effectively preventing redeposition of the etching byproduct.

The present invention is to remove the etching by-products of the Pt in-situ by etching the sidewalls of the photoresist pattern in order to overcome the problem of electrical short circuit caused by the Pt redeposited on the sidewalls of the photoresist pattern, the upper Pt electrode, ferroelectric film, Pt lower The electrode forms one photoresist pattern.

In general, a fence formed by redeposition of Pt etching by-products generated during etching of the Pt upper electrode, the ferroelectric layer, and the Pt upper electrode is less dense than the Pt layer, and thus the lower portion of the Pt upper electrode, the ferroelectric layer, and the Pt upper electrode may Etched faster than Pt. However, in the case of etching in a vertical shape in the etching process, the etching speed in the lateral direction is very low, making it difficult to remove the fence redeposited on the sidewall.

On the other hand, as in the present invention, if the shape of the capacitor is formed to become wider from the upper electrode to the lower electrode to increase the etching rate to the sidewall fence having a high etching rate can be naturally removed during the etching process.

Hereinafter, a method of forming a capacitor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6.

As shown in FIG. 1, an interlayer insulating film 11 is formed on a semiconductor substrate 10 on which a substructure (not shown) such as a transistor is formed, and the interlayer insulating film 11 is selectively etched to form a semiconductor substrate ( 10) forming a contact hole exposing the contact hole, and then forming a plug 12, a diffusion barrier 13 in the contact hole, and forming a first Pt film 14, a ferroelectric film 15 and an upper electrode to form a lower electrode. A second Pt film 16 is formed in this order, and a first photoresist pattern M1 serving as an etching mask is formed on the second Pt film 16. The etching mask may be formed of a W film or a film containing Ti elements in place of the photoresist.

Next, as shown in FIG. 2, an etching gas containing Cl ₂ is injected into the sputtering etching apparatus to etch a part of the second Pt film 16. By using Cl ₂ gas as described above, not only physical etching by sputtering but also chemical etching effect can be expected. In this case, etching is performed while maintaining the temperature of the support (lower electrode) of the semiconductor substrate 10 in the chamber at or above room temperature. More preferably, in the embodiment of the present invention, the temperature of the semiconductor substrate support is maintained at about 300 ° C.

The amount of Cl ₂ is to be 5 sccm or more in absolute amount in consideration of the etching selectivity with respect to the photoresist pattern, and to be relatively 20% or less of the total gas amount. In this etching process, PtCl _{x, which} is an etching byproduct of Pt, is redeposited on the sidewall of the first photoresist pattern M1 to form a fence F.

Next, as shown in FIG. 3, the second Pt film 16 remaining using the etching gas containing Cl ₂ and O ₂ is etched to form a Pt upper electrode, thereby exposing the ferroelectric film 15 to expose the fence ( F) is removed, and at the same time, sidewalls of the first photoresist pattern are etched to form a second photoresist pattern M2 having a smaller size than the first photoresist pattern.

When the etching mask is formed of W film, SF ₆ or NF ₃ is added in place of O ₂ , and when the etching mask is formed of a film containing Ti element, CF ₄ or C ₂ F ₆ is used instead of O ₂ . Add. Each of O ₂ , SF ₆ , NF ₃ , CF _4, or C ₂ F ₆ accounts for 10% or less of the total gas.

The fence (F) formed by redepositing the etching by-product of Pt has a very fine microstructure, and thus the etching speed is faster than that of the Pt film. In particular, the etching by-product PtCl _x generated during the etching process of the Pt film using Cl ₂ has a faster etching rate due to the smaller mutual bonding force.

Subsequently, the ferroelectric layer 15 is etched by using the second photoresist pattern M2 as an etching mask and including O ₂ in the ferroelectric layer etching gas to form the ferroelectric layer 15 pattern as shown in FIG. 4. The third photoresist pattern M3 smaller than the second photoresist pattern M2 is formed while exposing the one Pt film 14.

In this case, when the etching mask is formed of W film, SF ₆ or NF ₃ is added instead of O ₂ , and when the etching mask is formed of a film containing Ti element, CF ₄ or C ₂ is used instead of O ₂ . F ₆ is added.

Next, an etching gas including Cl ₂ and O ₂ is injected to etch a portion of the first Pt layer 14 to remove Pt etching by-products deposited on sidewalls of the third photoresist pattern M3, as shown in FIG. 5. Similarly, the fourth photoresist pattern M4 having a smaller size than the third photoresist pattern M3 is formed.

Subsequently, an etching gas including Cl ₂ and O ₂ is injected to etch the remaining portion of the first Pt layer 14 to form a Pt lower electrode pattern, thereby depositing Pt etching by-products deposited on sidewalls of the fourth photoresist pattern M4. As shown in FIG. 6, a fifth photoresist pattern M5 having a smaller size than the fourth photoresist pattern M4 is formed.

Sputtering effect by ions by increasing DC self bias using low frequency RF power of 1 MHz or less in etching process of the second Pt film 16, ferroelectric film 15 and first Pt film 14 To increase. On the other hand, in order to increase the sputtering effect and shorten the process time, the etching power is converted into DC bias and increased to a size of -300 V or more to perform etching. In addition, in order to smoothly discharge Pt, Bi, Sr, Ta, etc. generated by sputtering, etching is performed at an extremely low pressure of 2 mTorr or less.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention, the Pt upper electrode, the ferroelectric layer, and the Pt lower electrode are etched using one etching mask, thereby simplifying the process compared to the conventional technique of separately etching the Pt upper electrode. In addition, the etching formed by simultaneously removing the sidewalls of the photoresist pattern may be performed to remove the fence formed by redeposition of Pt in situ in the etching process. Thereby, the short circuit between the capacitors formed by the cell of a narrow area can be prevented. Therefore, the cost reduction effect can be obtained by increasing the number of net dies by reducing the cell area, and the mask process and the dry etching process for capacitor formation can be reduced in one step. As a result, cost reduction and yield improvement due to process simplification can be expected. In addition, since the upper surface of the ferroelectric film is not directly exposed to the plasma during the dry etching process, deterioration of the capacitor due to plasma damage can be prevented. Thereby, the yield improvement by element stabilization can be anticipated.

Claims (5)

In the capacitor forming method, A first step of sequentially stacking a first Pt film, a dielectric film, and a second Pt film, which will form an upper electrode, on the substrate; Forming a first etching mask on the second Pt layer; Etching a portion of the second Pt layer not covered with the first etching mask; The second Pt layer is etched until the dielectric layer is exposed to form an upper electrode pattern, and the etch by-products deposited on sidewalls of the first etch mask and the first etch mask are etched to have a smaller size than the first etch mask. Forming a second etching mask; The dielectric layer not covered with the second etching mask may be etched to form a dielectric layer pattern, and the second etching mask and the etching by-products deposited on the sidewalls of the second etching mask may be etched to reduce the size of the dielectric layer. A fifth step of forming an etching mask; A fourth etching having a smaller size than the third etching mask by etching the portion of the first Pt layer not covered with the third etching mask and etching the etching by-products deposited on the sidewalls of the third etching mask and the third etching mask. A sixth step of forming a mask; And The first Pt layer not covered with the fourth etching mask is etched to form a lower electrode pattern, and the fourth etching mask and the etching by-products deposited on sidewalls of the fourth etching mask are etched to have a size larger than that of the fourth etching mask. A seventh step of forming a small fifth etching mask Capacitor formation method comprising a. The method of claim 1, And the dielectric film is a ferroelectric material. The method according to claim 1 or 2, The first etching mask is formed in a photoresist pattern, The fourth step to the seventh step is a capacitor forming method, characterized in that for etching with an etching gas containing O ₂ . The method according to claim 1 or 2, Forming the first etching mask to W, In the fourth to seventh step, the method of forming a capacitor, characterized in that for etching with an etching gas containing SF ₆ or NF ₃ . The method according to claim 1 or 2, The first etching mask is formed of a film containing Ti element, The fourth step to the seventh step is a capacitor forming method characterized in that the etching with an etching gas containing CF ₄ or C ₂ F ₆ .