CN110767658A - Forming method of flash memory device - Google Patents
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- CN110767658A CN110767658A CN201911057262.0A CN201911057262A CN110767658A CN 110767658 A CN110767658 A CN 110767658A CN 201911057262 A CN201911057262 A CN 201911057262A CN 110767658 A CN110767658 A CN 110767658A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- LVGUZGTVOIAKKC-UHFFFAOYSA-N 1,1,1,2-tetrafluoroethane Chemical compound FCC(F)(F)F LVGUZGTVOIAKKC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 107
- 230000008569 process Effects 0.000 description 14
- 230000015654 memory Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
In the method for forming the flash memory device, a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the side surface and the top surface of the grid structure and the surface of the semiconductor substrate, the second dielectric layer is exposed by removing the third dielectric layer on the top surface of the grid structure and the surface of the semiconductor substrate, and the exposed second dielectric layer is removed by wet etching. The wet etching has high selectivity and is easy to control, and only the exposed second dielectric layer can be removed; therefore, etching damage to the semiconductor substrate can be avoided, and the performance of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a flash memory device.
Background
NOR Flash memory (NOR Flash) has become one of the most widely used non-volatile memories at present because of its advantages of low power consumption, large capacity, low cost, better reliability compared to NAND Flash memory (NAND Flash), faster processing speed when the data size is small, and on-chip execution capability. Nowadays, the NOR flash memory gradually enters the development and mass production stage of 50nm node through the mass production stage of 65nm node. Smaller technology nodes can present greater process challenges to the fabrication of NOR flash memories. The flash memory device comprises a side wall, and the side wall has the following functions of protecting a grid structure in the side wall and preventing source-drain punch-through caused by too close of a large dose of source/drain (S/D) injection.
In a 50nm NOR flash memory device, in order to reduce the process complexity, the thicknesses of the side walls of the storage region and the logic region device are consistent with those of a 65nm NOR flash memory device during S/D injection. Due to the reduction of the adjacent gate gap, in order to completely fill the interlayer dielectric (ILD) in the gap and ensure the contact process window, the process flow of the sidewall needs to be adjusted.
In the prior art, in a 50nm NOR flash memory device, in order to ensure smooth filling of ILD after S/D injection and a process window of contact, the thickness of an oxide layer contained in a sidewall structure is reduced. However, this process scheme has the following problems: because the thickness of the side wall oxide layer is small, after the side wall is formed, etching is difficult to stop on the stop layer in a subsequent etching process, the thickness of the side wall needing to be reserved is difficult to ensure, and the side wall is easy to etch on a silicon substrate, so that the etching damage of the semiconductor substrate is caused. Therefore, the expected effect of the etching process of the side wall is difficult to achieve. In addition, the dry etching at this step can cause the difference in the thickness of the remaining silicon oxide at the center and edge of the wafer, which affects the subsequent S/D implantation and thus the performance of the device.
Disclosure of Invention
The invention aims to provide a method for forming a flash memory device, which aims to solve the problem of etching damage to a semiconductor substrate in the forming process of the flash memory device in the prior art.
In order to solve the above technical problem, the present invention provides a method for forming a flash memory device, including:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
sequentially forming a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is made of a material different from that of the first dielectric layer and the third dielectric layer, and the first dielectric layer covers the side surface and the top surface of the gate structure and the surface of the semiconductor substrate;
removing the third dielectric layer on the top surface of the grid structure and the surface of the semiconductor substrate to expose part of the second dielectric layer;
and removing the exposed second dielectric layer by wet etching.
Optionally, in the method for forming the flash memory device, the solution used in the wet etching is phosphoric acid.
Optionally, in the method for forming the flash memory device, the thickness of the third dielectric layer is greater than the thickness of the first dielectric layer.
Optionally, in the method for forming the flash memory device, the first dielectric layer and the third dielectric layer are made of the same material.
Optionally, in the method for forming the flash memory device, the first dielectric layer and the third dielectric layer are made of silicon oxide.
Optionally, in the method for forming the flash memory device, the second dielectric layer is made of silicon nitride.
Optionally, in the method for forming the flash memory device, the third dielectric layer on the top surface of the gate structure and the surface of the semiconductor substrate is removed by dry etching.
Optionally, in the method for forming a flash memory device, the etching gas for the dry etching is one or a combination of tetrafluoromethane, tetrafluoroethane, silicon fluoride, nitrogen trifluoride and trifluoromethane.
Optionally, in the method for forming the flash memory device, the gate structure includes a gate dielectric layer and a gate located on the gate dielectric layer.
Optionally, in the method for forming a flash memory device, an oxide layer is formed on the surface of the semiconductor substrate, and the gate structure is located on the oxide layer.
In the method for forming the flash memory device, a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on the side surface and the top surface of the grid structure and the surface of the semiconductor substrate, the second dielectric layer is exposed by removing the third dielectric layer on the top surface of the grid structure and the surface of the semiconductor substrate, and the exposed second dielectric layer is removed by wet etching. The wet etching has high selectivity and is easy to control, and only the exposed second dielectric layer can be removed; therefore, etching damage to the semiconductor substrate can be avoided, and the performance of the device can be improved.
Drawings
Fig. 1 is a flow chart of a method of forming a flash memory device of an embodiment of the present invention;
FIGS. 2-4 are schematic diagrams of structures formed at various steps in a method of forming a flash memory device in accordance with an embodiment of the present invention;
wherein the reference numerals are as follows:
100-a semiconductor substrate; 101-an oxide layer; a 110 gate structure; 120-a first dielectric layer; 130 a second dielectric layer; 140 a third dielectric layer.
Detailed Description
The method for forming a flash memory device according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Please refer to fig. 1, which is a flowchart illustrating a method for forming a flash memory device according to an embodiment of the present invention. As shown in fig. 1, the method for forming the flash memory device includes:
step S1, providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
step S2, forming a first dielectric layer, a second dielectric layer and a third dielectric layer in sequence, wherein the second dielectric layer is made of a material different from that of the first dielectric layer and the third dielectric layer, and the first dielectric layer covers the side surface and the top surface of the grid structure and the surface of the semiconductor substrate;
step S3, removing the third dielectric layer on the top surface of the grid structure and the surface of the semiconductor substrate to expose part of the second dielectric layer;
and step S4, removing the exposed second dielectric layer through wet etching.
Referring to fig. 2, in step S1, a semiconductor substrate 100 is provided, and the material of the semiconductor substrate 100 may be, but is not limited to, monocrystalline silicon, polycrystalline silicon, amorphous silicon, or silicon-on-insulator. An oxide layer 101 may be formed on the surface of the semiconductor substrate to cover the surface of the semiconductor substrate 100 to protect the semiconductor substrate 100, and the oxide layer 101 may be a silicon oxide layer. A gate structure 110 is formed on the semiconductor substrate 100; in the embodiment of the present application, the gate structure 110 is located on the oxide layer 101. Specifically, the gate structure 110 includes a gate dielectric layer and a gate located on the gate dielectric layer, wherein the gate dielectric layer may be made of silicon oxide; the gate may be made of polysilicon, but is not limited to polysilicon, and may also be made of other materials known to those skilled in the art, such as metal, etc., which can be used as a gate.
In step S2, a first dielectric layer 120, a second dielectric layer 130, and a third dielectric layer 140 may be sequentially formed on the top and side surfaces of the gate structure 110 and the semiconductor substrate surface 100 by deposition. The deposition method may be, for example, Chemical Vapor Deposition (CVD). It is understood that the first dielectric layer 120 covers the side and top surfaces of the gate structure 110 and the surface of the semiconductor substrate 100, the second dielectric layer 130 covers the first dielectric layer 120, and the third dielectric layer 140 covers the second dielectric layer 130. The first dielectric layer 120, the second dielectric layer 130, and the third dielectric layer 140 are formed to prevent source/drain (S/D) punch-through caused by a high dose of source/drain (S/D) implantation in a subsequent source/drain (S/D) implantation process, thereby causing damage to the gate structure 110.
In the embodiment provided by the present invention, the material of the second dielectric layer 130 is different from the material of the first dielectric layer 120 and the third dielectric layer 140. The materials of the first dielectric layer 120 and the third dielectric layer 140 are the same, so as to form a thicker dielectric layer, thereby protecting the gate structure 110 and protecting the semiconductor substrate 100 in a subsequent etching process. In the embodiment of the present invention, preferably, the first dielectric layer 120 and the third dielectric layer 140 are made of silicon oxide, and the second dielectric layer 130 is made of silicon nitride, that is, the first dielectric layer 120, the second dielectric layer 130, and the third dielectric layer are an ONO structure layer. In the embodiment provided by the present invention, preferably, the thickness of the third dielectric layer is greater than that of the first dielectric layer, for example, the thickness range of the first dielectric layer 120 may be 50 to 100 angstroms, the thickness range of the second dielectric layer 130 may be 250 to 350 angstroms, and the thickness of the third dielectric layer may be 250 to 350 angstroms. When a plurality of gate structures are formed on the semiconductor substrate 100, the gap between adjacent gate structures is increased, thereby ensuring the filling of interlayer dielectric (ILD) in the subsequent process.
Referring to fig. 3, in step S3, the third dielectric layer 140 on the top surface of the gate structure 110 and the surface of the semiconductor substrate 100 is removed by dry etching, so as to expose a portion of the second dielectric layer 130. In an embodiment of the present invention, the etching gas for the dry etching is one or a combination of tetrafluoromethane, tetrafluoroethane, silicon fluoride, and nitrogen trifluoride and trifluoromethane. Specifically, the stop layer for the dry etching is the second dielectric layer 130, and the dry etching has a certain amount of over-etching during etching, and a part of the second dielectric layer 130 is etched away due to the over-etching during etching the first dielectric layer 120. The stop layer for dry etching is disposed on the second dielectric layer 120, so as to ensure the thickness of the second dielectric layer 120 after the dry etching, that is, after the dry etching is completed, the first dielectric layer 120 and a part of the second dielectric layer 130 are also covered on the semiconductor substrate 100. Thereby, the etching damage of the semiconductor substrate 100 by the dry etching can be avoided.
Referring to fig. 4, in step S4, the exposed second dielectric layer 130 is removed by wet etching, which has a high selectivity and is easy to control, and only the exposed second dielectric layer 130 can be removed, thereby avoiding damage to the semiconductor substrate 100 due to over-etching. Preferably, the solution used in the wet etching is phosphoric acid, and a higher etching ratio can be formed by etching the second dielectric layer 130 with phosphoric acid, so that only the portion to be etched can be removed in the etching process, thereby avoiding over-etching. Further, after the exposed second dielectric layer 130 is removed, the semiconductor substrate 100 is covered with a first dielectric layer 120, and the first dielectric layer 120 can protect the semiconductor substrate 100, so as to prevent an etching solution etched by a wet method from penetrating into the semiconductor substrate 100 during an etching process to damage the semiconductor substrate 100. Furthermore, the etching uniformity of the wet etching is good, so that the thickness difference of the first dielectric layer 120 on the semiconductor substrate 100 after etching can be avoided.
In summary, in the method for forming a flash memory device according to the present invention, a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed on the side surface and the top surface of the gate structure and the surface of the semiconductor substrate, the second dielectric layer is exposed by removing the third dielectric layer on the top surface of the gate structure and the surface of the semiconductor substrate, and the exposed second dielectric layer is removed by wet etching. The wet etching has high selectivity and is easy to control, and only the exposed second dielectric layer can be removed; therefore, etching damage to the semiconductor substrate can be avoided, and the performance of the device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for forming a flash memory device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
sequentially forming a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is made of a material different from that of the first dielectric layer and the third dielectric layer, and the first dielectric layer covers the side surface and the top surface of the gate structure and the surface of the semiconductor substrate;
removing the third dielectric layer on the top surface of the grid structure and the surface of the semiconductor substrate to expose part of the second dielectric layer;
and removing the exposed second dielectric layer by wet etching.
2. The method of claim 1, wherein the wet etching uses a solution of phosphoric acid.
3. The method of forming a flash memory device of claim 1, wherein a thickness of the third dielectric layer is greater than a thickness of the first dielectric layer.
4. The method of forming a flash memory device of claim 1, wherein the first dielectric layer and the third dielectric layer are the same material.
5. The method of claim 4, wherein the first dielectric layer and the third dielectric layer are both silicon oxide.
6. The method of claim 1, wherein the second dielectric layer is formed of silicon nitride.
7. The method of forming a flash memory device of claim 1, wherein the third dielectric layer on the top surface of the gate structure and the surface of the semiconductor substrate is removed by dry etching.
8. The method of forming a flash memory device according to claim 7, wherein the etching gas for the dry etching is one or a combination of tetrafluoromethane, tetrafluoroethane, silicon fluoride, and nitrogen trifluoride and trifluoromethane.
9. The method of forming a flash memory device of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode on the gate dielectric layer.
10. The method of claim 1, wherein an oxide layer is formed on the surface of the semiconductor substrate, and the gate structure is located on the oxide layer.
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| CN201911057262.0A CN110767658A (en) | 2019-10-30 | 2019-10-30 | Forming method of flash memory device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112071755A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Etching method and manufacturing method of three-dimensional memory |
| CN114551224A (en) * | 2022-04-28 | 2022-05-27 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN112071755B (en) * | 2020-09-17 | 2024-04-23 | 长江存储科技有限责任公司 | Etching method and manufacturing method of three-dimensional memory |
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Application publication date: 20200207 |