CN109659237B - Forming method of flash memory device - Google Patents

Forming method of flash memory device Download PDF

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Publication number
CN109659237B
CN109659237B CN201910001500.XA CN201910001500A CN109659237B CN 109659237 B CN109659237 B CN 109659237B CN 201910001500 A CN201910001500 A CN 201910001500A CN 109659237 B CN109659237 B CN 109659237B
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layer
floating gate
forming
control gate
oxide layer
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CN109659237A (en
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刘宪周
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

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Abstract

A method of forming a flash memory device, comprising: providing a substrate, wherein the surface of the substrate is provided with a floating gate layer; forming a control gate on the surface of the floating gate layer, wherein the control gate is internally provided with a first opening for exposing the floating gate layer; forming a first oxide layer and a material layer positioned on the surface of the first oxide layer on the side wall of the first opening; oxidizing the material layer, and forming a second oxide layer on the surface of the control gate on the side wall of the first opening; etching the floating gate layer by taking the control gate and the second oxide layer as masks until the substrate is exposed to form floating gates and second openings positioned between the floating gates; word lines are formed within the first and second openings. The flash memory device formed by the method can balance the breakdown voltage between the control gate and the word line and the control effect of the control gate on the floating gate.

Description

Forming method of flash memory device
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a flash memory device.
Background
In the current semiconductor industry, integrated circuit products can be divided into three major categories: analog circuits, digital circuits, and digital/analog hybrid circuits, where memory is an important type of digital circuit. In recent years, Flash memories (Flash memories) have been developed particularly rapidly. The flash memory has the main characteristics of long-term storage information under the condition of no power-on, and has the advantages of high integration level, high storage speed, easy erasing and rewriting and the like, so the flash memory is widely applied to various fields such as microcomputer, automatic control and the like.
The flash memory device mainly includes a Gate Stack (Stack Gate) structure and a Split Gate (Split Gate) structure, wherein the Split Gate structure has higher programming efficiency and can avoid excessive erasing and writing in the erasing and writing function, so that the flash memory device is widely applied to various electronic products such as smart cards, SIM cards, microcontrollers, mobile phones and the like.
However, the performance of the existing flash memory device is still poor.
Disclosure of Invention
The invention provides a method for forming a flash memory device, which aims to improve the performance of the flash memory device.
To solve the above technical problem, the present invention provides a method for forming a flash memory device, including: providing a substrate, wherein the surface of the substrate is provided with a floating gate layer; forming a control gate on the surface of the floating gate layer, wherein the control gate is internally provided with a first opening for exposing the floating gate layer; forming a first oxide layer and a material layer positioned on the surface of the first oxide layer on the side wall of the first opening; oxidizing the material layer, and forming a second oxide layer on the surface of the control gate on the side wall of the first opening; etching the floating gate layer by taking the control gate and the second oxide layer as masks until the substrate is exposed to form a floating gate and a second opening positioned between the floating gates; word lines are formed within the first and second openings.
Optionally, the thickness of the material layer is: 150 to 250 angstroms.
Optionally, the material of the material layer comprises silicon.
Optionally, the process for oxidizing the material layer includes a dry oxidation process and a wet oxidation process.
Optionally, a floating gate dielectric layer is further included between the floating gate layer and the control gate.
Optionally, the forming method of the floating gate dielectric layer and the control gate includes: forming a floating gate dielectric material film on the surface of the floating gate layer; forming a control gate material film on the floating gate dielectric material film, wherein the surface of the control gate material film is provided with a mask layer, and a mask opening exposing the surface of the control gate material film is formed in the mask layer; forming a side wall on the side wall of the mask opening; etching the control gate material film by taking the side wall and the mask layer as masks until the floating gate dielectric material film is exposed to form the control gate, wherein the control gate is internally provided with a first opening; and removing the floating gate dielectric material film at the bottom of the first opening by adopting a wet etching process until the floating gate layer is exposed to form a floating gate dielectric layer.
Optionally, the floating gate dielectric material film includes a third oxide layer located on the surface of the floating gate layer, a nitride layer located on the surface of the third oxide layer, and a fourth oxide layer located on the surface of the nitride layer; the third oxide layer is made of silicon oxide, the nitride layer is made of silicon nitride, and the fourth oxide layer is made of silicon oxide; the parameters of the wet etching process comprise: the etching agent comprises phosphoric acid, sulfuric acid and hydrogen peroxide.
Optionally, a fifth oxide layer is further disposed between the floating gate layer and the substrate; after the floating gate is formed and before the word line is formed, the method further comprises the following steps: removing the fifth oxide layer at the bottom of the second opening; the process for removing the fifth oxide layer at the bottom of the second opening comprises the following steps: wet etching process; the parameters of the wet etching process comprise: the cleaning agent comprises hydrofluoric acid, sulfuric acid and hydrogen peroxide.
Optionally, the thickness of the first oxide layer is: 60 to 70 angstroms.
Optionally, after forming the word line, the method further includes: forming a cap layer on the surface of the word line; and after the cap layer is formed, removing the mask layer and the control gate and the floating gate at the bottom of the mask layer to respectively form a first storage unit and a second storage unit which are positioned at two sides of the word line.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the flash memory device provided by the technical scheme of the invention, the control gate is internally provided with an opening, and a first oxide layer and a material layer are formed on the side wall of the opening. The material layer is converted into the oxide layer through an oxidation process, the thickness of the oxide layer is thick, and the thickness of the second oxide layer formed by the oxide layer and the first oxide layer is thick, so that the distance between the word line and the control gate is large, and therefore the breakdown voltage between the control gate and the word line is favorably improved. Meanwhile, as the first oxidation layer is arranged between the material layer and the control gate, when the material layer is completely oxidized, the first oxidation layer is used for slowing down the oxidation process and preventing the control gate from being oxidized too much, so that the thickness of the second oxidation layer is prevented from being too thick. And etching the floating gate layer by taking the control gate and the second oxide layer as masks to form the floating gate. Because the thickness of the second oxide layer is not too thick, the ratio of the size of the floating gate to the size of the control gate is not too large, and the control effect of the control gate on the floating gate is favorably improved. In summary, the flash memory device formed by the method can balance the breakdown voltage between the control gate and the word line and the control effect of the control gate on the floating gate.
Drawings
Fig. 1 to 3 are schematic structural views of a flash memory device;
fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a flash memory device according to an embodiment of the invention.
Detailed Description
As described in the background, flash memory devices have poor performance.
Fig. 1 to 3 are schematic structural views of a flash memory device.
Referring to fig. 1, a substrate 100 is provided, a floating gate layer 101 is provided on a portion of the surface of the substrate 100, a floating gate dielectric material film 102 is provided on a surface of the floating gate layer 101, a control gate material film 103 is provided on a surface of the floating gate dielectric material film 102, a mask layer 104 is provided on a portion of the control gate material film 103, and a mask opening (not shown) exposing the control gate material film 103 is provided in the mask layer 104; a first oxide layer 105 is formed on the sidewalls of the mask opening.
Referring to fig. 2, with the mask layer 104 and the first oxide layer 105 as masks, the control gate material film 103 (see fig. 1) is etched until the floating gate dielectric material film 102 (see fig. 1) is exposed, and a control gate 113 is formed, where the control gate 113 has a first opening 106 exposing the floating gate dielectric material film 102 therein; the floating gate dielectric material film 102 at the bottom of the first opening 106 is removed until the floating gate layer 101 is exposed, and a second opening (not shown) is formed in the floating gate dielectric material film at the bottom of the first opening 106.
Referring to fig. 3, a sidewall 107 is formed on the sidewalls of the first oxide layer 105, the first opening 106 and the second opening; etching the floating gate layer 101 by using the sidewall 107, the mask layer 104 and the first oxide layer 105 as masks until the surface of the substrate 100 is exposed, and forming a floating gate 111 and a third opening (not shown) located between the floating gates 111; a word line 108 is formed within the first opening 106, the second opening, and the third opening.
In the above method for forming the flash memory device, the method for forming the sidewall spacers 107 includes: forming sidewall films on the surfaces of the mask layer 104, the first oxide layer 105 and the floating gate layer 101, and on sidewalls of the first oxide layer 105, the first opening 106 and the second opening; and removing the side wall films on the surfaces of the mask layer 104, the first oxide layer 105 and the floating gate layer 101 to form the side wall 107. The process for removing the mask layer 104, the first oxide layer 105 and the sidewall film on the surface of the floating gate layer 101 includes a dry etching process. By-products are formed during the dry etching process, and the by-products are used for protecting the first oxide layer 105, the first opening 106 and the sidewall film of the sidewall of the second opening from being excessively removed. In the dry etching process, the byproducts are continuously accumulated, so that the sidewall film at the bottom of the sidewall of the first opening 106 is removed less than the sidewall film at the top of the sidewall of the first opening 106, that is: the thickness of the sidewall 107 formed on the top of the sidewall of the first opening 106 is thinner than the thickness of the sidewall 107 at the bottom of the sidewall of the first opening 106.
Also, after the control gate 113 is formed, the floating gate dielectric material film 102 at the bottom of the first opening 106 is removed, the floating gate dielectric material film 102 including silicon oxide. The process of removing the floating gate dielectric material film 102 at the bottom of the first opening 106 includes a wet process. Since the material of the first oxide layer 105 comprises silicon oxide, the etchant in the wet process reduces the dimension of the first oxide layer 105 in the direction parallel to the substrate 100, so that part of the top of the control gate 113 is exposed. The exposed top portion of control gate 113 is easily etched to form a pointed region 1 protruding towards first opening 106. The sharp corner regions 1 make the thickness of the subsequently formed sidewall 107 thinner. The thickness of the sidewall spacers 107 is small, so that the breakdown voltage between the word line 108 and the control gate 113 is small.
A method of increasing the breakdown voltage between the control gate 113 and word line 108 in the pointed region 1 comprises: the thickness of the sidewall 107 between the sharp region 1 control gate 113 and word line 108 is increased. However, the thickness of the sidewall 107 between the control gate 113 and the word line 107 in the sharp corner region 1 is increased, so that the thickness of the sidewall 107 formed by the bottom of the first opening 106 and the sidewall of the second opening is too thick, and the sidewall 107 and the control gate 113 are used as masks, the size of the formed floating gate 111 is larger, and the ratio between the floating gate 111 and the control gate 113 is too large, which is not favorable for improving the control effect of the control gate 113 on the floating gate 111.
To solve the above technical problem, the present invention provides a method for forming a flash memory device, including: providing a substrate, wherein the surface of the substrate is provided with a floating gate layer; forming a control gate on the surface of the floating gate layer, wherein the control gate is internally provided with a first opening for exposing the floating gate layer; forming a first oxide layer and a material layer positioned on the surface of the first oxide layer on the side wall of the first opening; oxidizing the material layer, and forming a second oxide layer on the surface of the control gate on the side wall of the first opening; etching the floating gate layer by taking the control gate and the second oxide layer as masks until the substrate is exposed to form a floating gate and a second opening positioned between the floating gates; word lines are formed within the first and second openings. The flash memory device formed by the method can balance the breakdown voltage between the control gate and the word line and the control effect of the control gate on the floating gate.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic structural diagrams of steps of a method for forming a flash memory device according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, and a floating gate layer 201 is formed on a surface of the substrate 200.
The substrate 200 provides a process platform for manufacturing a flash memory device, the substrate 200 includes a flash memory region (not shown) and a logic device region (not shown), and the flash memory device is formed on the substrate 200 in the flash memory region. In order to electrically isolate the flash memory region from the logic device region, an isolation structure (not shown) is used to electrically isolate the flash memory region from the logic device region.
The substrate 200 may be made of silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, silicon on insulator, germanium on insulator, or silicon germanium on insulator. In this embodiment, the material of the substrate 200 is silicon.
The floating gate layer 201 provides a process foundation for the subsequent formation of the floating gate of the flash memory device. The floating gate layer 201 is formed by a chemical vapor deposition process or a sputtering process. The material of the floating gate layer 201 includes polysilicon or metal doped with P-type or N-type ions. In this embodiment, the material of the floating gate layer 201 is polysilicon doped with N-type ions.
It should be noted that, in this embodiment, the manufacturing method of the flash memory device is performed in units of lot, that is: a batch of substrates 200 is processed at a time. In other embodiments, a method of manufacturing a flash memory device is provided in units of wafers, that is: one substrate at a time is processed.
In this embodiment, a fifth oxide layer (not shown) is further disposed between the substrate 200 and the floating gate layer 201. The material of the fifth oxide layer comprises silicon oxide. And the fifth oxide layer is used for blocking electrons in the subsequent floating gate.
In this embodiment, the floating gate layer 201 has a floating gate dielectric material film 202 on its surface and a control gate material film 203 on the surface of the floating gate dielectric material film 202.
In this embodiment, the floating gate dielectric material film 202 includes: a third oxide layer (not shown) on the surface of the floating gate layer 201, a nitride layer (not shown) on the surface of the third oxide layer, and a fourth oxide layer (not shown) on the surface of the nitride layer. The third oxide layer is made of silicon oxide, the nitride layer is made of silicon nitride, and the fourth oxide layer is made of silicon oxide. In other embodiments, the floating gate dielectric material film is a single layer structure of silicon oxide, and the forming process of the floating gate dielectric material film comprises a thermal oxidation process, an atomic layer deposition process or a chemical vapor deposition process.
The floating gate dielectric material film 202 is used for forming a floating gate dielectric layer in the following, and the floating gate dielectric layer is used for isolating the following floating gate and a control gate.
The material of the control gate material film 203 comprises polysilicon or metal doped with N-type or P-type ions, and the forming process of the control gate material film 203 comprises the following steps: a chemical vapor deposition process or a sputtering process.
The control gate material film 203 is used for the subsequent formation of a control gate.
Referring to fig. 5, a mask layer 204 is formed on a portion of the surface of the control gate material film 203, and the mask layer 204 has a mask opening (not shown) therein to expose the control gate material film 203; and forming a side wall 205 on the side wall of the mask layer 204.
The material of the mask layer 204 includes silicon nitride or titanium nitride. The sidewalls of the mask layer 204 are used for forming the sidewalls 205 subsequently.
The forming method of the side wall 205 includes: forming a side wall film on the top surface and the side wall of the mask layer 204; and removing the side wall film on the top surface of the mask layer 204, and forming a side wall 205 on the side wall of the mask layer 204.
The material of the side wall film comprises silicon oxide, and the forming process of the side wall film comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The process for removing the sidewall film on the top surface of the mask layer 204 includes a dry etching process.
The sidewall spacers 205 and the mask layer 204 are used as a mask for forming a control gate.
Referring to fig. 6, the control gate material film 203 is etched using the spacers 205 and the mask layer 204 as masks until the floating gate material film 202 is exposed, so as to form a control gate 206, and the control gate 206 has a first opening 250 therein, which exposes the floating gate material film 202.
The process for etching the control gate material film 203 includes a dry etching process with the spacers 205 and the mask layer 204 as masks.
Referring to fig. 7, the floating gate dielectric material film 202 (see fig. 6) at the bottom of the first opening 250 is removed to form a floating gate dielectric layer 207.
The process of removing the floating gate dielectric material film 202 at the bottom of the opening 250 includes a wet etching process. The significance of removing the floating gate dielectric material film 202 at the bottom of the initial second control gate 206 by using a wet etching process is that: the floating gate layer 201 can be easily stopped on the surface, which is beneficial to reducing the damage to the floating gate layer 201.
The parameters of the wet etching process comprise: the etching agent comprises phosphoric acid, sulfuric acid and hydrogen peroxide.
When the floating gate dielectric material film 202 at the bottom of the first opening 250 is removed, since the material of the sidewall spacer 205 includes silicon oxide, the etchant in the wet process reduces the dimension of the sidewall spacer 205 in the direction parallel to the substrate 200, so that part of the top of the control gate 206 is exposed. The exposed portion of the top of the control gate 206 is susceptible to etching to form a pointed region 11 protruding towards the second opening 250. The pointed regions 11 make the layer of material subsequently deposited in the pointed regions 11 thinner.
Referring to fig. 8, a first oxide layer 220 and a material layer 210 on the surface of the first oxide layer 220 are formed on the sidewalls of the first opening 250, the sidewall spacers 205 and the floating gate dielectric layer 207.
The material of the first oxide layer 220 includes silicon oxide, and the method for forming the first oxide layer 220 includes: forming a first oxide film on the surfaces of the mask layer 204, the side walls 205 and the floating gate layer 201, and on the side walls 205, the control gates 206 and the side walls of the floating gate dielectric layer 207; and removing the mask layer 204, the side wall 205 and the first oxide film on the surface of the floating gate layer 201 to form the first oxide layer 220.
The first oxidation film process comprises a high temperature oxidation process.
The thickness of the first oxide layer 220 is: 60 to 70 angstroms.
The first oxide layer 220 functions to include: in the subsequent oxidation process, the first oxide layer 220 is used to prevent the control gate 206 from being oxidized excessively and prevent the second oxide layer on the sidewall of the first opening 250 from being too thick, so that the ratio of the size of the control gate 206 to the size of the floating gate to be formed subsequently is not too small, which is beneficial to improving the control effect of the control gate 206 on the floating gate; the first oxide layer 220 serves as part of a subsequent second oxide layer that is used to form a mask for the floating gate.
The material of the material layer 210 includes polysilicon. The material layer 210 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. Although the thickness of the material layer 210 formed in the included angle region is made thinner by the pointed region 11, the subsequent material layer 210 is an oxide layer formed by an oxidation process, the thickness of the oxide layer is relatively thicker, and the oxide layer and the first oxide layer constitute a second oxide layer, and therefore, the thickness of the second oxide layer is thicker. The second oxide layer is used for isolating the subsequent control gate and the word line, so that the subsequent control gate is far away from the word line, and the breakdown voltage between the control gate and the word line is favorably improved.
The thickness of the material layer 210 is 150 to 250 angstroms. The thickness of the material layer 210 is chosen in the sense that: if the thickness of the material layer 210 is less than 150 angstroms, the thickness of the second oxide layer formed on the sidewall of the opening 250 by the subsequent oxide material layer 210 is still thinner, so that the breakdown voltage that can be sustained between the subsequent control gate and the word line is still smaller; if the thickness of the material layer 210 is greater than 250 angstroms, so that the thickness of the second oxide layer formed in the opening 250 is thicker, the ratio of the size of the floating gate to the size of the control gate formed by using the second oxide layer as a mask is too large, which is not favorable for controlling the floating gate by the control gate.
Referring to fig. 9, the material layer 210 (see fig. 8) is oxidized, and a second oxide layer 212 is formed on the surface of the control gate 206 on the sidewall of the first opening 250.
The process of oxidizing the material layer 210 (see fig. 8) includes: dry oxidation processes and wet oxidation processes.
The material layer 210 is formed by an oxidation process to form an oxide layer, so that the thickness of the oxide layer is relatively thick, and the thickness of the second oxide layer 212 formed by the oxide layer and the first oxide layer 220 (see fig. 8) is relatively thick, which is beneficial to improving the breakdown voltage between the control gate 206 and the subsequent word line.
Although the thickness of the material layer 210 in the angle region 11 is relatively thin, the material layer 210 is an oxide layer formed by an oxidation process, and the thickness of the oxide layer is relatively thick, so that the second oxide layer 212 formed by the first oxide layer 220 and the oxide layer is relatively thick, and the distance between the control gate 206 and the word line is relatively long, thereby being beneficial to improving the breakdown voltage between the control gate 206 and the word line.
Meanwhile, in the process of oxidizing the material layer 210 (see fig. 8), since the first oxide layer 220 is arranged between the material layer 210 and the control gate 206, the first oxide layer 220 can prevent the control gate 206 from being excessively oxidized, so that the thickness of the formed second oxide layer 212 is not too thick, and then the floating gate layer 201 is etched by using the second oxide layer 212 and the control gate 206 as masks, the size of the formed floating gate is not too large, and the ratio of the size of the floating gate to the size of the control gate 206 is not too large, which is beneficial to improving the control effect of the control gate 206 on the floating gate.
In this embodiment, only material layer 210 is oxidized. In other embodiments, portions of the control gate are also oxidized.
Referring to fig. 10, the floating gate layer 201 (see fig. 9) is etched using the second oxide layer 212 and the control gate 206 as masks until the top surface of the substrate 200 is exposed, forming floating gates 215 and second openings (not shown) between the floating gates 215.
The process for etching the floating gate layer 201 includes a dry etching process with the second oxide layer 212 and the control gate 206 as masks.
Because the thickness of the second oxide layer 212 is relatively thin, the size of the formed floating gate 215 is not too large by using the second oxide layer 212 and the control gate 206 as masks, and the ratio of the size of the floating gate 215 to the size of the control gate 206 is not too large, which is beneficial to improving the control effect of the control gate 206 on the floating gate 215.
Moreover, the thickness of the second oxide layer 212 is relatively large, which is beneficial to increase the breakdown voltage between the control gate 206 and the subsequent word line.
Referring to fig. 11, a tunnel oxide layer 214 is formed on the floating gate 215 and the second oxide layer 212; word line 213 is formed in second opening and first opening 250 in the surface of tunnel oxide layer 214.
After forming the floating gate 215 and before forming the word line 213, the forming method further includes: removing the fifth oxide layer at the bottom of the second opening; the process for removing the fifth oxide layer at the bottom of the second opening comprises the following steps: wet etching process; the parameters of the wet etching process comprise: the etching agent comprises hydrofluoric acid, sulfuric acid and hydrogen peroxide.
Since the second oxide layer 212 is formed by an oxidation process, the second oxide layer 212 is made denser, and the removal amount of the second oxide layer 212 by the etchant is small, after the cleaning process, the thickness of the second oxide layer 212 is thicker, and the distance between the control gate 206 and the word line 213 is still longer, so that the control gate 206 and the word line 213 can still bear a larger breakdown voltage.
The material of tunnel oxide layer 214 includes silicon oxide, and the forming process of tunnel oxide layer 214 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the word line 213 includes polysilicon.
The method for forming the word line 213 comprises the following steps: forming a layer of word line material on the surface of tunnel oxide layer 214, wherein the layer of word line material fills the second opening and the first opening 250; tunnel oxide layer 214 on the surface of the layer of word line material and mask layer 204 is planarized until the top surface of mask layer 204 is exposed, forming word line 213.
Referring to fig. 12, a cap layer 230 is formed on the surface of the word line 213; after the cap layer 230 is formed, the mask layer 204 (see fig. 11), and the control gate 206 (see fig. 11), the floating gate dielectric layer 207 and the floating gate 215 at the bottom of the mask layer 204 are removed, so as to form a first memory cell (not shown) and a second memory cell (not shown) respectively located at two sides of the word line 213.
The capping layer 230 is used for protecting the word line 213 from being damaged when the mask layer 204, the control gate 206 at the bottom of the mask layer 204, the floating gate dielectric layer 207 and the floating gate 215 are removed later.
The material of the cap layer 230 includes silicon oxide. In this embodiment, the cap layer 230 is formed by a thermal oxidation process. In other embodiments, the cap layer formation process comprises a chemical vapor deposition process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. A method of forming a flash memory device, comprising:
providing a substrate, wherein the surface of the substrate is provided with a floating gate layer;
forming a control gate on the surface of the floating gate layer, wherein the control gate is internally provided with a first opening for exposing the floating gate layer;
a floating gate dielectric layer is also arranged between the floating gate layer and the control gate;
the forming method of the floating gate dielectric layer and the control gate comprises the following steps:
forming a floating gate dielectric material film on the surface of the floating gate layer; forming a control gate material film on the surface of the floating gate dielectric material film, wherein the surface of the control gate material film is provided with a mask layer, and a mask opening exposing the surface of the control gate material film is formed in the mask layer; forming a side wall on the side wall of the mask opening; etching the control gate material film by taking the side wall and the mask layer as masks until the floating gate dielectric material film is exposed to form the control gate, wherein the control gate is internally provided with a first opening;
removing the floating gate dielectric material film at the bottom of the first opening to form a floating gate dielectric layer;
when the floating gate dielectric material film at the bottom of the first opening is removed, a sharp-angled region protruding towards the first opening is formed at the top of the exposed part of the control gate;
forming a first oxide layer and a material layer positioned on the surface of the first oxide layer on the side walls of the first opening, the side walls and the floating gate dielectric layer;
oxidizing the material layer, and forming a second oxide layer on the surface of the control gate on the side wall of the first opening;
etching the floating gate layer by taking the control gate and the second oxide layer as masks until the substrate is exposed to form floating gates and second openings positioned between the floating gates;
word lines are formed within the first and second openings.
2. The method of forming a flash memory device of claim 1, wherein the material layer has a thickness of: 150 to 250 angstroms.
3. The method of forming a flash memory device of claim 1, wherein the material of the material layer comprises silicon.
4. The method of forming a flash memory device of claim 1, wherein the process of oxidizing the material layer comprises a dry oxidation process and a wet oxidation process.
5. The method of forming a flash memory device of claim 1, wherein the method of forming the floating gate dielectric layer and the control gate further comprises: and removing the floating gate dielectric material film at the bottom of the first opening by adopting a wet etching process until the floating gate layer is exposed to form a floating gate dielectric layer.
6. The method of claim 5, wherein the floating gate dielectric material film comprises a third oxide layer on the surface of the floating gate layer, a nitride layer on the surface of the third oxide layer, and a fourth oxide layer on the surface of the nitride layer; the third oxide layer is made of silicon oxide, the nitride layer is made of silicon nitride, and the fourth oxide layer is made of silicon oxide; the parameters of the wet etching process comprise: an etchant, the etchant comprising: phosphoric acid, sulfuric acid and hydrogen peroxide.
7. The method of claim 1, wherein a fifth oxide layer is further formed between the floating gate layer and the substrate; after the floating gate is formed and before the word line is formed, the forming method further comprises: removing the fifth oxide layer at the bottom of the second opening; the process for removing the fifth oxide layer at the bottom of the second opening comprises the following steps: wet etching process; the parameters of the wet etching process comprise: the etching agent comprises hydrofluoric acid, sulfuric acid and hydrogen peroxide.
8. The method of forming a flash memory device of claim 1, wherein the first oxide layer has a thickness of: 60 to 70 angstroms.
9. The method of forming a flash memory device of claim 5, further comprising, after forming the word line: forming a cap layer on the surface of the word line; and after the cap layer is formed, removing the mask layer and the control gate and the floating gate at the bottom of the mask layer to respectively form a first storage unit and a second storage unit which are positioned at two sides of the word line.
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