CN102800679A - Formation method for memory cell of flash memory - Google Patents
Formation method for memory cell of flash memory Download PDFInfo
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- CN102800679A CN102800679A CN2012103016591A CN201210301659A CN102800679A CN 102800679 A CN102800679 A CN 102800679A CN 2012103016591 A CN2012103016591 A CN 2012103016591A CN 201210301659 A CN201210301659 A CN 201210301659A CN 102800679 A CN102800679 A CN 102800679A
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Abstract
The invention discloses a formation method for the memory cell of a flash memory. The formation method comprises the following steps of: providing a semiconductor substrate, wherein a floating gate layer is arranged on the surface of the semiconductor substrate, a first opening is arranged in the floating gate layer, the surface of the semiconductor substrate is exposed out of the first opening, the floating gate layer and the semiconductor substrate are mutually isolated via an insulating layer, a control gate layer is arranged on the surface of the floating gate layer, the control gate layer and the floating gate layer are mutually isolated via an interlayer dielectric layer, a mask layer is arranged on the surface of the control gate layer, a second opening is arranged in the mask layer, the second opening is communicated with the first opening, and the surface of the control gate layer is exposed out of the second opening; forming a first side wall on the sidewall of the first opening; forming a second side wall on the sidewall of the second opening, wherein the top of the second side wall is level with the surface of the mask layer; and forming source line layers in the first opening and the second opening by adopting a selective epitaxial deposition process, wherein the tops of the source line layers are not higher than the surface of the mask layer. The formed memory cell of the flash memory is stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of memory cell of flash memory.
Background technology
In present semiconductor industry, IC products mainly can be divided into the three major types type: analog circuit, digital circuit and DA combination circuit, wherein memory device is an important kind in the digital circuit.In recent years, in memory device, the development of flash memory (flash memory) is particularly rapid.The main feature of flash memory is under situation about not powering up, can keep canned data for a long time; And have integrated level height, access speed fast, be easy to wipe and advantage such as rewriting, thereby obtained using widely in multinomial fields such as microcomputer, automation controls.
In the prior art, the memory cell of flash memory please refer to Fig. 1, comprising:
Yet in the memory cell of the formed flash memory of prior art, the size of source line layer 108 is difficult to control, causes the unstable properties of flash memory.
Memory cell of more flash memories and forming method thereof please refer to the document us that publication number is US 2005/0181563A1.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of memory cell of flash memory, makes the size composite design standard of formed source line layer, makes the memory cell stable performance of formed flash memory.
For addressing the above problem, the present invention provides a kind of formation method of memory cell of flash memory, comprising: Semiconductor substrate is provided; Said semiconductor substrate surface has floating gate layer, has first opening in the said floating gate layer, and said first opening exposes the surface of Semiconductor substrate; Isolate each other through insulating barrier between said floating gate layer and the Semiconductor substrate, said floating gate layer surface has control grid layer, isolates each other through interlayer dielectric layer between said control grid layer and the floating gate layer; Said control grid layer surface has mask layer; Have second opening in the said mask layer, said second opening and first opening connect, and said second opening exposes the control grid layer surface; Sidewall at said first opening forms first side wall; Sidewall at said second opening forms second side wall, the top of said second side wall and said mask layer flush; Adopt the selective epitaxial depositing operation in said first opening and second opening, to form source line layer, the top of said source line layer is not higher than the surface of said mask layer.
Alternatively, the material of said source line layer is a polysilicon, highly is 2000 dusts ~ 3000 dusts.
Alternatively; Said selective epitaxial depositing operation is: deposition gases comprises silicon source gas and carrier gas; The flow of said silicon source gas is 1 standard milliliter per minute ~ 1000 standard milliliter per minutes, and the flow of said carrier gas is 0.1 standard Liter Per Minute ~ 50 standard Liter Per Minutes, and temperature is 500 ~ 800 degrees centigrade; Pressure is 1 holder ~ 100 holders, and the time is 0.1 h ~ 1 hour.
Alternatively, said silicon source gas is SiH
4Or SiH
2Cl
2, said carrier gas is nitrogen or hydrogen.
Alternatively, also comprise: after the line layer of the source of formation, form word line layer, have oxide layer between said word line layer and floating gate layer, control grid layer and the Semiconductor substrate and isolate each other in said floating gate layer, control grid layer and mask layer both sides; Form the 3rd side wall in said word line layer both sides.
Alternatively, the material of said word line layer is a polysilicon, and the material of said the 3rd side wall is that silica, silicon nitride or silicon nitride and silica multilayer are overlapping.
Alternatively, the ion injection is carried out in line layer, second side wall, mask layer and the 3rd side wall both sides in said source, forms the drain region.
Alternatively, the material of said floating gate layer and control grid layer is a polysilicon.
Alternatively, the material of said mask layer is a silicon nitride
Alternatively, the material of said first side wall and second side wall is a silica.
Alternatively, the material of said insulating barrier is a silica, and said interlayer dielectric layer is the laminated construction of silica-silicon-nitride and silicon oxide.
Alternatively, the formation method of said floating gate layer, control grid layer, mask layer, first side wall and second side wall is: form insulation film, floating boom film, interlayer medium film, control gate film and mask film successively at said semiconductor substrate surface; Etched portions mask film also exposes the control gate film surface, forms second opening and mask layer; Sidewall at said second opening forms second side wall; With said second side wall and mask layer is mask, and the said control gate film of etching, interlayer medium film, floating boom film and insulation film also expose semiconductor substrate surface, form first opening; Form first side wall at said first opening sidewalls.
Alternatively, before forming first side wall, the Semiconductor substrate of said first open bottom is carried out ion inject, form the source region.
Alternatively, the material of said Semiconductor substrate is silicon, SiGe, carborundum or silicon-on-insulator.
Compared with prior art, technical scheme of the present invention has the following advantages:
When adopting the selective epitaxial depositing operation in said first opening and second opening, to form source line layer; The Semiconductor substrate of said first open bottom is as Seed Layer; And from said first open bottom growth source line layer that makes progress; Therefore the height of formed source line layer can be controlled through the parameter of controlling said selective epitaxial depositing operation, can make the size composite design standard of formed source line layer; And, adopt said selective epitaxial process when same semiconductor substrate surface forms the source line layer in the memory cell of different flash memories, consistent size between each source line layer, the resistance of then said each source line layer is consistent, makes the stable performance of formed flash memory.
Further; After adopting said selective epitaxial depositing operation to form source line layer; Because the consistent size of said source line layer; And meet design standard, can make subsequent technique consistent size between formed each the complete memory cell of same semiconductor substrate surface, therefore the stable performance of formed flash memory.
Description of drawings
Fig. 1 is the structural representation of memory cell of the flash memory of prior art;
Fig. 2 is the schematic flow sheet of method of the memory cell of the said flash memory of the embodiment of the invention;
Fig. 3 to Fig. 7 is the cross-sectional view of forming process of the memory cell of the said flash memory of the embodiment of the invention.
Embodiment
Of background technology, in the memory cell of the formed flash memory of prior art, the size of source line layer is difficult to control, causes the unstable properties of flash memory.
Through discovering of inventor; Because in the prior art; Please refer to Fig. 1, the formation method of said source line layer 108 is: adopt chemical vapor deposition method or physical gas-phase deposition in said first opening and second opening and said mask layer 106 surperficial formation source line films; Adopt CMP process, remove the source line film that is higher than said mask layer 106 surfaces, form source line layer 108; The formation complex process of said source line layer 108 influences manufacturing cycle of product.
And prior art can be in the memory cell with the some flash memories of formation on semi-conductive substrate 100 surface; When the source line film that adopts CMP process to different memory cell carries out planarization; Because said CMP process is inconsistent for the grinding rate of whole Semiconductor substrate 100; The height of source line layer 108 that causes being positioned at after the planarization Semiconductor substrate 100 surperficial diverse locations is different; Make the size of said source line layer 108 be difficult to control, and be not inconsistent with design standard; Concrete; Said CMP process is lower at the grinding rate of the center and peripheral of said Semiconductor substrate 100; And other regional grinding rates are higher, and the source line layer 108 that therefore is formed at said Semiconductor substrate 100 center and peripherals is higher, and other regional source line layer heights are lower; Thereby, make the size of formed source line layer 108 be difficult to control; Because the difference between each source line layer 108 size can cause the resistance in said each source line layer 108 inconsistent, makes formed flash memory performance unstable.
In addition, when said source line film is carried out planarization, can carry out to a certain degree overground, the said mask layer 106 of planarization; Because said CMP process is inconsistent to the grinding rate on whole Semiconductor substrate 100 surfaces; Can cause between each memory cell after the planarization height of mask layer 106 and source line layer 108 inconsistent, thereby cause the size of final formed each memory cell inconsistent.
Through further discovering of inventor; When adopting the selective epitaxial depositing operation; And with the Semiconductor substrate of said first open bottom as silicon seed layer; During the source line layer that in said first opening and second opening, forms, the height of formed source line layer can be controlled through said selective epitaxial depositing operation, and the source line layer height in the memory cell of the formation and the different flash memories of same semiconductor substrate surface is consistent; Therefore, the size of formed source line layer is controlled easily, and the consistent size between the homology line layer not, makes formed flash memory performance stable.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 2 is the schematic flow sheet of method of the memory cell of the said flash memory of the embodiment of the invention, comprises step:
Step S101 forms insulation film, floating boom film, interlayer medium film, control gate film and mask film successively at said semiconductor substrate surface;
Step S102 removes part mask film and exposes the control gate film surface, forms second opening and mask layer; Sidewall at said second opening forms second side wall;
Step S103 is a mask with said second side wall and mask layer, removes said control gate film, interlayer medium film, floating boom film and insulation film and exposes semiconductor substrate surface, forms first opening; Form first side wall at said first opening sidewalls;
Step S104 adopts the selective epitaxial depositing operation in said first opening and second opening, to form source line layer, and the top of said source line layer is not higher than the surface of said mask layer;
Step S105 after the line layer of the source of formation, forms word line layer in said floating gate layer, control grid layer and mask layer both sides, isolates each other through oxide layer between said word line layer and floating gate layer, control grid layer and the Semiconductor substrate; Form the 3rd side wall in said word line layer both sides.
Below will combine accompanying drawing that the formation method of the memory cell of the said flash memory of the embodiment of the invention is described, Fig. 3 to Fig. 7 is the cross-sectional view of forming process of the memory cell of the said flash memory of the embodiment of the invention.
Please refer to Fig. 3, form insulation film 201, floating boom film 202, interlayer medium film 203, control gate film 204 and mask film 205 successively on said Semiconductor substrate 200 surfaces.
Said Semiconductor substrate 200 is used to subsequent technique provides workbench, and the material of said Semiconductor substrate 200 is monocrystalline silicon, SiGe, carborundum or silicon-on-insulator; Because when subsequent technique forms source line layer; Adopt the selective epitaxial depositing operation with the silicon on said Semiconductor substrate 200 surfaces as Seed Layer; Growing single-crystal silicon in said first opening and second opening; In order to form highly controlled source line layer, therefore the material of said Semiconductor substrate 200 need comprise silicon atom; In the present embodiment, said Semiconductor substrate 200 is injected through p type ion, forms p type well region, and the source region of follow-up formation and the conduction type in drain region are the n type; In other embodiments, said Semiconductor substrate 200 is injected through n type ion, forms n type well region, and the source region of follow-up formation and the conduction type in drain region are the p type.
The material of said insulation film 201 is a silica, and formation technology is chemical vapor deposition method, physical gas-phase deposition or thermal oxidation technology, and said insulation film 201 is used for isolation of semiconductor substrate 200 and floating boom film 202; The material of said floating boom film 202 and control gate film 204 is a polysilicon, and said interlayer medium film 203 is the laminated construction of silica-silicon-nitride and silicon oxide; The material of said mask film 205 is a silicon nitride, and the thickness of said mask film 205 is 1500 dusts ~ 3000 dusts; The formation technology of said floating boom film 202, interlayer medium film 203, control gate film 204 and mask film 205 is chemical vapor deposition method or physical gas-phase deposition; Said floating boom film 202 is used for forming floating gate layer and control grid layer at subsequent technique with control gate film 204.
The thickness of said mask film 205 has determined the height of the source line layer of follow-up formation; And the size of the memory cell of flash memory; And said mask film 205 adopts chemical vapor deposition method or physical gas-phase deposition to form; So the controllable thickness of said mask film 205, so the controllable size of the memory cell of formed flash memory.
Please refer to Fig. 4, remove part mask film 205 (like Fig. 3) and expose control gate film 204 surfaces, form second opening 206 and mask layer 205a; Sidewall at said second opening 206 forms second side wall 207.
The formation technology of said second opening 206 is: form photoresist layer on said mask film 205 surfaces, said photoresist layer exposes the position that needs to form second opening 206; With said photoresist layer is mask, and the said mask film 205 of dry etching or wet etching exposes said control gate film 204 surfaces, forms mask layer 205a; The size that mask layer 205a has confirmed floating gate layer and control grid layer that forms, and the thickness of said mask layer 205a determined the height of the source line layer of follow-up formation, and said mask layer 205a thickness can accurately be controlled through depositing operation.
The material of said second side wall 207 is a silica, and the formation technology of said second side wall 207 is: adopt the good physical gas-phase deposition of chemical vapor deposition method to form the second side wall film in the sidewall and the bottom of the said mask layer 205a surface and second opening 206; Adopt back the said second side wall film of etching technics etching, remove the second side wall film of said mask layer 205a and second opening, 206 bottoms, form second side wall 207; Said second side wall 207 is in order to isolate the source line layer of said control gate film 204 and follow-up formation.
Please refer to Fig. 5; Is mask with said second side wall 207 with mask layer 205a; Remove said control gate film 204, interlayer medium film 203, floating boom film 202 and insulation film 201 and expose Semiconductor substrate 200 surfaces; Form first opening 208, and control grid layer 204a, interlayer dielectric layer 203a, floating gate layer 202a and insulating barrier 201a; Form first side wall 209 at said first opening, 208 sidewalls.
The formation technology of said first opening 208 is dry etching or wet etching; In the present embodiment, when forming said first opening 208, be that the mask removal needs to form control gate film 204, interlayer medium film 203, floating boom film 202 and the insulation film 201 beyond the memory cell position with said mask layer 205a; Formed first opening 208 and second opening 206 connect, and are used to form source line layer in said first opening 208 and second opening, the 206 inherent subsequent techniques.
After forming first opening 208, the Semiconductor substrate 200 of said first opening 208 bottoms is carried out ion inject, form the source region; In the present embodiment, said source region is the n type; In other embodiments, when said well region was the n type, said source region was the p type.
After forming the source region, form first side wall 209 at the sidewall of said first opening 208, the material of said first side wall 209 is a silica, the formation technology of said first side wall 209 is identical with second side wall 207, does not give unnecessary details at this.
Please refer to Fig. 6, adopt selective epitaxial depositing operation formation source line layer 210 in said first opening 208 (like Fig. 5) and second opening 206 (like Fig. 6), the top of said source line layer 210 is not higher than the surface of said mask layer 205a.
The material of said source line layer 210 is a polysilicon; The height of said source line layer 210 is by the thickness decision of mask layer 205a, and the height of said source line layer 210 is 2000 dusts ~ 3000 dusts; Said selective epitaxial depositing operation is: deposition gases comprises silicon source gas and carrier gas; The flow of said silicon source gas is 1 standard milliliter per minute ~ 1000 standard milliliter per minutes; The flow of said carrier gas is 0.1 standard Liter Per Minute ~ 50 standard Liter Per Minutes; Temperature is 500 ~ 800 degrees centigrade, and pressure is 1 holder ~ 100 holders, and the time is 0.1 h ~ 1 hour; Wherein, said silicon source gas comprises SiH
4, SiH
2Cl
2In one or both, said carrier gas comprises one or both in nitrogen, the hydrogen.
In said selective epitaxial deposition process; Semiconductor substrate 200 surfaces of said first opening 206 bottoms are as the Seed Layer of growing single-crystal silicon, fill the source line layer 210 of full said first opening 208 and second opening 206 by the said first opening 206 bottoms square one-tenth that makes progress gradually; Therefore, the height of formed source line layer 210 can accurately be controlled through said selective epitaxial depositing operation; And; Be formed at the height of the source line layer 210 in the memory cell of the flash memory of semi-conductive substrate 200 surperficial diverse locations consistent; Make the resistance of source line layer 210 of formed each memory cell identical; When formed each memory cell was worked, operating current was stable, thus the memory cell stable performance of formed flash memory; In addition, it is simple to adopt said selecting property epitaxial deposition process to form source line layer 210 technology, and can save the processing step of chemico-mechanical polishing, thereby work simplification, the cost of the memory cell that forms flash memory are reduced and the output capacity height.
Secondly, owing to the height of said source line layer 210 can accurately be controlled, therefore; Subsequent technique is reference with the height of said source line layer 210; The size of formed word line and the 3rd side wall also can be able to control, and makes word line and the 3rd side wall can meet pre-set dimension, thus the consistent size of formed each memory cell; And meet design standard, be suitable for integrated.
Please refer to Fig. 7; After the source of formation line layer 210; Form word line layer 211 in said floating gate layer 202a, control grid layer 204a and mask layer 205a both sides, isolate each other through oxide layer 212 between said word line layer 211 and floating gate layer 202a, control grid layer 204a and the Semiconductor substrate 200; Form the 3rd side wall 213 in said word line layer 211 both sides.
The material of said word line layer 211 is a polysilicon; The formation technology of said word line layer 211 and oxide layer 212 is: adopt depositing operation, preferably chemical vapor deposition method forms silicon oxide film and word line layer films on said Semiconductor substrate 200, floating gate layer 202a, control grid layer 204a, mask layer 205a and source line layer 210 surface; Adopt back etching technics to remove the silicon oxide film and the word line layer film on said mask layer 205a and source line layer 210 surface, form silicon oxide layer 212 and word line layer 211 in said floating gate layer 202a, control grid layer 204a and mask layer 205a both sides; Therefore, the size of said word line layer 211 is by the height decision of said source line layer 210, and the height of said source line layer 210 can accurately be controlled through adjustment selective epitaxial depositing operation, and the size of said word line layer 211 is controlled easily.
Said the 3rd side wall 213 is made up of the individual layer of silica or silicon nitride, or is overlapped by silicon nitride and silica multilayer; The formation technology of said the 3rd side wall 213 is identical with the formation technology of said first side wall 209 and second side wall 207, repeats no more at this.
In the present embodiment, after forming said the 3rd side wall 213, be mask with said the 3rd side wall 213, word line layer 211, mask layer 205a and source line layer 210, carry out ion in said the 3rd side wall 213 both sides and inject, form the drain region; In the present embodiment, said drain region is the n type; When the well region in the Semiconductor substrate 200 was the n type, said drain region was the p type.
In other embodiments, before forming said the 3rd side wall layer 213, be mask with said word line layer 211, mask layer 205a and source line layer 210, carry out the light dope ion in said word line layer 211 both sides and inject; After forming the 3rd side wall 213, carry out heavy doping ion in said the 3rd side wall 213 both sides and inject, form the drain region.
In the present embodiment; Adopt the selective epitaxial depositing operation to form the source line layer 210 of the memory cell of flash memory; The height of said source line layer 210 can accurately be controlled through regulating said selective epitaxial deposition process parameters; And be positioned at the height of the source line layer 210 of the memory cell of semi-conductive substrate 200 surperficial diverse locations consistent, thereby make the stable performance of formed flash memory; In addition,, serve as also to be consistent with the height of said source line layer 210, thereby make the size homogeneous of formed each memory cell, be suitable for integrated with reference to the word line layer 211 that forms and the size of the 3rd side wall 213 because the height of each source line layer 210 is consistent.
In sum; When adopting the selective epitaxial depositing operation in said first opening and second opening, to form source line layer; The Semiconductor substrate of said first open bottom is as Seed Layer; And from said first open bottom growth source line layer that makes progress, therefore the height of formed source line layer can be controlled through the parameter of controlling said selective epitaxial depositing operation, can make the compound standard that relates to of size of formed source line layer; And, adopt said selective epitaxial process when same semiconductor substrate surface forms the source line layer in the memory cell of different flash memories, consistent size between each source line layer, the resistance of then said each source line layer is consistent, makes the stable performance of formed flash memory.
Further; After adopting said selective epitaxial depositing operation to form source line layer; Because the consistent size of said source line layer; And meet design standard, can make subsequent technique consistent size between formed each the complete memory cell of same semiconductor substrate surface, therefore the stable performance of formed flash memory.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (14)
1. the formation method of the memory cell of a flash memory is characterized in that, comprising:
Semiconductor substrate is provided, and said semiconductor substrate surface has floating gate layer, has first opening in the said floating gate layer; Said first opening exposes the surface of Semiconductor substrate; Isolate each other through insulating barrier between said floating gate layer and the Semiconductor substrate, said floating gate layer surface has control grid layer, isolates each other through interlayer dielectric layer between said control grid layer and the floating gate layer; Said control grid layer surface has mask layer; Have second opening in the said mask layer, said second opening and first opening connect, and said second opening exposes the control grid layer surface;
Sidewall at said first opening forms first side wall;
Sidewall at said second opening forms second side wall, the top of said second side wall and said mask layer flush;
Adopt the selective epitaxial depositing operation in said first opening and second opening, to form source line layer, the top of said source line layer is not higher than the surface of said mask layer.
2. the formation method of the memory cell of flash memory according to claim 1 is characterized in that the material of said source line layer is a polysilicon, highly is 2000 dusts ~ 3000 dusts.
3. like the formation method of the memory cell of the said flash memory of claim 2; It is characterized in that said selective epitaxial depositing operation is: deposition gases comprises silicon source gas and carrier gas, the flow of said silicon source gas is 1 standard milliliter per minute ~ 1000 standard milliliter per minutes; The flow of said carrier gas is 0.1 standard Liter Per Minute ~ 50 standard Liter Per Minutes; Temperature is 500 ~ 800 degrees centigrade, and pressure is 1 holder ~ 100 holders, and the time is 0.1 h ~ 1 hour.
4. the formation method of the memory cell of flash memory according to claim 1 is characterized in that said silicon source gas is SiH
4Or SiH
2Cl
2, said carrier gas is nitrogen or hydrogen.
5. the formation method of the memory cell of flash memory according to claim 1; It is characterized in that; Also comprise: after the line layer of the source of formation; Form word line layer in said floating gate layer, control grid layer and mask layer both sides, have oxide layer between said word line layer and floating gate layer, control grid layer and the Semiconductor substrate and isolate each other; Form the 3rd side wall in said word line layer both sides.
6. like the formation method of the memory cell of the said flash memory of claim 5, it is characterized in that the material of said word line layer is a polysilicon, the material of said the 3rd side wall is that silica, silicon nitride or silicon nitride and silica multilayer are overlapping.
7. like the formation method of the memory cell of the said flash memory of claim 5, it is characterized in that line layer, second side wall, mask layer, word line layer and the 3rd side wall both sides are carried out ion and injected in said source, form the drain region.
8. the formation method of the memory cell of flash memory according to claim 1 is characterized in that the material of said floating gate layer and control grid layer is a polysilicon.
9. the formation method of the memory cell of flash memory according to claim 1 is characterized in that the material of said mask layer is a silicon nitride.
10. the formation method of the memory cell of flash memory according to claim 1 is characterized in that the material of said first side wall and second side wall is a silica.
11. the formation method of the memory cell of flash memory is characterized in that according to claim 1, the material of said insulating barrier is a silica, and said interlayer dielectric layer is the laminated construction of silica-silicon-nitride and silicon oxide.
12. the formation method of the memory cell of flash memory according to claim 1; It is characterized in that the formation method of said floating gate layer, control grid layer, mask layer, first side wall and second side wall is: form insulation film, floating boom film, interlayer medium film, control gate film and mask film successively at said semiconductor substrate surface; Etched portions mask film also exposes the control gate film surface, forms second opening and mask layer; Sidewall at said second opening forms second side wall; With said second side wall and mask layer is mask, and the said control gate film of etching, interlayer medium film, floating boom film and insulation film also expose semiconductor substrate surface, form first opening; Form first side wall at said first opening sidewalls.
13. the formation method like the memory cell of the said flash memory of claim 12 is characterized in that, before forming first side wall, the Semiconductor substrate of said first open bottom is carried out ion inject, and forms the source region.
14. the formation method of the memory cell of flash memory is characterized in that according to claim 1, the material of said Semiconductor substrate is silicon, SiGe, carborundum or silicon-on-insulator.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346127A (en) * | 2013-06-28 | 2013-10-09 | 上海宏力半导体制造有限公司 | Flash memory device structure and manufacturing method |
| CN104465664A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and manufacturing method thereof |
| CN106206453A (en) * | 2016-08-30 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | The forming method of memorizer |
| CN106298790A (en) * | 2016-09-18 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN107230678A (en) * | 2017-08-09 | 2017-10-03 | 上海华虹宏力半导体制造有限公司 | The manufacture method of flash memory |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN112838008A (en) * | 2021-01-08 | 2021-05-25 | 上海华虹宏力半导体制造有限公司 | Process method of floating gate type split gate flash memory device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050141276A1 (en) * | 2003-12-26 | 2005-06-30 | Sharp Kabushiki Kaisha | Semiconductor memory device and production method therefor |
| CN101155648A (en) * | 2005-01-31 | 2008-04-02 | 应用材料公司 | Low temperature etchant for treatment of silicon-containing surfaces |
| US20100197101A1 (en) * | 2006-03-22 | 2010-08-05 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device and related method |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
| CN102637696A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Memory cell of flash memory, and formation method thereof |
-
2012
- 2012-08-22 CN CN201210301659.1A patent/CN102800679B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050141276A1 (en) * | 2003-12-26 | 2005-06-30 | Sharp Kabushiki Kaisha | Semiconductor memory device and production method therefor |
| CN101155648A (en) * | 2005-01-31 | 2008-04-02 | 应用材料公司 | Low temperature etchant for treatment of silicon-containing surfaces |
| US20100197101A1 (en) * | 2006-03-22 | 2010-08-05 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device and related method |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
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