CN104064463A - Transistor and formation method thereof - Google Patents
Transistor and formation method thereof Download PDFInfo
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- CN104064463A CN104064463A CN201310092797.8A CN201310092797A CN104064463A CN 104064463 A CN104064463 A CN 104064463A CN 201310092797 A CN201310092797 A CN 201310092797A CN 104064463 A CN104064463 A CN 104064463A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides a transistor and a formation method thereof. The formation method of the transistor comprises: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of separating layers, openings are formed between neighboring separating layers, the bottoms of the openings are provided with threshold voltage adjusting layers, and the threshold voltage adjusting layers are internally provided with doped ions; forming barrier layers on the surfaces of the threshold voltage adjusting layers and channel layers on the surfaces of the barrier layers, wherein the channel layers are at intrinsic states, and the barrier layers are used for preventing penetration by the doped ions in the threshold voltage adjusting layers; forming grid structures on the surfaces of the channel layers, wherein the surfaces of the grid structures are flush with the surfaces of the separating layers; removing the separating layers until the semiconductor substrate is exposed; and after the separating layers are removed, forming a doping layer on the surface of the semiconductor substrate at the two sides of the threshold voltage adjusting layers, the separating layers, the channels layers and the grid structures, wherein the surface of the doping layer is not lower than the surfaces of the channel layers. The formed transistor is lower in power consumption and stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistor and forming method thereof.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor device in integrated circuit, especially MOS(Metal Oxide Semiconductor, Metal-oxide-semicondutor) size of device constantly dwindles, and meets the miniaturization of integrated circuit development and integrated requirement with this.In the process that continues to dwindle in the size of MOS transistor device, existing technique has been subject to challenge using silica or silicon oxynitride as the technique of gate dielectric layer.There are some problems using silica or silicon oxynitride as the transistor that gate dielectric layer was formed, comprised that leakage current increases and the diffusion of impurity, thereby affect transistorized threshold voltage, and then affect the performance of semiconductor device.
Prior art, in order accurately to control transistorized threshold voltage, can be adulterated ion to regulate in transistorized channel region.As shown in Figure 1, be the transistorized cross-sectional view in the channel region of prior art with doping ion, comprising: Semiconductor substrate 100; Be positioned at the doped region 110 of Semiconductor substrate 100; Be positioned at the gate dielectric layer 101 on 110 surfaces, doped region; Be positioned at the grid layer 102 on gate dielectric layer 101 surfaces; Be positioned at the surperficial side wall 103 of Semiconductor substrate 100 of gate dielectric layer 101 and grid layer 102 both sides; Be positioned at source region and the drain region 104 of the Semiconductor substrate 100 of side wall 103 and grid layer 102 both sides.Wherein, in described doped region 110, there is the ion that can regulate transistor threshold voltage, described doped region 110 in the time that transistor is worked as channel region.
But along with constantly dwindling of transistor feature size, transistorized threshold V T but cannot correspondingly reduce, and causes transistor dissipation excessive, is unfavorable for the integrated of system.
The more adjustable transistorized related data of multi-Vt please refer to the U.S. patent documents that publication number is US2012/0299111.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, reduces transistorized power consumption, and makes transistorized stable performance.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprise: Semiconductor substrate is provided, described semiconductor substrate surface has some separators, between adjacent separator, form opening, described open bottom has threshold voltage adjustments layer, in described threshold voltage adjustments layer, has doping ion; Form barrier layer and be positioned at the channel layer of described barrier layer surface on described threshold voltage adjustments layer surface, described channel layer is eigenstate, and described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer; Form grid structure on described channel layer surface, the surface of described grid structure flushes with insulation surface; Remove described separator until expose Semiconductor substrate; After removing described separator, form doped layer at the semiconductor substrate surface of described threshold voltage adjustments layer, separator, channel layer and grid structure both sides, the surface of described doped layer is not less than channel layer surface.
Optionally, the material on described barrier layer is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material.
Optionally, the formation technique on described barrier layer is selective epitaxial depositing operation.
Optionally, the material of described channel layer is silicon, and the formation technique of described channel layer is selective epitaxial depositing operation, and the thickness of described channel layer is 5 nanometer～20 nanometers.
Optionally, also comprise: the ion that adulterates in described channel layer, described doping ion is one or both in germanium and carbon, and the mol ratio of described doping ion and silicon atom is 0.01～0.5, and described doping ion is doped in channel layer by in-situ doped technique.
Optionally, the material of described threshold voltage adjustments layer is silicon, in described silicon materials, doped with one or more combinations in carbon, germanium, tin and III-V family ion, described threshold voltage adjustments layer is formed in the semiconductor substrate surface of described open bottom or the Semiconductor substrate of open bottom.
Optionally, in the time that described threshold voltage adjustments layer is positioned at the semiconductor substrate surface of open bottom, the formation technique of described threshold voltage adjustments layer is: adopt selective epitaxial depositing operation to form silicon layer at the semiconductor substrate surface of described open bottom; Adopt ion implantation technology or in-situ doped technique doped with II I-V family ion in described silicon layer.
Optionally, in the time that described threshold voltage adjustments layer is positioned at the Semiconductor substrate of open bottom, the formation technique of described threshold voltage adjustments layer is: adopt ion implantation technology doped with II I-V family ion in the Semiconductor substrate of described open bottom.
Optionally, the technique of removing described separator is back etching technics, and in the time returning described in etching separator, making described separator form the first side wall at the semiconductor substrate surface of described barrier layer and channel layer both sides, described the first side coping is lower than channel layer surface.
Optionally, also comprise: before forming grid structure, form the second side wall in the sidewall surfaces of described opening.
Optionally, the material of described the second side wall is different from the material of separator, and the formation technique of described the second side wall is: sidewall and lower surface at described insulation surface and opening deposit the second side wall layer; Etching is removed the second side wall layer of insulation surface and open bottom.
Optionally, after described etching technics, adopt process of surface treatment to make the smooth surface of channel layer, the gas of described process of surface treatment is hydrogen or argon gas, technological parameter is: gas flow 0.1 standard liter/min～5 standard liter/min, treatment temperature is 100 degrees Celsius～600 degrees Celsius, and the processing time is 10 minutes～60 minutes.
Optionally, described grid structure comprises gate dielectric layer and is positioned at the grid layer on described gate dielectric layer surface.
Optionally, the material of described gate dielectric layer is silica, and the material of described grid layer is polysilicon; Or the material of described gate dielectric layer is high K dielectric material, the material of described grid layer is metal.
Optionally, before removing separator, form protective layer on described grid structure surface, the material of described protective layer is different from the material of separator.
Optionally, also comprise: the doped layer surface in described grid structure both sides forms the 3rd side wall.
Optionally, the material of described doped layer is silicon, SiGe or carborundum, has p-type ion or N-shaped ion in described doped layer, and the formation technique of described doped layer is selective epitaxial depositing operation.
Optionally, the concentration of described p-type ion or N-shaped ion raises gradually from semiconductor substrate surface to doped layer surface, and the concentration range of described p-type ion or N-shaped ion is 1e18～1e21/ cubic centimetre.
Optionally, the material of described separator is silicon nitride or silica, and the orientation index of described semiconductor substrate surface is <110> or <100>.
Accordingly, the present invention also provides and adopts the transistor that above-mentioned any one method forms, and comprising: Semiconductor substrate; Be positioned at the threshold voltage adjustments layer of described semiconductor substrate surface, in described threshold voltage adjustments layer, there is doping ion; Be positioned at the barrier layer on described threshold voltage adjustments layer surface, described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer; Be positioned at the channel layer of described barrier layer surface; Be positioned at the grid structure on described channel layer surface; The doped layer that is located at the semiconductor substrate surface of described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides, the surface of described doped layer is not less than channel layer surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
Open bottom between separator forms threshold voltage adjustments layer, forms barrier layer, and form channel layer at described barrier layer surface on described threshold voltage adjustments layer surface.Wherein, described channel layer is eigenstate, has the doping ion for adjusting threshold voltage in threshold voltage adjustments layer; Because barrier layer is between channel layer and threshold voltage adjustments layer, can stop the doping ion penetration in threshold voltage adjustments layer, therefore the barrier layer ion that can prevent from adulterating enters in the channel layer of eigenstate, avoid in channel layer because doping ion produces random doping disturbance effect, make transistorized threshold voltage stablize, reduce and easily control, make transistorized power-dissipation-reduced, device performance improves; And because channel layer is eigenstate, therefore the carrier mobility in channel layer improves, transistor performance strengthens.In addition, described threshold voltage adjustments layer, channel layer and grid structure are formed in the opening between separator, the size of described opening can accurately be controlled by photoetching and etching technics, and the transistorized characteristic size that therefore formed is easily control accurately, makes transistorized performance more stable.
Further, adopt back etching technics to remove separator, and make separator form the first side wall at the semiconductor substrate surface of barrier layer and channel layer both sides, described the first side coping is lower than channel layer surface.Described the first side wall can isolation threshold voltage regulating course and doped layer; Because described doped layer is used for as transistorized source region and drain region, therefore in described doped layer, there is p-type or N-shaped ion, described the first side wall can be avoided the Ion Phase counterdiffusion in ion and the doped layer in threshold voltage adjustments layer and produce leakage current, and then the performance of stable transistor.
Further, the doped layer that is positioned at the semiconductor substrate surface of the first side wall and grid structure both sides forms by selective epitaxial depositing operation, therefore can be by controlling the reacting gas passing in deposition process, ion in doped layer is raise gradually from semiconductor substrate surface to doped layer surface, and the ion concentration of adulterating is easily accurately controlled by technique.And the doping ion concentration that is positioned at described doped layer inner bottom part is low, the ability that diffusion occurs is little, and transistor performance is stable.In addition, described doped layer forms by selective epitaxial depositing operation, therefore can make to produce lattice mismatch between formed doped layer and channel layer, and then make described doped layer provide stress to channel layer, to improve the carrier mobility of channel layer, transistorized performance further improves.
In transistor arrangement, between threshold voltage adjustments layer and channel layer, there is barrier layer, described channel layer is eigenstate, in threshold voltage adjustments layer, there is the doping ion for adjusting threshold voltage, described barrier layer can prevent that the doping ion in threshold voltage adjustments layer from entering in channel layer, transistorized threshold voltage is stablized and easily controlled transistorized power-dissipation-reduced; And described channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.
Brief description of the drawings
Fig. 1 is the transistor cross-sectional view in prior art channel region with doping ion;
Fig. 2 to Fig. 7 is the cross-sectional view of the transistorized forming process described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, although transistor feature size constantly reduce, transistorized threshold voltage V
tbut cannot correspondingly reduce, cause transistor dissipation excessive.
Study discovery through the present inventor, along with transistorized feature size downsizing, the size of transistorized channel region is corresponding reducing also, causes the doping ion in channel region more responsive for the impact of threshold voltage.Concrete, the doping ion in channel region can produce random doping disturbance (RDF, RandomDopant Fluctuations) effect, and described random doping disturbance effect can produce threshold voltage deviations V
t, and threshold voltage deviations V
tvalue increase along with reducing of channel region size.Described threshold voltage deviations V
tcan make the cut-in voltage difference of different crystal pipe, in order to ensure transistorized normal work, put on transistorized operating voltage and need to be greater than described threshold voltage and threshold voltage deviations V
tsummation, easily cause operating voltage too high, transistor dissipation is excessive.And, although adulterate ion in channel region time, can adjusting threshold voltage, prevent leakage current generating, in the time that the doping ion concentration in channel region is too high, can the migration of limiting carrier in channel region, affect transistorized performance.
The above-mentioned adverse effect of bringing for fear of the ion that adulterates in channel region, make transistorized threshold voltage controlled simultaneously, in one embodiment, in Semiconductor substrate, make the channel region that contacts gate dielectric layer be eigenstate, and the ion that adulterates below the channel region of described eigenstate, to form threshold voltage adjustments region.Because described channel region is eigenstate, therefore can not produce random doping disturbance effect, suppress threshold voltage deviations V
tgeneration, thereby can reduce threshold voltage, reduce device power consumption.And the channel region of eigenstate can not hinder the migration of charge carrier, the electric current in channel region increases, transistorized better performances.
But because the threshold voltage adjustments district that is positioned at below, channel region has doping ion, described doping ion very easily diffuses in the channel region of eigenstate, still can cause that transistorized threshold voltage is unstable, causes transistorized unstable properties.
Further study through the present inventor, after forming threshold voltage adjustments layer, form barrier layer on described threshold voltage adjustments layer surface, and form channel layer at described barrier layer surface.Wherein, described channel layer is eigenstate, has the doping ion for adjusting threshold voltage in threshold voltage adjustments layer; The doping ion penetration in threshold voltage adjustments layer, between channel layer and threshold voltage adjustments layer, can be avoided in barrier layer, prevents that described doping ion from entering in the channel layer of eigenstate.Therefore, can not produce random doping disturbance effect in channel layer, transistorized threshold voltage is stable, power-dissipation-reduced, and device performance improves; And the carrier mobility in channel layer can improve, strengthen transistorized performance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 2 to Fig. 7 is the cross-sectional view of the transistorized forming process described in the embodiment of the present invention.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces have some separators 201, between adjacent separator 201, form opening 202; Form threshold voltage adjustments layer 203 in described opening 202 bottoms, in described threshold voltage adjustments layer 203, there is doping ion.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided; Described Semiconductor substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates or silicon-on-insulator (SOI) substrate.The orientation index on described Semiconductor substrate 200 surfaces is <110> or <100>.
The material of described separator 201 is insulating material, comprises silicon nitride or silica, and in the present embodiment, the material of described separator 201 is silicon nitride; The formation technique of described separator 201 is: at Semiconductor substrate 200 surface deposition isolated films; Etched portions isolated film is until expose Semiconductor substrate 200, formation separator 201; Opening 202 between adjacent separator 201 has defined position and the shape of the grid structure of follow-up formation, because position and the size of described opening 202 can accurately be controlled by photoetching and etching technics, therefore can make the follow-up characteristic size that is formed at grid structure in described opening 202 and channel layer more accurate, make transistorized performance more stable.
And, when the described separator 201 of follow-up removal, can adopt back etching technics, make the separator 201 after etching form side wall in the threshold voltage adjustments layer both sides of follow-up formation, described side wall can be isolated the doped layer of described threshold voltage adjustments layer and follow-up formation, described doped layer is used for as transistorized source region and drain region, therefore, described side wall can be avoided the Ion Phase counterdiffusion in threshold voltage adjustments layer and doped layer and affect device performance.
Described threshold voltage adjustments layer 203, for controlling transistorized threshold voltage, makes formed transistor threshold voltage meet design requirement; The material of described threshold voltage adjustments layer 203 is semi-conducting material, comprises silicon or germanium; In described semi-conducting material, have doping ion, described doping ion comprises one or more combinations in carbon, germanium, tin and III-V family ion; By adjusting the doping ion concentration in semi-conducting material, can accurately control transistorized threshold voltage.
In one embodiment, described threshold voltage adjustments layer 203 is formed at Semiconductor substrate 202 surfaces of opening 202 bottoms; The formation technique of described threshold voltage adjustments layer 203 is: adopt selective epitaxial depositing operation to form semiconductor layer on Semiconductor substrate 200 surfaces of described opening 202 bottoms; In described selective epitaxial depositing operation, adopt the in-situ doped technique ion that adulterates in described semiconductor layer, form threshold voltage adjustments layer 203; The semiconductor layer thickness that adopts selective epitaxial depositing operation to form is accurate, and the accurately easily control of ion concentration that adopts in-situ doped technique to adulterate, and makes transistorized performance more stable; Or, after described selective epitaxial depositing operation, adopt the ion implantation technology ion that adulterates in described semiconductor layer, form threshold voltage adjustments layer 203.
In another embodiment, adopt ion implantation technology, directly at the interior doped with II I-V of Semiconductor substrate 200 of described opening 202 bottoms family ion, form threshold voltage adjustments layer 203.In the present embodiment, without adopting selective epitaxial deposition to form semiconductor layer, can simplify technique, save cost.
Please refer to Fig. 3, form barrier layer 204 and be positioned at the channel layer 205 on 204 surfaces, described barrier layer on described threshold voltage adjustments layer 203 surface, described channel layer 205 is eigenstate, and described barrier layer 204 is for stoping the doping ion penetration in threshold voltage adjustments layer 203.
The material on described barrier layer 204 is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material be monocrystal material, and the formation technique on described barrier layer 204 is selective epitaxial depositing operation; Because described barrier layer 204 is the monocrystal material of SiGe, carborundum or Germanium carbon, in SiGe, carborundum or the silicon Germanium carbon material of monocrystalline, a little less than the diffusivity of doping ion, therefore described barrier layer 204 can stop the interior diffusion of channel layer 205 to follow-up formation of doping ion in threshold voltage adjustments layer 203, and then can ensure eigenstate or the low-doped state of described channel layer 205, avoid the interior generation random doping of channel layer 205 disturbance effect, threshold voltage is reduced, improve transistorized performance.
The material of described channel layer 205 is silicon or the germanium of eigenstate, and the formation technique of described channel layer 205 is selective epitaxial depositing operation, and the thickness of described channel layer 205 is 5 nanometer～20 nanometers; In one embodiment, the doping ion of low concentration can also adulterate in described channel layer 205, described doping ion is one or both in germanium and carbon, the mol ratio of described doping ion and silicon atom is 0.01～0.5, and described doping ion is doped in channel layer 205 by in-situ doped technique or ion implantation technology.
Described channel layer 205 is used to form transistorized channel region; Because described channel layer 205 is eigenstate, or there is the doping ion of low concentration, therefore described channel layer 205 is difficult to occur random doping disturbance effect, can not make threshold voltage produce deviation, then without raising threshold voltage value in order to ensure transistorized normal unlatching, formed transistorized operating voltage is reduced, and then make transistorized Energy Intensity Reduction, improve the performance of the semiconductor device forming.
Secondly, because described channel layer 205 is eigenstate, or there is the doping ion of low concentration, therefore when the transistor that formed is worked, the carrier mobility in channel region can not be hindered, and the carrier mobility in channel region improves, transistorized operating current improves, and transistorized performance strengthens.
And, owing to thering is barrier layer 204 between threshold voltage adjustments layer 203 and described channel layer 205, described barrier layer 204 can prevent that doping ion in threshold voltage adjustments layer 203 is to the interior diffusion of channel layer 205, the eigenstate or the low-doped state that have ensured described channel layer 205, make formed transistorized stable performance.
Please refer to Fig. 4, after forming described channel layer 205, form the second side wall 206 in the sidewall surfaces of described opening 202; After forming described the second side wall 206, adopt process of surface treatment to make the smooth surface of channel layer 205.
The material of described the second side wall 206 is different with the material of separator 201, and in the time of follow-up removal separator 201, described the second side wall 206 can be protected the grid structure of follow-up formation; In the present embodiment, the material of described the second side wall 206 is silica.Described the second side wall 206 is for when the follow-up removal separator 201, protects the sidewall surfaces of grid structure of follow-up formation injury-free, and the appearance and size that ensures described grid structure with this is accurate.
The formation technique of described the second side wall 206 is: sidewall and lower surface at described separator 201 surfaces and described opening 202 deposit the second side wall layer; Adopt the second side wall layer described in anisotropic dry etch process etching, until expose channel layer 205 and separator 201 surfaces of opening 202 bottoms.
But, because described anisotropic dry etch process can cause damage to the surface of described channel layer 205, and when described channel layer 205 surfaces sustain damage, easily produce leakage current, affect the stability of transistor performance, therefore need to after described anisotropic dry etch process, carry out process of surface treatment, so that described channel layer 205 smooth surfaces; The gas of described process of surface treatment is hydrogen or argon gas, and technological parameter is: gas flow 0.1 standard liter/min～5 standard liter/min, and treatment temperature is 100 degrees Celsius～600 degrees Celsius, the processing time is 10 minutes～60 minutes.
Please refer to Fig. 5, after described process of surface treatment, form grid structure (not shown), the surface of described grid structure and separator 201 flush on described channel layer 205 surfaces; Form protective layer 209 on described grid structure surface, the material of described protective layer 209 is different from the material of separator 201.
In the present embodiment, described grid structure comprises: be positioned at the gate dielectric layer 207 on channel layer 205 surfaces, and be positioned at the grid layer 208 on described gate dielectric layer 207 surfaces; The material of described gate dielectric layer 207 is silica or high K dielectric material; In the time that the material of described gate dielectric layer 207 is silica, the material of described grid layer 208 is polysilicon; In the time that the material of described gate dielectric layer 207 is high K dielectric material, for example hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide, the material of described grid layer 208 is metal, for example copper, tungsten, aluminium or silver, the transistor forming is high-K metal gate (HKMG, High-K Metal Gate) transistor.In the present embodiment, the material of described gate dielectric layer 207 is silica, and the material of described grid layer 208 is polysilicon.
The formation technique of described gate dielectric layer 207 and grid layer 208 is: at the surface of described separator 201 and the sidewall of described opening 202 and lower surface deposition gate dielectric membrane; At described gate dielectric layer film surface deposition grid film, until fill full described opening 202(with reference to figure 4); Adopt glossing, preferably CMP (Chemical Mechanical Polishing) process is removed gate dielectric membrane and the grid film higher than separator 201 surfaces, and exposes separator 201.
After forming described grid structure; form protective layer 209 on described grid structure surface; the material of described protective layer 209 is different from the material of separator 201; make the described protective layer 209 can be in the technique of follow-up removal separator 201; protect described grid structure surface injury-free, accurately complete to ensure the pattern of grid structure.In the present embodiment; the material of described protective layer 209 is silica, and because the material of the grid layer 208 in the present embodiment is polysilicon, therefore described protective layer 209 can material thermal oxidation technology form; and without adopting deposition and etching technics, it is simple that it forms technique.
Please refer to Fig. 6, return described in etching separator 201(as shown in Figure 5), make described separator 201 form the first side wall 201a on Semiconductor substrate 200 surfaces of described barrier layer 204 and channel layer 205 both sides, the top of described the first side wall 201a is lower than channel layer 205 surfaces.
In the present embodiment, the technique of removing separator 201 is anisotropic dry etch process, can be at etching separator 201 until after exposing Semiconductor substrate 200, make the separator 201 being etched form the first side wall 201a on barrier layer 204 and channel layer 205 both sides; Described the first side wall 201a is for mutually isolating barrier layer 204 and channel layer 205 and the doped layer of follow-up formation; Because described doped layer is used for as transistorized source region or drain region, therefore in described doped layer, there is p-type or N-shaped ion, described the first side wall 201a can prevent ion in doped layer to barrier layer 204 or the interior diffusion of channel layer 205, thereby suppress the generation of leakage current, make transistorized performance more stable.
And the top of described the first side wall 201a is lower than the surface of channel layer 205, the doped layer of follow-up formation can contact with channel layer; Because described doped layer is used for as transistorized source region or drain region, therefore can be in the transistorized channel region of the interior formation of described channel layer 205.
Please refer to Fig. 7, form doped layer 210 on Semiconductor substrate 200 surfaces of described the first side wall 201a and grid structure both sides, the surface of described doped layer 210 is not less than channel layer 205 surfaces; Doped layer 210 surfaces in described grid structure both sides form the 3rd side wall 211.
Described doped layer 210 is for as transistorized source region or drain region; The formation technique of described doped layer 210 is selective epitaxial depositing operation; The material of described doped layer 210 is silicon, SiGe or carborundum, and especially, in the time that the material of described doped layer 210 is SiGe or carborundum, described doped layer 210 can provide stress to channel layer 205; In the time that the transistor of required formation is PMOS transistor, the material of described doped layer 210 is SiGe, can provide compression to channel layer 205, to improve the carrier mobility of channel region, improves transistorized performance; And in the time that the transistor of required formation is nmos pass transistor, the material of described doped layer 210 is carborundum, can provide tension stress to channel layer 205.
Because described doped layer 210 is for as transistorized source region or drain region, interior doped p type ion or the N-shaped ion of needing of described doped layer 210; Wherein, described doping ion can be after selective epitaxial depositing operation forms doped layer 210, adopts ion implantation technology to adulterate in described doped layer 210; In addition, described doping ion can be in described selective epitaxial deposition process, adopts in-situ doped technique to be doped in doped layer 210; And, in the time adopting in-situ doped technique, can accurately control the concentration of described doping ion, described doping ion is raise to doped layer 210 surfaces gradually from Semiconductor substrate 200 surfaces; The concentration range of described p-type or N-shaped doping ion is 1e18～1e21/ cubic centimetre.In the doped layer 210 near Semiconductor substrate 200 surfaces, the concentration of doping ion is lower, therefore having suppressed doping ion spreads towards periphery, reduce the diffusion of doping ion to threshold voltage adjustments layer 203 or barrier layer 204, thereby reduce the generation of leakage current, make formed transistorized function admirable.
The material of described the 3rd side wall 211 is one or both combinations in silica and silicon nitride, forms technique and is: at doped layer 210, the second side wall 206 and grid structure surface deposition the 3rd side wall layer; Adopt the 3rd side wall layer described in anisotropic dry etch process etching, until expose doped layer 210 and grid structure surface.Described the 3rd side wall 211 is at subsequent technique grill-protected electrode structure.
In the present embodiment, between threshold voltage adjustments layer and channel layer, form barrier layer, the described barrier layer ion that can prevent from adulterating enters in the channel layer of eigenstate, avoid in channel layer because doping ion produces random doping disturbance effect, reduce transistorized threshold voltage deviation, thereby reduction threshold voltage, reduces transistorized power consumption, improve transistor performance.Secondly, because channel layer can keep eigenstate or low-doped state, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.At this, described threshold voltage adjustments layer, channel layer and grid structure are formed in the opening between separator, the size of described opening can accurately be controlled by photoetching and etching technics, and the transistorized characteristic size that therefore formed is easily control accurately, makes transistorized performance more stable.In addition, also have the first side wall between doped layer and barrier layer, described the first side wall can avoid the ion in doped layer to spread in barrier layer, reduces the generation of leakage current, and transistorized performance is more stable.
Accordingly, the present embodiment also provides a kind of transistorized structure, please continue to refer to Fig. 7, comprising: Semiconductor substrate 200; Be positioned at the threshold voltage adjustments layer 203 on described Semiconductor substrate 200 surfaces, in described threshold voltage adjustments layer 203, there is doping ion; Be positioned at the barrier layer 204 on described threshold voltage adjustments layer 203 surface, described barrier layer 204 is for stoping the doping ion penetration in threshold voltage adjustments layer 203; Be positioned at the channel layer 205 on 204 surfaces, described barrier layer; Be positioned at the grid structure on described channel layer 205 surfaces; The doped layer 210 that is located at Semiconductor substrate 200 surfaces of described threshold voltage adjustments layer 203, barrier layer 204, channel layer 205 and grid structure both sides, the surface of described doped layer 210 is not less than channel layer 205 surfaces; The first side wall 201a on Semiconductor substrate 200 surfaces between threshold voltage adjustments layer 203 and doped layer 210, the top of described the first side wall 201a is lower than channel layer 205 surfaces; Be positioned at the 3rd side wall 211 on doped layer 210 surfaces of described grid structure both sides.
The material on described barrier layer 204 is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material.The material of described channel layer 205 is silicon, and thickness is 5 nanometer～20 nanometers; In one embodiment, described channel layer 205 is eigenstate; In another embodiment, in described channel layer 205, have doping ion, described doping ion is one or both in germanium and carbon, and the concentration range of described doping ion is 1e18～1e21/ cubic centimetre.The material of described threshold voltage adjustments layer 203 is silicon, and in described silicon materials, doped with one or more combinations in carbon, germanium, tin and III-V family ion, described threshold voltage adjustments layer 203 is positioned at Semiconductor substrate 200 surfaces or Semiconductor substrate.The material of described the first side wall 201a is silicon nitride or silica.The orientation index on described Semiconductor substrate 200 surfaces is <110> or <100>.
Described grid structure comprises gate dielectric layer 207 and is positioned at the grid layer 208 on described gate dielectric layer 207 surfaces; The material of described gate dielectric layer 207 is silica, and the material of described grid layer 208 is polysilicon; Or the material of described gate dielectric layer 207 is high K dielectric material, the material of described grid layer 208 is metal.
The material of described doped layer 210 is silicon, SiGe or carborundum, has p-type ion or N-shaped ion in described doped layer 210; The concentration of described p-type ion or N-shaped ion raises to doped layer 210 surfaces gradually from Semiconductor substrate 200 surfaces, and the concentration range of described p-type ion or N-shaped ion is 1e18～1e21/ cubic centimetre.
In the present embodiment, Semiconductor substrate 200 surfaces of described barrier layer 204 and channel layer 205 both sides have the first side wall 201a, and the top of described the first side wall 201a is lower than channel layer 205 surfaces.The sidewall surfaces of described grid structure has the second side wall 206; The material of described the second side wall 206 is different from the material of the first side wall 201a.Described grid structure surface has protective layer 209, and the material of described protective layer 209 is different from the material of the first side wall 201a.Doped layer 210 surfaces of described grid structure both sides have the 3rd side wall 211.
In the transistor of the present embodiment, between threshold voltage adjustments layer and channel layer, have barrier layer, described barrier layer can prevent that the doping ion in threshold voltage adjustments layer from entering in channel layer, makes transistorized threshold voltage stable, transistorized power-dissipation-reduced; And described channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.
In sum, the open bottom between separator forms threshold voltage adjustments layer, forms barrier layer, and form channel layer at described barrier layer surface on described threshold voltage adjustments layer surface.Wherein, described channel layer is eigenstate, has the doping ion for adjusting threshold voltage in threshold voltage adjustments layer; Because barrier layer is between channel layer and threshold voltage adjustments layer, and for stopping the doping ion penetration in threshold voltage adjustments layer, therefore the barrier layer ion that can prevent from adulterating enters in the channel layer of eigenstate, avoid in channel layer because doping ion produces random doping disturbance effect, make transistorized threshold voltage stablize, reduce and easily control, make transistorized power-dissipation-reduced, device performance improves; And because channel layer is eigenstate, therefore the carrier mobility in channel layer improves, transistor performance strengthens.In addition, described threshold voltage adjustments layer, channel layer and grid structure are formed in the opening between separator, the size of described opening can accurately be controlled by photoetching and etching technics, and the transistorized characteristic size that therefore formed is easily control accurately, makes transistorized performance more stable.
Further, adopt back etching technics to remove separator, and make separator form the first side wall at the semiconductor substrate surface of barrier layer and channel layer both sides, described the first side coping is lower than channel layer surface.Described the first side wall can isolation threshold voltage regulating course and doped layer; Because described doped layer is used for as transistorized source region and drain region, therefore in described doped layer, there is p-type or N-shaped ion, described the first side wall can be avoided the Ion Phase counterdiffusion in ion and the doped layer in threshold voltage adjustments layer and produce leakage current, and then the performance of stable transistor.
Further, the doped layer that is positioned at the semiconductor substrate surface of the first side wall and grid structure both sides forms by selective epitaxial depositing operation, therefore can be by controlling the reacting gas passing in deposition process, ion in doped layer is raise gradually from semiconductor substrate surface to doped layer surface, and the ion concentration of adulterating is easily accurately controlled by technique.Ion concentration in described doped layer raises to top gradually from bottom, can suppress the generation of leakage current, makes transistor performance stable.In addition, described doped layer forms by selective epitaxial depositing operation, therefore can make to produce lattice mismatch between formed doped layer and channel layer, and then make described doped layer provide stress to channel layer, to improve the carrier mobility of channel layer, transistorized performance further improves.
In transistor arrangement, between threshold voltage adjustments layer and channel layer, there is barrier layer, described channel layer is eigenstate, in threshold voltage adjustments layer, there is the doping ion for adjusting threshold voltage, described barrier layer can prevent that the doping ion in threshold voltage adjustments layer from entering in channel layer, transistorized threshold voltage is stablized and easily controlled transistorized power-dissipation-reduced; And described channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a transistorized formation method, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has some separators, between adjacent separator, forms opening, and described open bottom has threshold voltage adjustments layer, in described threshold voltage adjustments layer, has doping ion;
Form barrier layer and be positioned at the channel layer of described barrier layer surface on described threshold voltage adjustments layer surface, described channel layer is eigenstate, and described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer;
Form grid structure on described channel layer surface, the surface of described grid structure flushes with insulation surface;
Remove described separator until expose Semiconductor substrate;
After removing described separator, form doped layer at the semiconductor substrate surface of described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides, the surface of described doped layer is not less than channel layer surface.
2. transistorized formation method as claimed in claim 1, is characterized in that, the material on described barrier layer is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material.
3. transistorized formation method as claimed in claim 1, is characterized in that, the formation technique on described barrier layer is selective epitaxial depositing operation.
4. transistorized formation method as claimed in claim 1, is characterized in that, the material of described channel layer is silicon, and the formation technique of described channel layer is selective epitaxial depositing operation, and the thickness of described channel layer is 5 nanometer～20 nanometers.
5. transistorized formation method as claimed in claim 4, it is characterized in that, also comprise: ion adulterates in described channel layer, described doping ion is one or both in germanium and carbon, the mol ratio of described doping ion and silicon atom is 0.01～0.5, and described doping ion is doped in channel layer by in-situ doped technique.
6. transistorized formation method as claimed in claim 1, it is characterized in that, the material of described threshold voltage adjustments layer is silicon, in described silicon materials, doped with one or more combinations in carbon, germanium, tin and III-V family ion, described threshold voltage adjustments layer is formed in the semiconductor substrate surface of described open bottom or the Semiconductor substrate of open bottom.
7. transistorized formation method as claimed in claim 6, it is characterized in that, in the time that described threshold voltage adjustments layer is positioned at the semiconductor substrate surface of open bottom, the formation technique of described threshold voltage adjustments layer is: adopt selective epitaxial depositing operation to form silicon layer at the semiconductor substrate surface of described open bottom; Adopt ion implantation technology or in-situ doped technique doped with II I-V family ion in described silicon layer.
8. transistorized formation method as claimed in claim 6, it is characterized in that, in the time that described threshold voltage adjustments layer is positioned at the Semiconductor substrate of open bottom, the formation technique of described threshold voltage adjustments layer is: adopt ion implantation technology doped with II I-V family ion in the Semiconductor substrate of described open bottom.
9. transistorized formation method as claimed in claim 1, it is characterized in that, the technique of removing described separator is back etching technics, and in the time returning described in etching separator, make described separator form the first side wall at the semiconductor substrate surface of described barrier layer and channel layer both sides, described the first side coping is lower than channel layer surface.
10. transistorized formation method as claimed in claim 1, is characterized in that, also comprises: before forming grid structure, form the second side wall in the sidewall surfaces of described opening.
11. transistorized formation methods as claimed in claim 10, it is characterized in that, the material of described the second side wall is different from the material of separator, and the formation technique of described the second side wall is: sidewall and lower surface at described insulation surface and opening deposit the second side wall layer; Etching is removed the second side wall layer of insulation surface and open bottom.
12. transistorized formation methods as claimed in claim 11, it is characterized in that, after described etching technics, adopt process of surface treatment to make the smooth surface of channel layer, the gas of described process of surface treatment is hydrogen or argon gas, technological parameter is: gas flow 0.1 standard liter/min～5 standard liter/min, and treatment temperature is 100 degrees Celsius～600 degrees Celsius, the processing time is 10 minutes～60 minutes.
13. transistorized formation methods as claimed in claim 1, is characterized in that, described grid structure comprises gate dielectric layer and is positioned at the grid layer on described gate dielectric layer surface.
14. transistorized formation methods as claimed in claim 13, is characterized in that, the material of described gate dielectric layer is silica, and the material of described grid layer is polysilicon; Or the material of described gate dielectric layer is high K dielectric material, the material of described grid layer is metal.
15. transistorized formation methods as claimed in claim 1, is characterized in that, before removing separator, form protective layer on described grid structure surface, and the material of described protective layer is different from the material of separator.
16. transistorized formation methods as claimed in claim 1, is characterized in that, also comprise: the doped layer surface in described grid structure both sides forms the 3rd side wall.
17. transistorized formation methods as claimed in claim 1, is characterized in that, the material of described doped layer is silicon, SiGe or carborundum, has p-type ion or N-shaped ion in described doped layer, and the formation technique of described doped layer is selective epitaxial depositing operation.
18. transistorized formation methods as claimed in claim 17, it is characterized in that, the concentration of described p-type ion or N-shaped ion raises gradually from semiconductor substrate surface to doped layer surface, and the concentration range of described p-type ion or N-shaped ion is 1e18～1e21/ cubic centimetre.
19. transistorized formation methods as claimed in claim 1, it is characterized in that, the material of described separator is silicon nitride or silica, and the orientation index of described semiconductor substrate surface is <110> or <100>.
20. 1 kinds of employings as the transistor that claim 1 to 19 any one method is formed, is characterized in that, comprising: Semiconductor substrate; Be positioned at the threshold voltage adjustments layer of described semiconductor substrate surface, in described threshold voltage adjustments layer, there is doping ion; Be positioned at the barrier layer on described threshold voltage adjustments layer surface, described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer; Be positioned at the channel layer of described barrier layer surface; Be positioned at the grid structure on described channel layer surface; The doped layer that is positioned at the semiconductor substrate surface of described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides, the surface of described doped layer is not less than channel layer surface.
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