CN101826464A - Forming method of MOS (Metal Oxide Semiconductor) transistor and threshold voltage regulating method thereof - Google Patents
Forming method of MOS (Metal Oxide Semiconductor) transistor and threshold voltage regulating method thereof Download PDFInfo
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- CN101826464A CN101826464A CN200910046886A CN200910046886A CN101826464A CN 101826464 A CN101826464 A CN 101826464A CN 200910046886 A CN200910046886 A CN 200910046886A CN 200910046886 A CN200910046886 A CN 200910046886A CN 101826464 A CN101826464 A CN 101826464A
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Abstract
The invention discloses a forming method of an MOS (Metal Oxide Semiconductor) transistor and a threshold voltage regulating method thereof. The forming method of the MOS transistor comprises the following steps of: directly carrying out ion implantation on a semiconductor substrate to form an ion diffusion region used for regulating the threshold voltage; forming a grid structure on the semiconductor substrate; carrying out ion implantation at both sides of the grid structure in the semiconductor substrate so as to form a bag-shaped implantation region, a source extension region, a drain extension region, a source electrode and a drain electrode; and annealing the semiconductor substrate, wherein the energy and the dosage of implanted ions for forming the ion diffusion region are determined according to the threshold voltage of the MOS transistor. In the method, an extra photomask is not needed to be added for independently carrying out the parallel regulation of the threshold voltage of devices in different sizes, thereby simple and flexible regulation of the threshold voltage is realized, the process period of the manufacture procedure is shortened and the cost is saved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, refer to a kind of formation method and threshold voltage adjustment method thereof of MOS transistor especially.
Background technology
At present, because the integrated level of integrated circuit is more and more higher, size of devices is more and more littler, and the characteristic size of device (CD) is developed from the zone of 0.13 μ m below 0.10 μ m.Along with semiconductor device develops to high density and small size, metal monooxide semiconductor (MOS) device is main actuating force.Threshold voltage (Vt) and drive current (Id) are two important electrical quantitys of MOS transistor, also are the important control parameters in manufacturing process.Different core circuit (Core) with fail/go into/output circuit (IO) has different Vt and Id performance requirement.
In the prior art, doping shape, the bag shape by control gate oxide layer, channel region, well area, source/drain extension region injected the performance requirement that (pocket implant) distinguishes and source/drain electrode injection shape and heat budget or the like obtain to expect usually.Modal is to change ion to inject type, energy and dosage, and change gate oxide thickness dual mode, but which kind of method no matter, all need to utilize light shield, like this, can use different light shields and define different device areas, make the transistorized manufacture craft of whole M OS become complicated more.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of formation method of MOS transistor, can regulate threshold voltage simply, neatly.
Another object of the present invention is to provide a kind of threshold voltage adjustment method of MOS transistor, can realize that threshold voltage regulates simply, flexibly.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of formation method of MOS transistor comprises:
On Semiconductor substrate, directly carry out ion and inject, be formed for regulating the ion diffusion region of threshold voltage;
On Semiconductor substrate, form grid structure;
In grid structure both sides, Semiconductor substrate, carry out ion and inject with shape pouch injection region, source and drain extension region, and source and drain electrode, Semiconductor substrate is annealed.
Described formation method also comprises:
Before forming described ion diffusion region, in Semiconductor substrate, form isolation structure;
Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
Described MOS transistor is a nmos pass transistor, and the polysilicon chip thickness in the described grid structure is 75nm～120nm, forms described ion diffusion region and the ion that injects is a P type ion, and its energy range is 50KeV～200KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
Described second ion is the boron ion.
Described MOS transistor is the PMOS transistor, polysilicon chip thickness range in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a N type ion, and its energy range is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
Described second ion is a phosphonium ion.
Between the degree of depth circle Yu Yuan/drain extension region and source/drain electrode of described bag shape injection region, the conduction type of described bag shape injection region and the conductivity type opposite of source/drain extension region or source/drain electrode.
Before formation source/drain electrode step, also be included in and form the side wall step on grid structure both sides, the Semiconductor substrate.
A kind of threshold voltage adjustment method of MOS transistor, this method comprises:
Before forming grid structure on the Semiconductor substrate, do not cover in Semiconductor substrate and to carry out ion under the photoresistance state and inject, be formed for regulating the ion diffusion region of threshold voltage;
In grid structure both sides, Semiconductor substrate, carry out ion and inject, Semiconductor substrate is annealed with shape pouch injection region, source/drain extension region and source/drain electrode;
The energy of ions and the dosage that form described ion diffusion region and inject are determined according to the threshold voltage of MOS transistor.
Also comprise:
Before forming described ion diffusion region, in Semiconductor substrate, form isolation structure;
Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
Described MOS transistor is a nmos pass transistor, and the polysilicon chip thickness in the described grid structure is 75nm～120nm, forms described ion diffusion region and the ion that injects is a P type ion, and its energy range is 50KeV～200KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
Described second ion is the boron ion.
Described MOS transistor is the PMOS transistor, polysilicon chip thickness range in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a N type ion, and its energy range is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
Described second ion is a phosphonium ion.
As seen from the above technical solution, the present invention did not cover in Semiconductor substrate and to carry out ion under the photoresistance state and inject before forming grid structure on the Semiconductor substrate, was formed for regulating the ion diffusion region of threshold voltage; In grid structure both sides, Semiconductor substrate, carry out ion and inject, Semiconductor substrate is annealed with shape pouch injection region, source/drain extension region and source/drain electrode.The energy of ions and the dosage that form described ion diffusion region and inject are determined according to the threshold voltage of MOS transistor.The inventive method does not need to increase extra light shield can increase adjusting to the MOS transistor threshold voltage, to such an extent as to and can ignore the influence of other device is very little.Shortened the making technology cycle, provided cost savings.
Further, before forming described ion diffusion region, in Semiconductor substrate, form isolation structure; Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
Description of drawings
Fig. 1 a～Fig. 1 f is that the present invention is the schematic diagram of formation method of the MOS transistor of embodiment with the nmos pass transistor.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Using the step that the inventive method forms MOS transistor comprises: before forming grid structure on the Semiconductor substrate, do not cover in Semiconductor substrate and to carry out ion under the photoresistance state and inject, be formed for regulating the ion diffusion region of threshold voltage; In grid structure both sides, Semiconductor substrate, carry out ion and inject, Semiconductor substrate is annealed with shape pouch injection region, source/drain extension region and source/drain electrode.When MOS transistor was PMOS, second ion of injection was a N type ion, as phosphonium ion, arsenic ion etc.; When MOS transistor was NMOS, second ion of injection was P type ion, as boron ion etc.The injection degree of depth (energy) and the dosage of the ion that forms ion diffusion region and inject have determined the thickness and the concentration of ion diffusion region, and the threshold voltage of regulating with needs has relation, is promptly determined by the threshold voltage of MOS transistor.
Also be included in before the described ion diffusion region of formation, in Semiconductor substrate, form isolation structure; Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
The inventive method does not need to increase extra light shield can increase adjusting to certain classification device threshold voltage, to such an extent as to and can ignore the influence of other device is very little.
Forming process with nmos pass transistor is an example below, in conjunction with Fig. 1 a～Fig. 1 f, for embodiment the inventive method is described in detail.
With reference to accompanying drawing 1a, Semiconductor substrate 100 is provided, Semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI).Form isolation structure 101 in Semiconductor substrate, isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In Semiconductor substrate 100, also be formed with the gate channel layer of various traps (well) structure and substrate surface.In general, the ion doping conduction type that forms trap (well) structure is identical with gate channel layer ion doping conduction type, but concentration is low than gate channel layer, and the depth bounds that ion injects is wider, need reach the degree of depth greater than isolation structure 101 simultaneously.In order to simplify, blank Semiconductor substrate 100 diagrams only are shown among Fig. 1 a～Fig. 1 f.
Then, carry out ion and inject, be formed for regulating the ion diffusion region of threshold voltage.The injection degree of depth (energy) and the dosage of the ion that forms ion diffusion region and inject have determined the thickness and the concentration of ion diffusion region, and the threshold voltage of regulating with needs has relation, is promptly determined by the threshold voltage of MOS transistor.
Here emphasize be the present invention in the forming process of nmos pass transistor, before forming grid structure on the Semiconductor substrate, increase the technology that the ion that forms ion diffusion region injects, with simply, regulate threshold voltage neatly.The ion that injects is a P type ion, as the boron ion etc.The injection energy of ion and dosage and the threshold voltage that needs to regulate have relation.
As an embodiment of the invention, the injection boron energy of ions that forms ion diffusion region 107 is 50KeV～200KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2Polysilicon chip thickness in the described grid structure is 75nm～120nm.
In the transistorized forming process of PMOS, the ion of injection is a N type ion.As an embodiment of the invention, the energy that forms the injection phosphonium ion of ion diffusion region 107 is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2Polysilicon chip thickness range in the described grid structure is 75nm～120nm.
How to determine that according to injecting energy and dosage the threshold voltage of MOS transistor belongs to those skilled in the art's conventional techniques means, repeats no more here.What the present invention emphasized is, before forming grid structure on the Semiconductor substrate, do not cover the technology that increases the ion injection that forms ion diffusion region under the photoresistance state in Semiconductor substrate, dosage and energy that the ion that injects forming described ion diffusion region injects carry out appropriate choosing, realized device to different size carry out effective threshold voltage adjustments promptly almost parallel adjusting different size certain device threshold voltage and hardly other device is exerted an influence, thereby flexibility, shortened the making technology cycle, provided cost savings.
With reference to accompanying drawing 1b, on Semiconductor substrate 100, form gate dielectric layer 102 and polysilicon gate 103 successively, gate dielectric layer 102 constitutes grid structure with polysilicon gate 103.Then, carry out oxidation step, form silicon oxide layers 104 so that the edge of protection polysilicon gate 103 in polysilicon gate 104 peripheries.
With reference to accompanying drawing 1c, in the grid structure both sides that form, Semiconductor substrate 100, to carry out ion and inject i.e. bag shape injection (Pocket implant) 110, bag shape is injected the 110 general angles that adopt and is injected between 0 to 45 ion of spending, and forms bag shape injection region 105.Degree of depth circle of bag shape injection region 105 is between follow-up source/drain extension region to be formed and source/drain electrode, and its conduction type and the follow-up source/drain extension region to be formed or the conductivity type opposite of source/drain electrode are the P type.
With reference to accompanying drawing 1d, in grid structure both sides, Semiconductor substrate 100, carry out ion and inject 111, formation source/drain extension region 106.The present technique field that forms personnel's known technology of source/drain extension region 106 no longer describes in detail here.The conduction type of source/drain extension region 106 is the N type, i.e. the ions that first ion injection 111 is injected are phosphorus (P) ion or arsenic (As) ion.
With reference to accompanying drawing 1e, on grid structure both sides, Semiconductor substrate 100, form side wall 108, side wall 108 can for a kind of in silica, silicon nitride, the silicon oxynitride or they constitute.Optimize execution mode for one as present embodiment, described side wall 108 is formed jointly for silica, silicon nitride, concrete technology is roughly: forming first silicon oxide layer, first silicon nitride layer and second silicon oxide layer on the Semiconductor substrate 100 and on the silicon oxide layer 104, adopting etching (etch-back) method to form side wall then.
With reference to accompanying drawing 1f, in grid structure both sides, Semiconductor substrate 100, carry out source/drain electrode and inject formation source/drain electrode 109.Described source/drain electrode 109 is the N type, i.e. the ion that source/drain electrode is injected is phosphorus (P) ion or arsenic (As) ion.
At last, Semiconductor substrate 100 is annealed, make the various ions diffusion of injection even.
Behind above-mentioned process implementing, as Fig. 1 f, the nmos pass transistor of formation comprises: be positioned at the grid structure on the Semiconductor substrate 100; Be arranged in the source/drain extension region 106 and the source/drain electrode 109 of grid structure both sides, Semiconductor substrate 100; Also comprise being positioned at the grid structure below, form grid structure and inject the ion diffusion region 107 that forms by ion before.
Among the present invention, the formation of ion diffusion region 107 can also form before isolation structure.
The inventive method is equally applicable to the PMOS transistor, as long as form before the grid structure, does not cover in Semiconductor substrate and to carry out ion under the photoresistance state and inject, and the ion diffusion region that is formed for regulating threshold voltage gets final product.For the PMOS transistor, the ion of the formation ion diffusion region of injection is a N type ion, as phosphonium ion, arsenic ion etc.The energy range that ion injects is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2Polysilicon chip thickness range in the described grid structure is 75nm～120nm.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1. the formation method of a MOS transistor is characterized in that, comprising:
On Semiconductor substrate, directly carry out ion and inject, be formed for regulating the ion diffusion region of threshold voltage;
On Semiconductor substrate, form grid structure;
In grid structure both sides, Semiconductor substrate, carry out ion and inject with shape pouch injection region, source and drain extension region, and source and drain electrode, Semiconductor substrate is annealed.
2. formation method according to claim 1 is characterized in that, described formation method also comprises:
Before forming described ion diffusion region, in Semiconductor substrate, form isolation structure;
Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
3. formation method according to claim 1 and 2, it is characterized in that, described MOS transistor is a nmos pass transistor, polysilicon chip thickness in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a P type ion, its energy range is 50KeV～200KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
4. formation method according to claim 3 is characterized in that, described second ion is the boron ion.
5. formation method according to claim 1 and 2, it is characterized in that, described MOS transistor is the PMOS transistor, polysilicon chip thickness range in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a N type ion, its energy range is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
6. formation method according to claim 5 is characterized in that, described second ion is a phosphonium ion.
7. formation method according to claim 1 is characterized in that, between the degree of depth circle Yu Yuan/drain extension region and source/drain electrode of described bag shape injection region, and the conduction type of described bag shape injection region and the conductivity type opposite of source/drain extension region or source/drain electrode.
8. formation method according to claim 1 is characterized in that, before formation source/drain electrode step, also is included in and forms the side wall step on grid structure both sides, the Semiconductor substrate.
9. the threshold voltage adjustment method of a MOS transistor is characterized in that, this method comprises:
Before forming grid structure on the Semiconductor substrate, do not cover in Semiconductor substrate and to carry out ion under the photoresistance state and inject, be formed for regulating the ion diffusion region of threshold voltage;
In grid structure both sides, Semiconductor substrate, carry out ion and inject, Semiconductor substrate is annealed with shape pouch injection region, source/drain extension region and source/drain electrode;
The energy of ions and the dosage that form described ion diffusion region and inject are determined according to the threshold voltage of MOS transistor.
10. threshold voltage adjustment method according to claim 9 is characterized in that, also comprises:
Before forming described ion diffusion region, in Semiconductor substrate, form isolation structure;
Perhaps, after forming described ion diffusion region, form before the grid structure, in Semiconductor substrate, form isolation structure.
11. according to claim 9 or 10 described formation methods, it is characterized in that, described MOS transistor is a nmos pass transistor, polysilicon chip thickness in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a P type ion, its energy range is 50KeV～200KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
12. formation method according to claim 11 is characterized in that, described second ion is the boron ion.
13. according to claim 9 or 10 described formation methods, it is characterized in that, described MOS transistor is the PMOS transistor, polysilicon chip thickness range in the described grid structure is 75nm～120nm, the ion that forms described ion diffusion region and inject is a N type ion, its energy range is 100KeV～400KeV, and the dosage range of injection is 3e11cm
-2～2e12cm
-2
14. formation method according to claim 13 is characterized in that, described second ion is a phosphonium ion.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332405A (en) * | 2011-09-30 | 2012-01-25 | 上海宏力半导体制造有限公司 | Intrinsic device fabrication process |
| CN104064463A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
-
2009
- 2009-03-02 CN CN200910046886A patent/CN101826464A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332405A (en) * | 2011-09-30 | 2012-01-25 | 上海宏力半导体制造有限公司 | Intrinsic device fabrication process |
| CN104064463A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
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Open date: 20100908 |