CN104425383B - The preparation method of semiconductor devices - Google Patents
The preparation method of semiconductor devices Download PDFInfo
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- CN104425383B CN104425383B CN201310407943.1A CN201310407943A CN104425383B CN 104425383 B CN104425383 B CN 104425383B CN 201310407943 A CN201310407943 A CN 201310407943A CN 104425383 B CN104425383 B CN 104425383B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
Present invention is disclosed a kind of preparation method of semiconductor devices, including：Front-end devices structure is provided, the front-end devices structure includes Semiconductor substrate and the grid structure in the Semiconductor substrate, and the side wall of the grid structure is formed with the first side wall；Recess process is carried out to the Semiconductor substrate, groove is formed with the exposed region of the Semiconductor substrate of the first side wall both sides；Carry out shallow doping process；The second side wall is formed in the side wall of the grid structure；Carry out source drain doping technique；Remove second side wall；Stress liner layer is formed on the surface on the surface of the Semiconductor substrate, the surface of the grid structure and first side wall.In the preparation method of semiconductor devices of the invention, due to the presence of the groove so that the stress liner that subsequently forms layer closer to channel region, to improve stress migration effect, so as to effectively improve raceway groove carriers transport efficiency.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of preparation method of semiconductor devices.
Background technology
At present, the principal element of influence field-effect transistor performance is the mobility of carrier, and wherein carrier is moved
Shifting rate can influence the size of electric current in raceway groove.The decline of carrier mobility can not only reduce transistor in field-effect transistor
Switch speed, but also can reduce resistance difference during on and off.Therefore, it is brilliant in CMOSFET
In the development of body pipe (CMOS), effectively improve carrier mobility and always be one of emphasis of transistor arrangement design.
Conventional, in cmos device manufacturing technology, by P-type mos field-effect transistor (PMOS) and N
Type metal oxide semiconductor field-effect transistor (NMOS) is separately processed, for example, being used in the manufacture method of PMOS device
Compression material, and tensile stress material is used in the manufacture method of nmos device, apply appropriate stress with to channel region, from
And improve the mobility of carrier.
In the prior art, stress liner layer is formed generally around the surface of Semiconductor substrate and grid structure
(stress liner), stress is applied with to raceway groove.On the other hand, in order that stress liner layer is closer to channel region, so as to right
Channel region applies appropriate stress, while increase interlayer dielectric lamellar spacing filling window, can generally form source/drain region
Afterwards, positioned at the side wall construction of grid structure both sides, this is referred to as stress close to technology (being also called SPT technologies) for removal.
However, in the SPT technologies of prior art, stress liner layer is formed in the top of channel region, and and channel region
Domain it is distant, therefore stress liner layer can be influenceed to the migration effect of channel region, and then can not effectively improve raceway groove
Carriers mobility.So, how a kind of preparation method is provided, can solve the problem that the problems of the prior art, it has also become ability
One of technical problem of domain urgent need to resolve.
The content of the invention
It is an object of the present invention to provide a kind of preparation method of semiconductor devices, can effectively improve raceway groove and contain
Stream transport factor, so as to improve the electrical property of semiconductor devices.
In order to solve the above technical problems, a kind of preparation method of semiconductor devices, including：
Front-end devices structure is provided, the front-end devices structure includes Semiconductor substrate and in the Semiconductor substrate
Grid structure, the side wall of the grid structure is formed with the first side wall；
Recess process is carried out to the Semiconductor substrate, with the sudden and violent of the Semiconductor substrate of the first side wall both sides
Dew region forms groove；
Shallow doping process is carried out, shallow doped region is formed with the Semiconductor substrate of the grid structure both sides；
The second side wall is formed in the side wall of the grid structure；
Carry out source drain doping technique, with the Semiconductor substrate of the second side wall both sides formed source electrode and
Drain electrode；
Second side wall is removed, to expose the surface of first side wall；And
Formed on the surface on the surface of the Semiconductor substrate, the surface of the grid structure and first side wall
Stress liner layer.
Further, shallow doping process step and side second side of wall formation in first side wall are carried out described
Between wall step, also include：
The 3rd side wall is formed in the side wall of the grid structure；
Cavity technique is carried out, cavity is formed with the Semiconductor substrate of the 3rd side wall both sides；
Stressed semiconductor alloy-layer is formed in the cavity.
Further, in the step of the removal second side wall, also include：Remove the 3rd side wall.
Further, it is described to include the step of carry out cavity technique：The 3rd side wall both sides are removed using dry etching
The Semiconductor substrate, wherein, the etching gas of the dry etching are included in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen
One or more combination.
Further, it is described to include the step of carry out cavity technique：The 3rd side wall both sides are removed using wet etching
The Semiconductor substrate, wherein, the etching liquid of the wet etching is tetramethyl aqua ammonia.
Further, the grid structure is metal gate structure.
Further, the material of the stressed semiconductor alloy-layer is sige alloy.
Further, shallow doping process step and side second side of wall formation in first side wall are carried out described
Between wall step, also include：
The 4th side wall is formed in the side wall of the grid structure；
Cavity technique is carried out, cavity is formed with the Semiconductor substrate of the 4th side wall both sides；
Stressed semiconductor alloy-layer is formed in the cavity；
The 4th side wall is removed, to expose the surface of first side wall.
Further, thickness of the thickness of the 4th side wall less than second side wall.
Further, it is described to include the step of carry out cavity technique：The 4th side wall both sides are removed using dry etching
The Semiconductor substrate, wherein, the etching gas of the dry etching are included in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen
One or more combination.
Further, it is described to include the step of carry out cavity technique：The 4th side wall both sides are removed using wet etching
The Semiconductor substrate, wherein, the etching liquid of the wet etching is tetramethyl aqua ammonia.
Further, the grid structure is polysilicon gate construction.
Further, the material of the stressed semiconductor alloy-layer is sige alloy.
Further, it is described carry out source drain doping technique the step of and the step of the removal second side wall
Between, also include：Carry out self-registered technology.
Further, the depth of the groove is
Further, it is described to include the step of carry out recess process to the Semiconductor substrate：Removed using dry etching
The first side wall both sides have the Semiconductor substrate of certain depth, with the semiconductor of the first side wall both sides
The exposed region of substrate forms the groove.
Further, the thickness of first side wall is
Further, the thickness of second side wall is
Compared with prior art, the preparation method of the semiconductor devices that the present invention is provided has advantages below：Described half
In the preparation method of conductor device, before shallow doping process is carried out, recess process is carried out to the Semiconductor substrate, with institute
The exposed region for stating the Semiconductor substrate of the first side wall both sides forms groove, compared with prior art, due to the groove
Presence so that subsequently form stress liner layer closer to channel region, to improve stress migration effect, so as to effectively change
Kind raceway groove carriers transport efficiency.
Brief description of the drawings
Fig. 1 is the flow chart of the preparation method of semiconductor devices in one embodiment of the invention；
Fig. 2-Figure 12 is the schematic diagram of device architecture in the preparation method of semiconductor devices in one embodiment of the invention；
Figure 13-Figure 16 is the schematic diagram of device architecture in the preparation method of semiconductor devices in another embodiment of the present invention.
Specific embodiment
The preparation method of semiconductor devices of the invention is described in more detail below in conjunction with schematic diagram, wherein table
Show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize advantageous effects of the invention.Therefore, description below be appreciated that it is widely known for those skilled in the art, and
It is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, is only used to conveniently, lucidly aid in illustrating the purpose of the embodiment of the present invention.
Core concept of the invention is, there is provided a kind of preparation method of semiconductor devices, including：
Step S11, there is provided front-end devices structure, the front-end devices structure includes Semiconductor substrate and is partly led positioned at described
Grid structure on body substrate, the side wall of the grid structure is formed with the first side wall；
Step S12, recess process is carried out to the Semiconductor substrate, with the semiconductor of the first side wall both sides
The exposed region of substrate forms groove；
Step S13, carries out shallow doping process, and shallow mixing is formed with the Semiconductor substrate of the grid structure both sides
Miscellaneous area；
Step S14, the second side wall is formed in the side wall of the grid structure；
Step S15, carries out source drain doping technique, with the shape in the Semiconductor substrate of the second side wall both sides
Into source electrode and drain electrode；
Step S16, removes second side wall, to expose the surface of first side wall；And
Step S17, in the table on the surface of the Semiconductor substrate, the surface of the grid structure and first side wall
Stress liner layer is formed on face.
Before shallow doping process is carried out, recess process is carried out to the Semiconductor substrate, with first side wall two
The exposed region of the Semiconductor substrate of side forms groove, due to the presence of the groove so that the stress lining for subsequently forming
Bed course closer to channel region, to improve stress migration effect, thus effectively improve raceway groove carriers transport efficiency.
Several embodiments of the preparation method of the semiconductor devices are exemplified below, with clear explanation present disclosure,
It will be clear that present disclosure is not restricted to following examples, other are normal by those of ordinary skill in the art's
The improvement of rule technological means is also within thought range of the invention.
【First embodiment】
Incorporated by reference to Fig. 1 and Fig. 2-Figure 12, the preparation method of semiconductor devices of the invention is illustrated.Wherein, Fig. 1 is
The flow chart of the preparation method of semiconductor devices in one embodiment of the invention, Fig. 2-Figure 12 is semiconductor in one embodiment of the invention
The schematic diagram of device architecture in the preparation method of device.
First, as shown in figure 1, carrying out step S11, there is provided front-end devices structure, the front-end devices structure includes partly leading
Body substrate 100 and the grid structure in the Semiconductor substrate 100 110, the side wall of the grid structure 110 are formed with
One side wall 120, as shown in Figure 2.Wherein, the thickness of first side wall 120 isSuch as described first side wall
120 thickness isDeng can be very good to protect the grid structure 110, but first side wall
120 thickness be not limited to forThe material of first side wall 120 can be silicon nitride, silica or nitrogen oxygen
The combination of one or more of SiClx, is not limited specifically.
The Semiconductor substrate 100 can be using monocrystalline silicon, the monocrystalline silicon doped with impurity, the silicon-on-insulator of undoped p
(SOI) or SiGe (SiGe) etc., in the present embodiment, the Semiconductor substrate 100 is made up of single crystal silicon material.The substrate
100 also including isolated area etc. necessary device, this is the common knowledge of this area, and therefore not to repeat here.
Preferably, the grid structure 110 can include the gate dielectric layer 111, the and of gate material layers 112 that stack gradually
Grid hard mask layer 113, as shown in Figure 2.In the present embodiment, the grid structure 110 is metal gate structure, i.e., described grid
The material of pole material layer 112 is metal, then the material of the gate dielectric layer 111 is the oxide of high dielectric, the grid
The material of hard mask layer 113 is nitrogen oxides etc..But the grid structure 110 is not limited to the gate dielectric layer for stacking gradually
111st, gate material layers 112 and grid hard mask layer 113, the grid structure 110 can also be Semiconductor Oxide-nitridation
Thing-Oxidc-Semiconductor (SONOS) layer stacked gate structure.
Then, step S12 is carried out, recess process is carried out to the Semiconductor substrate 100, with first side wall 120
The exposed region 101 of the Semiconductor substrate 100 of both sides is (not by the grid structure 110 in i.e. described Semiconductor substrate 100
The region covered with first side wall 120) groove 102 is formed, as shown in Figure 3.Wherein, the depth of the groove 120 isThe thickness of such as described groove 120 isDeng can be very good so that subsequent shape
Into stress liner layer closer to device channel region, but first side wall thickness be not limited to for
In the present embodiment, the step S12 removes the both sides of the first side wall 120 using dry etching has a depthkeeping
The Semiconductor substrate 100 of degree, with the exposed region shape of the Semiconductor substrate 100 of the both sides of the first side wall 120
Into the groove 120, the certain depth is the depth of the groove 120.The gas of the dry etching can be lithium
Sulphur, carbon tetrafluoride etc. can etch the gas of monocrystalline silicon, not be limited specifically.
Then, step S13 is carried out, shallow doping process is carried out, is served as a contrast with the semiconductor of the both sides of the grid structure 110
Shallow doped region 103 is formed in bottom 100, as shown in Figure 4.
Preferably, between step S13 and step S14, also including preparing embedded stressed semiconductor alloy-layer the step of,
To improve the stress of channel region, step is specifically included in the present embodiment, the step of prepare embedded stressed semiconductor alloy-layer
Rapid S101~step S103：
Carry out step S101：The 3rd side wall 130 is formed in the side wall of the grid structure 110, due to the grid structure
110 side wall is also formed with the first side wall 120, so, the 3rd side wall 130 is located at the outside of first side wall 120, such as schemes
Shown in 5.The material of the 3rd side wall 130 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, tool
Body is not limited.；
Carry out step S102：Cavity technique is carried out, with the Semiconductor substrate 100 of the both sides of the 3rd side wall 130
Middle formation cavity 104, the cavity 104 adjacent to the side of shallow doped region 103 edge by the of the Semiconductor substrate 100
One crystallographic direction (110) and the second crystallographic direction (111) are defined.Because the Semiconductor substrate 100 is silicon substrate, so, institute
Cavity 104 is stated adjacent to the edge of the side of shallow doped region 103 in diamond-shaped (Diamond-shaped), i.e., described cavity
104 is in " ∑ " shape adjacent to the edge of the side of shallow doped region 103, as shown in Figure 6.Preferably, dry etching can be used
Or wet etching removes the Semiconductor substrate 100 of the both sides of the 3rd side wall 130, wherein, the etching of the dry etching
Gas includes chlorine, hydrogen bromide, carbon tetrafluoride and one or more combination in oxygen；The etching liquid of the wet etching is tetramethyl
Base aqua ammonia；
Carry out step S103：Stressed semiconductor alloy-layer 105 is formed in the cavity 104, as shown in Figure 7.Wherein, may be used
Stressed semiconductor alloy-layer 105 is formed in the cavity 104 with using epitaxy technique, due to the present embodiment in, it is described partly to lead
The material of body substrate 100 is monocrystalline silicon, so the material of the stressed semiconductor alloy-layer 105 is sige alloy, can be fine
Raising channel region stress.
Then, step S14 is carried out, the second side wall 140 is formed in the side wall of the grid structure 100, due to the grid
The side wall of structure 110 is also formed with the first side wall 120 and the 3rd side wall 130, so, the 3rd side wall 130 is located at described the
The outside of three side wall 130, as shown in Figure 8.The thickness of second side wall 140 isSuch as described second side wall
140 thickness isDeng, but first side wall thickness be not limited to forInstitute
The material for stating the second side wall 140 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, not limit specifically
System.
Then, step S15 is carried out, source drain doping technique is carried out, with described the half of the both sides of the second side wall 140
Source electrode 106 and drain electrode 107 are formed in conductor substrate 100, as shown in Figure 9.
Wherein, in the present embodiment, between step S15 and step S16, also including carrying out self-registered technology, to be formed
Self-aligned silicide 108, as shown in Figure 10.
Then, step S16 is carried out, second side wall 140 is removed, in the present embodiment, due to first side wall 120
Outer wall also there is the 3rd side wall 130, so, while removal the 3rd side wall 130, to expose first side wall
120 surface, as shown in figure 11.
Finally, carry out step S15, the surface of the Semiconductor substrate 100, the surface of the grid structure 110 and
Stress liner layer 109 is formed on the surface of first side wall 120, as shown in figure 12.Due to the presence of the groove 102, make
The stress liner layer 109 is obtained closer to channel region 10, stress migration effect can be improved, so as to effectively improve in raceway groove
Charge carrier transport efficiency.
【Second embodiment】
Incorporated by reference to Figure 13-Figure 16, Figure 13-Figure 16 is device in the preparation method of semiconductor devices in another embodiment of the present invention
The schematic diagram of part structure, in Figure 13-Figure 16, reference number is represented and the statement of Fig. 2-Figure 12 identicals and first embodiment phase
Same part.The preparation of the preparation method of semiconductor devices and semiconductor devices in an embodiment in another embodiment
Method is essentially identical, and its difference is：The grid structure 110 is polysilicon gate construction, i.e., described gate material layers 112
Material is polysilicon, then the material of the gate dielectric layer 111 is silica, and the material of the grid hard mask layer 113 is
Nitrogen oxides etc..
Preferably, in inventing the preparation method of semiconductor devices in another embodiment, between step S13 and step S14,
Also include the step of preparing embedded stressed semiconductor alloy-layer, to improve the stress of channel region, in the present embodiment, prepare
The step of embedded stressed semiconductor alloy-layer, specifically includes step S201~step S204：
Step S201 is carried out, the 4th side wall 230 is formed in the side wall of the grid structure 110, as shown in figure 13.Described
The material of four side walls 230 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, not be limited specifically；
Step S202 is carried out, cavity technique is carried out, with the Semiconductor substrate 100 of the both sides of the 4th side wall 230
Middle formation cavity 104, as shown in figure 13.Preferably, the 4th side wall 230 can be removed using dry etching or wet etching
The Semiconductor substrate 100 of both sides, wherein, the etching gas of the dry etching include chlorine, hydrogen bromide, carbon tetrafluoride and
One or more combination in oxygen；The etching liquid of the wet etching is tetramethyl aqua ammonia；
Step S203 is carried out, stressed semiconductor alloy-layer 105 is formed in the cavity 104, as shown in figure 14.Wherein,
Stressed semiconductor alloy-layer 105 can be formed in the cavity 104 using epitaxy technique, due to the present embodiment in, described half
The material of conductor substrate 100 is monocrystalline silicon, so the material of the stressed semiconductor alloy-layer 105 is sige alloy, can be very
The stress of good raising channel region.
Step S204 is carried out, the 4th side wall 230 is removed, to expose the surface of first side wall 120, such as Figure 15 institutes
Show.
Then, step S14 is carried out, the second side wall 240 is formed in the side wall of the grid structure 100, due to the grid
The side wall of structure 110 is also formed with the first side wall 120, so, the 3rd side wall 130 is located at the outside of the first side wall 120, such as schemes
Shown in 16.The thickness of second side wall is more than the thickness of the 4th side wall, preferably, the thickness of second side wall 140
ForThe thickness of such as described second side wall 140 isDeng, but first side
The thickness of wall be not limited to for
In the present embodiment, can also realize before shallow doping process is carried out, groove is carried out to the Semiconductor substrate
Technique, so as to the first side wall both sides the Semiconductor substrate exposed region formed groove, can also realize so that
The stress liner layer for subsequently forming can also improve stress migration effect, so that effectively closer to the beneficial effect of channel region
Ground improves raceway groove carriers transport efficiency.
Obviously, those skilled in the art can carry out various changes and modification without deviating from essence of the invention to the present invention
God and scope.So, if these modifications of the invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (18)
1. a kind of preparation method of semiconductor devices, including：
Front-end devices structure is provided, the front-end devices structure includes Semiconductor substrate and the grid in the Semiconductor substrate
Pole structure, the side wall of the grid structure is formed with the first side wall；
Recess process is carried out to the Semiconductor substrate, with the exposed region of the Semiconductor substrate of the first side wall both sides
Domain forms groove；
Shallow doping process is carried out, shallow doped region is formed with the Semiconductor substrate of the grid structure both sides；
The second side wall is formed in the side wall of the grid structure；
Source drain doping technique is carried out, to form source electrode and drain electrode in the Semiconductor substrate of the second side wall both sides；
Second side wall is removed, to expose the surface of first side wall, and exposes the groove of the first side wall both sides；With
And
Stress is formed on the surface on the surface of the Semiconductor substrate, the surface of the grid structure and first side wall
Laying, the groove of the stress liner layer filling the first side wall both sides.
2. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that carry out shallow doping process step described
It is rapid and described between the side wall of first side wall forms the second side wall step, also include：
The 3rd side wall is formed in the side wall of the grid structure；
Cavity technique is carried out, cavity is formed with the Semiconductor substrate of the 3rd side wall both sides；
Stressed semiconductor alloy-layer is formed in the cavity.
3. the preparation method of semiconductor devices as claimed in claim 2, it is characterised in that in removal second side wall
The step of in, also include：Remove the 3rd side wall.
4. the preparation method of semiconductor devices as claimed in claim 2, it is characterised in that described the step of carry out cavity technique
Including：The Semiconductor substrate of the 3rd side wall both sides is removed using dry etching, wherein, the etching of the dry etching
Gas includes chlorine, hydrogen bromide, carbon tetrafluoride and one or more combination in oxygen.
5. the preparation method of semiconductor devices as claimed in claim 2, it is characterised in that described the step of carry out cavity technique
Including：The Semiconductor substrate of the 3rd side wall both sides is removed using wet etching, wherein, the etching of the wet etching
Liquid is tetramethyl aqua ammonia.
6. the preparation method of semiconductor devices as claimed in claim 2, it is characterised in that the grid structure is metal gates
Structure.
7. the preparation method of semiconductor devices as claimed in claim 2, it is characterised in that the stressed semiconductor alloy-layer
Material is sige alloy.
8. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that carry out shallow doping process step described
It is rapid and described between the side wall of first side wall forms the second side wall step, also include：
The 4th side wall is formed in the side wall of the grid structure；
Cavity technique is carried out, cavity is formed with the Semiconductor substrate of the 4th side wall both sides；
Stressed semiconductor alloy-layer is formed in the cavity；
The 4th side wall is removed, to expose the surface of first side wall.
9. the preparation method of semiconductor devices as claimed in claim 8, it is characterised in that the thickness of the 4th side wall is less than
The thickness of second side wall.
10. the preparation method of semiconductor devices as claimed in claim 8, it is characterised in that the step for carrying out cavity technique
Suddenly include：The Semiconductor substrate of the 4th side wall both sides is removed using dry etching, wherein, the quarter of the dry etching
Erosion gas includes chlorine, hydrogen bromide, carbon tetrafluoride and one or more combination in oxygen.
The preparation method of 11. semiconductor devices as claimed in claim 8, it is characterised in that the step for carrying out cavity technique
Suddenly include：The Semiconductor substrate of the 4th side wall both sides is removed using wet etching, wherein, the quarter of the wet etching
Erosion liquid is tetramethyl aqua ammonia.
The preparation method of 12. semiconductor devices as claimed in claim 8, it is characterised in that the grid structure is polysilicon
Grid structure.
The preparation method of 13. semiconductor devices as claimed in claim 8, it is characterised in that the stressed semiconductor alloy-layer
Material be sige alloy.
The preparation method of 14. semiconductor devices as described in any one in claim 1-13, it is characterised in that it is described enter
Between the step of the step of row source drain doping technique and the removal second side wall, also include：Carry out autoregistration work
Skill.
The preparation method of 15. semiconductor devices as claimed in claim 1, it is characterised in that the depth of the groove is
The preparation method of 16. semiconductor devices as claimed in claim 1, it is characterised in that carried out to the Semiconductor substrate
The step of recess process, includes：The semiconductor that removing the first side wall both sides using dry etching has certain depth is served as a contrast
Bottom, the groove is formed with the exposed region in the Semiconductor substrate of the first side wall both sides.
The preparation method of 17. semiconductor devices as claimed in claim 1, it is characterised in that the thickness of first side wall is
The preparation method of 18. semiconductor devices as claimed in claim 1, it is characterised in that the thickness of second side wall is
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| CN102110652A (en) * | 2009-12-24 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing embedded type semiconductor devices |
| CN102184895A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
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