CN104425383A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
- Publication number
- CN104425383A CN104425383A CN201310407943.1A CN201310407943A CN104425383A CN 104425383 A CN104425383 A CN 104425383A CN 201310407943 A CN201310407943 A CN 201310407943A CN 104425383 A CN104425383 A CN 104425383A
- Authority
- CN
- China
- Prior art keywords
- side wall
- semiconductor substrate
- preparation
- semiconductor device
- sides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a preparation method of a semiconductor device. The preparation method comprises the following steps: providing a front-end device structure, wherein the front-end device structure comprises a semiconductor substrate and gate structures arranged on the semiconductor substrate, and first spacers are formed on the spacers of the gate structures; grooving the semiconductor substrate to form grooves in exposed areas, at the two sides of the first spacers, of the semiconductor substrate; carrying out shallow doping; forming second spacers on the spacers of the gate structures; carrying out source/drain doping; removing the second spacers; forming stress cushion layers on the surface of the semiconductor substrate, the surfaces of the gate structures and the surfaces of the first spacers. In the preparation method of the semiconductor device, due to existence of the grooves, the stress cushion layers formed subsequently are closer to channel areas to improve the stress migration effects, thus effectively improving the migration efficiency of carriers in channels.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of preparation method of semiconductor device.
Background technology
At present, the principal element affecting field-effect transistor performance is the mobility of charge carrier, and wherein the mobility of charge carrier can affect the size of electric current in raceway groove.In field-effect transistor, the decline of carrier mobility not only can reduce the switch speed of transistor, but also resistance difference when holding and close can be made to reduce.Therefore, in the development of complementary metal oxide semiconductor field effect transistor (CMOS), effectively improve carrier mobility and always be one of emphasis that transistor arrangement designs.
Conventional, in cmos device manufacturing technology, by P-type mos field-effect transistor (PMOS) and N-type mos field effect transistor (NMOS) separately process, such as, compression material is adopted in the manufacture method of PMOS device, and in the manufacture method of nmos device, adopt tensile stress material, to apply suitable stress to channel region, thus improve the mobility of charge carrier.
In the prior art, usually around the surface and grid structure of Semiconductor substrate, form stress liner layer (stress liner), with to raceway groove stress application.On the other hand, in order to make stress liner layer closer to channel region, to apply suitable stress to channel region, and increase interlayer dielectric layer gap-fill window simultaneously, usually understanding after formation source/drain region, remove the side wall construction being positioned at grid structure both sides, this is called as stress close to technology (being also called SPT technology).
But, in the SPT technology of prior art, stress liner layer is formed in the top of channel region, and distant with channel region, therefore can affect the migration effect of stress liner layer to channel region, and then effectively can not improve raceway groove carriers mobility.So, how a kind of preparation method is provided, can the problems of the prior art be solved, become one of this area technical problem needing solution badly.
Summary of the invention
The object of the invention is to, a kind of preparation method of semiconductor device is provided, effectively can improve raceway groove carriers mobility, thus improve the electrical property of semiconductor device.
For solving the problems of the technologies described above, a kind of preparation method of semiconductor device, comprising:
There is provided front-end devices structure, described front-end devices structure comprises Semiconductor substrate and is positioned at the grid structure in described Semiconductor substrate, and the sidewall of described grid structure is formed with the first side wall;
Recess process is carried out to described Semiconductor substrate, forms groove with the exposed region of the described Semiconductor substrate in described first side wall both sides;
Carry out shallow doping process, to form shallow doped region in the described Semiconductor substrate of described grid structure both sides;
The second side wall is formed at the sidewall of described grid structure;
Carry out source/drain doping process, to form source electrode and drain electrode in the described Semiconductor substrate of described second side wall both sides;
Remove described second side wall, to expose the surface of described first side wall; And
The surface of the surface of the surface of described Semiconductor substrate, described grid structure and described first side wall forms stress liner layer.
Further, carry out shallow doping process step and the described sidewall at described first side wall is formed between the second side wall step described, also comprise:
The 3rd side wall is formed at the sidewall of described grid structure;
Carry out cavity technique, to form cavity in the described Semiconductor substrate of described 3rd side wall both sides;
Stressed semiconductor alloy-layer is formed in described cavity.
Further, in the step of described second side wall of described removal, also comprise: remove described 3rd side wall.
Further, described step of carrying out cavity technique comprises: adopt dry etching to remove the described Semiconductor substrate of described 3rd side wall both sides, wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen.
Further, the step of carrying out cavity technique described in comprises: adopt wet etching to remove the described Semiconductor substrate of described 3rd side wall both sides, wherein, the etching liquid of described wet etching is tetramethyl aqua ammonia.
Further, described grid structure is metal gate structure.
Further, the material of described stressed semiconductor alloy-layer is sige alloy.
Further, carry out shallow doping process step and the described sidewall at described first side wall is formed between the second side wall step described, also comprise:
The 4th side wall is formed at the sidewall of described grid structure;
Carry out cavity technique, to form cavity in the described Semiconductor substrate of described 4th side wall both sides;
Stressed semiconductor alloy-layer is formed in described cavity;
Remove described 4th side wall, to expose the surface of described first side wall.
Further, the thickness of described 4th side wall is less than the thickness of described second side wall.
Further, described step of carrying out cavity technique comprises: adopt dry etching to remove the described Semiconductor substrate of described 4th side wall both sides, wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen.
Further, the step of carrying out cavity technique described in comprises: adopt wet etching to remove the described Semiconductor substrate of described 4th side wall both sides, wherein, the etching liquid of described wet etching is tetramethyl aqua ammonia.
Further, described grid structure is polysilicon gate construction.
Further, the material of described stressed semiconductor alloy-layer is sige alloy.
Further, also comprise: carry out self-registered technology between the step of source/drain doping process and the step of described second side wall of described removal described carrying out.
Further, the degree of depth of described groove is
Further, described the step that described Semiconductor substrate carries out recess process to be comprised: adopt dry etching to remove described Semiconductor substrate that described first side wall both sides have certain depth, form described groove with the exposed region of the described Semiconductor substrate in described first side wall both sides.
Further, the thickness of described first side wall is
Further, the thickness of described second side wall is
Compared with prior art, the preparation method of semiconductor device provided by the invention has the following advantages: in the preparation method of described semiconductor device, before carrying out shallow doping process, recess process is carried out to described Semiconductor substrate, groove is formed with the exposed region of the described Semiconductor substrate in described first side wall both sides, compared with prior art, due to the existence of described groove, make the stress liner layer formed subsequently closer to channel region, to improve stress migration effect, thus effectively improve raceway groove carriers transport efficiency.
Accompanying drawing explanation
Fig. 1 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention;
Fig. 2-Figure 12 is the schematic diagram of device architecture in the preparation method of semiconductor device in one embodiment of the invention;
Figure 13-Figure 16 is the schematic diagram of device architecture in the preparation method of semiconductor device in another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, the preparation method to semiconductor device of the present invention is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of preparation method of semiconductor device, comprising:
Step S11, provides front-end devices structure, and described front-end devices structure comprises Semiconductor substrate and is positioned at the grid structure in described Semiconductor substrate, and the sidewall of described grid structure is formed with the first side wall;
Step S12, carries out recess process to described Semiconductor substrate, forms groove with the exposed region of the described Semiconductor substrate in described first side wall both sides;
Step S13, carries out shallow doping process, to form shallow doped region in the described Semiconductor substrate of described grid structure both sides;
Step S14, forms the second side wall at the sidewall of described grid structure;
Step S15, carries out source/drain doping process, to form source electrode and drain electrode in the described Semiconductor substrate of described second side wall both sides;
Step S16, removes described second side wall, to expose the surface of described first side wall; And
Step S17, the surface of the surface of the surface of described Semiconductor substrate, described grid structure and described first side wall forms stress liner layer.
Before carrying out shallow doping process, recess process is carried out to described Semiconductor substrate, groove is formed with the exposed region of the described Semiconductor substrate in described first side wall both sides, due to the existence of described groove, make the stress liner layer formed subsequently closer to channel region, to improve stress migration effect, thus effectively improve raceway groove carriers transport efficiency.
Below enumerate several embodiments of the preparation method of described semiconductor device, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by the routine techniques means of those of ordinary skill in the art are also within thought range of the present invention.
[the first embodiment]
Incorporated by reference to Fig. 1 and Fig. 2-Figure 12, illustrate the preparation method of semiconductor device of the present invention.Wherein, Fig. 1 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention, and Fig. 2-Figure 12 is the schematic diagram of device architecture in the preparation method of semiconductor device in one embodiment of the invention.
First, as shown in Figure 1, step S11 is carried out, front-end devices structure is provided, the grid structure 110 that described front-end devices structure comprises Semiconductor substrate 100 and is positioned in described Semiconductor substrate 100, the sidewall of described grid structure 110 is formed with the first side wall 120, as shown in Figure 2.Wherein, the thickness of described first side wall 120 is
such as the thickness of described first side wall 120 is
deng, described grid structure 110 can well be protected, but the thickness of described first side wall 120 be not limited to into
the material of described first side wall 120 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, does not specifically limit.
Described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) or SiGe (SiGe) etc. doped with impurity, and in the present embodiment, described Semiconductor substrate 100 is made up of single crystal silicon material.Described substrate 100 also comprises the necessary devices such as isolated area, and this is the common practise of this area, and therefore not to repeat here.
Preferably, described grid structure 110 can comprise the gate dielectric layer 111, gate material layers 112 and the grid hard mask layer 113 that stack gradually, as shown in Figure 2.In the present embodiment, described grid structure 110 is metal gate structure, and namely the material of described gate material layers 112 is metal, then the material of described gate dielectric layer 111 is the oxide of high dielectric, and the material of described grid hard mask layer 113 is nitrogen oxide etc.But described grid structure 110 is not limited to the gate dielectric layer 111, gate material layers 112 and the grid hard mask layer 113 that stack gradually, described grid structure 110 can also be Semiconductor Oxide-Nitride Oxide-semiconductor (SONOS) layer stacked gate structure.
Then, carry out step S12, recess process is carried out to described Semiconductor substrate 100, groove 102 is formed, as shown in Figure 3 with the exposed region 101 of the described Semiconductor substrate 100 in described first side wall 120 both sides (namely in described Semiconductor substrate 100 not by region that described grid structure 110 and described first side wall 120 cover).Wherein, the degree of depth of described groove 120 is
such as the thickness of described groove 120 is
deng, the stress liner layer that formed subsequently can well be made closer to the channel region of device, but the thickness of described first side wall be not limited to into
In the present embodiment, described step S12 adopts described first side wall 120 both sides of dry etching removal to have the described Semiconductor substrate 100 of certain depth, form described groove 120 with the exposed region of the described Semiconductor substrate 100 in described first side wall 120 both sides, described certain depth is the degree of depth of described groove 120.The gas of described dry etching can be that sulphur hexafluoride, carbon tetrafluoride etc. can the gases of etching single crystal silicon, does not specifically limit.
Then, carry out step S13, carry out shallow doping process, to form shallow doped region 103 in the described Semiconductor substrate 100 of described grid structure 110 both sides, as shown in Figure 4.
Preferably, between step S13 and step S14, also comprise the step preparing embedded stressed semiconductor alloy-layer, to improve the stress of channel region, in the present embodiment, the step preparing embedded stressed semiconductor alloy-layer specifically comprises step S101 ~ step S103:
Carry out step S101: form the 3rd side wall 130 at the sidewall of described grid structure 110, the sidewall due to described grid structure 110 is also formed with the first side wall 120, so described 3rd side wall 130 is positioned at outside described first side wall 120, as shown in Figure 5.The material of described 3rd side wall 130 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, does not specifically limit.；
Carry out step S102: carry out cavity technique, to form cavity 104 in the described Semiconductor substrate 100 of described 3rd side wall 130 both sides, the edge of the contiguous side, described shallow doped region 103 of described cavity 104 is defined by the first crystal direction (110) of described Semiconductor substrate 100 and the second crystallographic direction (111).Because described Semiconductor substrate 100 is silicon substrate, so, the edge of the contiguous side, described shallow doped region 103 of described cavity 104 is diamond-shaped (Diamond-shaped), and namely the edge of the contiguous side, described shallow doped region 103 of described cavity 104 is in " ∑ " shape, as shown in Figure 6.Preferably, dry etching or wet etching can be adopted to remove the described Semiconductor substrate 100 of described 3rd side wall 130 both sides, and wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen; The etching liquid of described wet etching is tetramethyl aqua ammonia;
Carry out step S103: in described cavity 104, form stressed semiconductor alloy-layer 105, as shown in Figure 7.Wherein, epitaxy technique can be adopted in described cavity 104 to form stressed semiconductor alloy-layer 105, due in the present embodiment, the material of described Semiconductor substrate 100 is monocrystalline silicon, so the material of described stressed semiconductor alloy-layer 105 is sige alloy, the stress of channel region can well be improved.
Subsequently, carry out step S14, form the second side wall 140 at the sidewall of described grid structure 100, sidewall due to described grid structure 110 is also formed with the first side wall 120 and the 3rd side wall 130, so described 3rd side wall 130 is positioned at outside described 3rd side wall 130, as shown in Figure 8.The thickness of described second side wall 140 is
such as the thickness of described second side wall 140 is
deng, but the thickness of described first side wall be not limited to into
the material of described second side wall 140 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, does not specifically limit.
Then, carry out step S15, carry out source/drain doping process, to form source electrode 106 and drain electrode 107 in the described Semiconductor substrate 100 of described second side wall 140 both sides, as shown in Figure 9.
Wherein, in the present embodiment, between step S15 and step S16, also comprise and carry out self-registered technology, to form self-aligned silicide 108, as shown in Figure 10.
Then, carry out step S16, remove described second side wall 140, in the present embodiment, the outer wall due to described first side wall 120 also has described 3rd side wall 130, so, remove described 3rd side wall 130, to expose the surface of described first side wall 120, as shown in figure 11 simultaneously.
Finally, carry out step S15, the surface of the surface of described Semiconductor substrate 100, the surface of described grid structure 110 and described first side wall 120 forms stress liner layer 109, as shown in figure 12.Due to the existence of described groove 102, make described stress liner layer 109 closer to channel region 10, stress migration effect can be improved, thus effectively improve raceway groove carriers transport efficiency.
[the second embodiment]
Incorporated by reference to the schematic diagram that Figure 13-Figure 16, Figure 13-Figure 16 is device architecture in the preparation method of semiconductor device in another embodiment of the present invention, in Figure 13-Figure 16, reference number represents the parts that the statement identical with Fig. 2-Figure 12 is identical with the first execution mode.In another embodiment described, the preparation method of semiconductor device is substantially identical with the preparation method of semiconductor device in a described embodiment, its difference is: described grid structure 110 is polysilicon gate construction, namely the material of described gate material layers 112 is polysilicon, then the material of described gate dielectric layer 111 is silicon dioxide, and the material of described grid hard mask layer 113 is nitrogen oxide etc.
Preferably, invent in the preparation method of semiconductor device in another embodiment, between step S13 and step S14, also the step preparing embedded stressed semiconductor alloy-layer is comprised, to improve the stress of channel region, in the present embodiment, the step preparing embedded stressed semiconductor alloy-layer specifically comprises step S201 ~ step S204:
Carry out step S201, form the 4th side wall 230 at the sidewall of described grid structure 110, as shown in figure 13.The material of described 4th side wall 230 can be the combination of one or more of silicon nitride, silica or silicon oxynitride, does not specifically limit;
Carry out step S202, carry out cavity technique, to form cavity 104 in the described Semiconductor substrate 100 of described 4th side wall 230 both sides, as shown in figure 13.Preferably, dry etching or wet etching can be adopted to remove the described Semiconductor substrate 100 of described 4th side wall 230 both sides, and wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen; The etching liquid of described wet etching is tetramethyl aqua ammonia;
Carry out step S203, in described cavity 104, form stressed semiconductor alloy-layer 105, as shown in figure 14.Wherein, epitaxy technique can be adopted in described cavity 104 to form stressed semiconductor alloy-layer 105, due in the present embodiment, the material of described Semiconductor substrate 100 is monocrystalline silicon, so the material of described stressed semiconductor alloy-layer 105 is sige alloy, the stress of channel region can well be improved.
Carry out step S204, remove described 4th side wall 230, to expose the surface of described first side wall 120, as shown in figure 15.
Subsequently, carry out step S14, form the second side wall 240 at the sidewall of described grid structure 100, the sidewall due to described grid structure 110 is also formed with the first side wall 120, so described 3rd side wall 130 is positioned at outside the first side wall 120, as shown in figure 16.The thickness of described second side wall is greater than the thickness of described 4th side wall, and preferably, the thickness of described second side wall 140 is
such as the thickness of described second side wall 140 is
deng, but the thickness of described first side wall be not limited to into
In the present embodiment, can also realize before carrying out shallow doping process, recess process is carried out to described Semiconductor substrate, thus the exposed region of described Semiconductor substrate in described first side wall both sides forms groove, the stress liner layer that makes to be formed the subsequently beneficial effect closer to channel region can also be realized, stress migration effect can also be improved, thus effectively improve raceway groove carriers transport efficiency.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (18)
1. a preparation method for semiconductor device, comprising:
There is provided front-end devices structure, described front-end devices structure comprises Semiconductor substrate and is positioned at the grid structure in described Semiconductor substrate, and the sidewall of described grid structure is formed with the first side wall;
Recess process is carried out to described Semiconductor substrate, forms groove with the exposed region of the described Semiconductor substrate in described first side wall both sides;
Carry out shallow doping process, to form shallow doped region in the described Semiconductor substrate of described grid structure both sides;
The second side wall is formed at the sidewall of described grid structure;
Carry out source/drain doping process, to form source electrode and drain electrode in the described Semiconductor substrate of described second side wall both sides;
Remove described second side wall, to expose the surface of described first side wall; And
The surface of the surface of the surface of described Semiconductor substrate, described grid structure and described first side wall forms stress liner layer.
2. the preparation method of semiconductor device as claimed in claim 1, is characterized in that, carries out shallow doping process step and the described sidewall at described first side wall is formed between the second side wall step, also comprise described:
The 3rd side wall is formed at the sidewall of described grid structure;
Carry out cavity technique, to form cavity in the described Semiconductor substrate of described 3rd side wall both sides;
Stressed semiconductor alloy-layer is formed in described cavity.
3. the preparation method of semiconductor device as claimed in claim 2, is characterized in that, in the step of described second side wall of described removal, also comprise: remove described 3rd side wall.
4. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, described step of carrying out cavity technique comprises: adopt dry etching to remove the described Semiconductor substrate of described 3rd side wall both sides, wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen.
5. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, described step of carrying out cavity technique comprises: adopt wet etching to remove the described Semiconductor substrate of described 3rd side wall both sides, wherein, the etching liquid of described wet etching is tetramethyl aqua ammonia.
6. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, described grid structure is metal gate structure.
7. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, the material of described stressed semiconductor alloy-layer is sige alloy.
8. the preparation method of semiconductor device as claimed in claim 1, is characterized in that, carries out shallow doping process step and the described sidewall at described first side wall is formed between the second side wall step, also comprise described;
The 4th side wall is formed at the sidewall of described grid structure;
Carry out cavity technique, to form cavity in the described Semiconductor substrate of described 4th side wall both sides;
Stressed semiconductor alloy-layer is formed in described cavity;
Remove described 4th side wall, to expose the surface of described first side wall.
9. the preparation method of semiconductor device as claimed in claim 8, it is characterized in that, the thickness of described 4th side wall is less than the thickness of described second side wall.
10. the preparation method of semiconductor device as claimed in claim 8, it is characterized in that, described step of carrying out cavity technique comprises: adopt dry etching to remove the described Semiconductor substrate of described 4th side wall both sides, wherein, the etching gas of described dry etching comprises one or more combination in chlorine, hydrogen bromide, carbon tetrafluoride and oxygen.
The preparation method of 11. semiconductor device as claimed in claim 8, it is characterized in that, described step of carrying out cavity technique comprises: adopt wet etching to remove the described Semiconductor substrate of described 4th side wall both sides, wherein, the etching liquid of described wet etching is tetramethyl aqua ammonia.
The preparation method of 12. semiconductor device as claimed in claim 8, it is characterized in that, described grid structure is polysilicon gate construction.
The preparation method of 13. semiconductor device as claimed in claim 8, is characterized in that, the material of described stressed semiconductor alloy-layer is sige alloy.
14., as the preparation method of the semiconductor device in claim 1-13 as described in any one, is characterized in that, between the step of source/drain doping process and the step of described second side wall of described removal, also comprise: carry out self-registered technology described carrying out.
The preparation method of 15. semiconductor device as claimed in claim 1, it is characterized in that, the degree of depth of described groove is
The preparation method of 16. semiconductor device as claimed in claim 1, it is characterized in that, the step of described Semiconductor substrate being carried out to recess process comprises: adopt the described first side wall both sides of dry etching removal to have the described Semiconductor substrate of certain depth, form described groove with the exposed region of the described Semiconductor substrate in described first side wall both sides.
The preparation method of 17. semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described first side wall is
The preparation method of 18. semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described second side wall is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407943.1A CN104425383B (en) | 2013-09-09 | 2013-09-09 | The preparation method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407943.1A CN104425383B (en) | 2013-09-09 | 2013-09-09 | The preparation method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104425383A true CN104425383A (en) | 2015-03-18 |
| CN104425383B CN104425383B (en) | 2017-07-11 |
Family
ID=52974020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310407943.1A Active CN104425383B (en) | 2013-09-09 | 2013-09-09 | The preparation method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104425383B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090267117A1 (en) * | 2008-04-29 | 2009-10-29 | Chartered Semiconductor Manufacturing, Ltd. | Enhanced stress for transistors |
| CN102110652A (en) * | 2009-12-24 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing embedded type semiconductor devices |
| CN102184895A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
| US20120068268A1 (en) * | 2010-09-22 | 2012-03-22 | Hsiao Tsai-Fu | Transistor structure and method of fabricating the same |
-
2013
- 2013-09-09 CN CN201310407943.1A patent/CN104425383B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090267117A1 (en) * | 2008-04-29 | 2009-10-29 | Chartered Semiconductor Manufacturing, Ltd. | Enhanced stress for transistors |
| CN102110652A (en) * | 2009-12-24 | 2011-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing embedded type semiconductor devices |
| US20120068268A1 (en) * | 2010-09-22 | 2012-03-22 | Hsiao Tsai-Fu | Transistor structure and method of fabricating the same |
| CN102184895A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104425383B (en) | 2017-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101386838B1 (en) | METHODS AND APPARATUS FOR DOPED SiGe SOURCE/DRAIN STRESSOR DEPOSITION | |
| US9306019B2 (en) | Integrated circuits with nanowires and methods of manufacturing the same | |
| US8043919B2 (en) | Method of fabricating semiconductor device | |
| US9431252B2 (en) | Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same | |
| KR20120022464A (en) | Method of fabricating semiconductor device | |
| CN105448739B (en) | Semiconductor device having gate structure and method of manufacturing the same | |
| US20160133723A1 (en) | Tunneling Field Effect Transistor (TFET) With Ultra Shallow Pockets Formed By Asymmetric Ion Implantation and Method of Making Same | |
| CN103426765A (en) | Forming method of semiconductor device and forming method of fin type field effect transistor | |
| US9673324B1 (en) | MOS device with epitaxial structure associated with source/drain region and method of forming the same | |
| US8993445B2 (en) | Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection | |
| CN104253046A (en) | Fin field effect transistor and forming method thereof | |
| CN103779278A (en) | CMOS (Complementary Metal Oxide Semiconductor) tube forming method | |
| CN103000534A (en) | Manufacture method of groove-type P-type metal oxide semiconductor power transistor | |
| US10686078B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN102339852A (en) | Semiconductor device and method for manufacturing the same | |
| CN103295899A (en) | Manufacturing method of FinFET device | |
| CN103855004A (en) | Transistor forming method | |
| CN102931233B (en) | Nmos pass transistor and forming method thereof | |
| US20180108656A1 (en) | Asymmetrical fin structure and method of fabricating the same | |
| US8541847B2 (en) | Semiconductor device and method for fabricating the same | |
| CN103123899B (en) | FinFET manufacture method | |
| CN108573872B (en) | Semiconductor structure and forming method thereof | |
| CN105632926A (en) | Method for forming fin type field effect transistor | |
| CN104064463A (en) | Transistor and formation method thereof | |
| CN103426766B (en) | Pmos transistor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |