CN106298790A - The forming method of flash memory - Google Patents
The forming method of flash memory Download PDFInfo
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- CN106298790A CN106298790A CN201610828320.5A CN201610828320A CN106298790A CN 106298790 A CN106298790 A CN 106298790A CN 201610828320 A CN201610828320 A CN 201610828320A CN 106298790 A CN106298790 A CN 106298790A
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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Abstract
A kind of forming method of flash memory, including: Semiconductor substrate is provided, Semiconductor substrate has floating gate structural membrane and the control gate structural membrane being positioned in floating gate structural membrane；Control gate structural membrane is formed several discrete dielectric layers, there is between adjacent dielectric the first opening；The first side wall is formed at the first opening sidewalls；Remove control gate structural membrane and the floating gate structural membrane of the first open bottom with the first side wall for mask, form the second opening in the first open bottom；In the Semiconductor substrate of the second open bottom, form source region, source region has source ion；After forming source region, form the second side wall at the second opening sidewalls；After forming the second side wall, doping compensation ion in source region, the conduction type of described counterion is identical with the conduction type of source ion；In source region after doping compensation ion, the first opening and the second opening form source line layer.Described method is avoided that flash memory erasing was lost efficacy.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the forming method of a kind of flash memory.
Background technology
Flash memory is a kind of important device in IC products.Being mainly characterized by of flash memory is being not added with
The information of storage can be kept for a long time in the case of voltage.Flash memory has integrated level height, faster access speed and is prone to
The advantages such as erasing, thus be widely used.
Flash memory is divided into two types: gatestack (stack gate) flash memory and point grid (split gate) are fast
Flash memory.The problem that gatestack flash memory existed erasing.Split-gate flash memory owing to having higher programming efficiency,
Functionally can avoid excessive erasable problem erasable, thus be widely used in all kinds of such as smart card, SIM, microcontroller
In the electronic product such as device, mobile phone.
But, there is the problem that serious erasing was lost efficacy in existing Split-gate flash memory.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of flash memory, to avoid flash memory erasing to lose
Effect.
For solving the problems referred to above, the present invention provides the forming method of a kind of flash memory, including: quasiconductor lining is provided
The end, described Semiconductor substrate has floating gate structural membrane and the control gate structural membrane being positioned in floating gate structural membrane；Controlling
Form several discrete dielectric layers in grid structural membrane, there is between adjacent dielectric the first opening；In the first opening sidewalls shape
Become the first side wall；Control gate structural membrane and the floating gate structural membrane of the first open bottom is removed with the first side wall for mask,
First open bottom forms the second opening；In the Semiconductor substrate of the second open bottom formed source region, source region has source from
Son；After forming source region, form the second side wall at the second opening sidewalls；After forming the second side wall, doping compensation ion in source region,
The conduction type of described counterion is identical with the conduction type of source ion；In source region after doping compensation ion, open first
Mouth and the second opening are formed source line layer.
Optionally, in described source region, the technique of doping compensation ion is ion implantation technology.
Optionally, when the conduction type of described source ion is p-type, the conduction type of described counterion is p-type.
Optionally, the parameter of described ion implantation technology includes: the ion of employing is boron ion, Implantation Energy be 2KeV～
4KeV, implantation dosage is 1E15atom/cm2～1E16atom/cm2, implant angle is 70 degree～90 degree.
Optionally, the parameter of described ion implantation technology includes: the ion of employing is indium ion, Implantation Energy be 5KeV～
20KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
Optionally, when the conduction type of described source ion is N-type, the conduction type of described counterion is N-type.
Optionally, the parameter of described ion implantation technology includes: the ion of employing is phosphonium ion, Implantation Energy be 2KeV～
5KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
Optionally, the parameter of described ion implantation technology includes: the ion of employing is arsenic ion, Implantation Energy be 3KeV～
15KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
Optionally, described Semiconductor substrate has wordline bitline regions and line floating gate region, source, and line floating gate region, described source is positioned at phase
Between adjacent wordline bitline regions；Described floating gate structural membrane is positioned in the Semiconductor substrate of line floating gate region, part source, and it is floating to be positioned at source line
Floating gate structural membrane in the Semiconductor substrate of grid region also extends in the Semiconductor substrate of described wordline bitline regions；Described control gate
Structural membrane is positioned in Semiconductor substrate and floating gate structural membrane；Described dielectric layer covers the control gate structure of wordline bitline regions
Film.
Optionally, after forming described source line layer, also include: remove dielectric layer and the control gate structure of wordline bitline regions
Film, forms control gate structure bottom the first side wall；The 3rd side is formed in described control gate structure and the first side wall sidewall
Wall；With described first side wall, source line layer and the 3rd side wall as mask, remove the part floating gate structural membrane of wordline bitline regions,
Floating gate structure is formed on the bottom of control gate structure and the 3rd side wall；In the 3rd side wall sidewall exposed and floating gate structure
Sidewall forms word line structure.
Compared with prior art, technical scheme has the advantage that
In the forming method of the flash memory that technical solution of the present invention provides, before forming the second side wall, form source
District so that source region is relatively big in the size being perpendicular on the second opening sidewalls direction, the electric capacity that source region and floating gate structure are constituted increases
Greatly, therefore, it is possible to be more coupling in floating gate structure by the voltage on the line layer of source, beneficially flash memory is programmed.
After forming the second side wall, doping compensation ion in source region.Due to the conduction type of described counterion and leading of source ion
Electricity type is identical, and the most described counterion can compensate for source ion loss in the second side wall forming process in source region.Make
Obtain the concentration of source ion in the region that source region contacts with source line layer to increase.And then make the contact resistance between source line layer and source region
Reduce.Therefore, the electric current that flash memory reads in erasing operating process is relatively big, thus avoids word line structure erasing to lose efficacy.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of Split-gate flash memory；
Fig. 2 to Figure 17 is the structural representation of flash memory forming process in one embodiment of the invention.
Detailed description of the invention
As described in background, there is serious erasing inefficacy in existing Split-gate flash memory.
Fig. 1 is the structural representation of a kind of Split-gate flash memory, and Split-gate flash memory includes: Semiconductor substrate 100；
Grid structure unit, grid structure unit includes two discrete grid structures, has groove (not shown) between grid structure,
Grid structure includes the floating gate structure 120 being positioned on part semiconductor substrate 100 and the control being positioned in floating gate structure 120
Grid structure 121；First side wall 130, is positioned in control gate structure 121；Second side wall 131, is positioned at recess sidewall；Source line layer
140, between the first side wall 130 and between the second side wall 131；Word line structure, is positioned at grid structure, the first side wall 130
Both sides sidewall with source line layer 140；Source region 150, is positioned in the Semiconductor substrate 100 bottom source line layer 140.
A kind of method forming above-mentioned Split-gate flash memory includes: provide Semiconductor substrate, and described Semiconductor substrate has
Having wordline bitline regions and line floating gate region, source, line floating gate region, described source is between adjacent word line bitline regions；Serve as a contrast at part semiconductor
Described wordline bitline regions and the floating gate structural membrane of line floating gate region, source and control gate structural membrane it is developed across at the end；Form medium
Layer, described dielectric layer covers floating gate structural membrane and the control gate structural membrane of wordline bitline regions, has between adjacent dielectric
First opening；The first side wall is formed at the first opening sidewalls；The floating gate of the first open bottom is removed with the first side wall for mask
Structural membrane and control gate structural membrane, form the second opening in the first open bottom；Semiconductor substrate in the second open bottom
Middle formation source region；After forming source region, form the second side wall at the second opening sidewalls；After forming the second side wall, at the first opening and
Second opening is formed source line layer；After the line layer of formation source, remove the dielectric layer of wordline bitline regions, control gate structural membrane and floating boom
Electrode structure film, forms control gate structure and floating gate structure；Then in the first side wall exposed, control gate structure and floating
Gate structure sidewall forms word line structure.
In said method, it is initially formed source region, rear formation the second side wall.It is initially formed source region, the rear reason forming the second side wall
It is: make source region relatively big in the size being perpendicular on the second opening sidewalls direction, the electric capacity that source region and floating gate structure are constituted
Increase, therefore, it is possible to the voltage on the line layer of source is more coupling in floating gate structure, with at flash memory programmed
Improving the voltage in floating gate structure in journey, beneficially Split-gate flash memory is programmed.
But, there is serious erasing Problem of Failure in the Split-gate flash memory that said method is formed, it has been investigated that, former
Because being:
During forming the second side wall, the source region exposed can be caused etching loss, easily by the source in source region
Region corresponding to the peak concentration of ion is removed, and causes the concentration of source ion in the region that source region contact with source line layer to be less than described
Peak concentration, the contact resistance thus resulting in source line layer and source region is bigger.And then cause in Split-gate flash memory erasing operation
During read electric current too small.And the size of the electric current whether Split-gate flash memory erasing lost efficacy according to described reading is sentenced
Disconnected.If the electric current of described reading is too small, then it is judged as that Split-gate flash memory erasing was lost efficacy.
On this basis, the present invention provides the forming method of a kind of flash memory, including: Semiconductor substrate, institute are provided
State the control gate structural membrane that there is in Semiconductor substrate floating gate structural membrane He be positioned in floating gate structural membrane；In control gate structure
Form several discrete dielectric layers on film, there is between adjacent dielectric the first opening；First is formed at the first opening sidewalls
Side wall；Remove control gate structural membrane and the floating gate structural membrane of the first open bottom with the first side wall for mask, open first
The second opening is formed bottom Kou；In the Semiconductor substrate of the second open bottom, form source region, source region has source ion；Formed
After source region, form the second side wall at the second opening sidewalls；After forming the second side wall, doping compensation ion in source region, described benefit
The conduction type repaying ion is identical with the conduction type of source ion；In source region after doping compensation ion, at the first opening and
Two openings are formed source line layer.
In described method, before forming the second side wall, form source region so that source region is being perpendicular to the second opening sidewalls side
Size upwards is relatively big, and the electric capacity that source region and floating gate structure are constituted increases, therefore, it is possible to by more for the voltage on the line layer of source
Being coupling in floating gate structure, beneficially flash memory is programmed.After forming the second side wall, doping compensation in source region
Ion.Owing to the conduction type of described counterion and the conduction type of source ion are identical, the most described counterion can be mended
Repay source ion loss in the second side wall forming process in source region.Make source ion in the region that source region contacts with source line layer
Concentration increases.And then the contact resistance between source line layer and source region is reduced.Therefore, flash memory is in erasing operating process
The electric current of middle reading is relatively big, thus avoids word line structure erasing to lose efficacy.
Understandable, below in conjunction with the accompanying drawings to the present invention for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
Specific embodiment be described in detail.
Fig. 2 to Figure 17 is the structural representation of flash memory forming process in one embodiment of the invention.
With reference to Fig. 2, it is provided that Semiconductor substrate 200.
Described Semiconductor substrate 200 provides technique platform for forming flash memory.
Described Semiconductor substrate 200 has wordline bitline regions and line floating gate region, source, and line floating gate region, described source is positioned at adjacent words
Between line bitline regions.
The material of described Semiconductor substrate 200 can be silicon, germanium or SiGe.Described Semiconductor substrate 200 is all right
Silicon-on-insulator (SOI), germanium on insulator (GeOI) or germanium on insulator SiClx (SiGeOI).In the present embodiment, described partly lead
The bill of materials crystal silicon of body substrate 200.
Then, floating gate structural membrane and control gate structural membrane are formed.
In the present embodiment, described floating gate structural membrane is positioned in line floating gate region, part source Semiconductor substrate 200, and is positioned at source
Floating gate structural membrane in line floating gate region Semiconductor substrate 200 also extends in described wordline bitline regions Semiconductor substrate 200；Control
Controlling grid structural film is positioned in Semiconductor substrate 200 and floating gate structural membrane.
Floating gate structural membrane and the forming process of control gate structural membrane is specifically introduced below with reference to Fig. 3 to Fig. 7.
With reference to Fig. 3, form initial floating gate structural membrane 210 on semiconductor substrate 200；In described initial floating gate structure
The first mask layer 220 is formed on film 210.
It is initial be positioned in initial floating gate oxide film that described initial floating gate structural membrane 210 includes initial floating gate oxide film
Floating boom film.
Described initial floating gate oxide film isolates initial floating boom film and Semiconductor substrate 200.Described initial floating gate oxide film is used
In being subsequently formed floating gate oxide film.The formation process of described initial floating gate oxide film is depositing operation or oxidation technology.At the beginning of described
The material of beginning floating gate oxide film is silicon dioxide.
Described initial floating boom film is used for being subsequently formed floating boom film.The formation process of described initial floating boom film is depositing operation,
Such as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition method.Institute
The material stating initial floating boom film is polysilicon.
Described first mask layer 220 is used for being subsequently formed mask layer.The formation work of described first mask layer 220
Skill is depositing operation, such as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemistry gas
Phase depositing operation.Described first mask layer 220 can be single layer structure, it is also possible to for laminated construction.When the first mask material
When the bed of material 220 is single layer structure, the material of the first mask layer 220 can be silicon nitride, silicon oxynitride or fire sand.When
When first mask layer 220 is laminated construction, the material of each layer in laminated construction can be silicon nitride, silicon oxynitride or
Fire sand.
The thickness of described initial floating gate oxide film, initial floating boom film and the first mask layer 220 can be according to technique need
Want and set.
With reference to Fig. 4, the most described first mask layer 220 (with reference to Fig. 3), (reference of initial floating gate structural membrane 210
Fig. 3) with part semiconductor substrate 200, described Semiconductor substrate 200 is formed floating gate structural membrane 211 and is positioned at floating gate
The first mask layer 221 in structural membrane 211, concurrently forms groove 230, and described groove 230 is positioned at adjacent floating grid structure film
211, between adjacent first mask layer 221 and in Semiconductor substrate 200.
Described floating gate structural membrane 211 is positioned in line floating gate region, part source Semiconductor substrate 200, and is positioned at line floating gate region, source
Floating gate structural membrane 211 in Semiconductor substrate 200 also extends in described wordline bitline regions Semiconductor substrate 200.
Described floating gate structural membrane 211 includes the floating gate oxide film being positioned on part semiconductor substrate 200 and is positioned at floating boom
Floating boom film on oxide-film.Described floating gate oxide film is positioned in line floating gate region, part source Semiconductor substrate 200, and it is floating to be positioned at source line
Floating gate oxide film in grid region Semiconductor substrate 200 also extends in described wordline bitline regions Semiconductor substrate 200.
In the present embodiment, the first mask layer 220 forms patterned photoresist layer, described patterned photoetching
Glue-line defines the position of groove 230；With described patterned photoresist layer as mask, etch the first mask layer 220, just
Beginning floating gate structural membrane 210 and part semiconductor substrate 200, form groove 230, floating gate structural membrane 211 and the first mask layer
221；Then described patterned photoresist layer is removed.
In other embodiments, the first mask layer forms patterned photoresist layer, described patterned light
Photoresist layer defines the position of groove；With described patterned photoresist layer as mask, etch the first mask layer, form the
One mask layer；Then with described first mask layer for mask etching initial floating gate structural membrane and part semiconductor substrate, formed
Groove, floating gate structural membrane；After forming the first mask layer, remove described patterned photoresist layer.
With reference to Fig. 5, in groove 230 (with reference to Fig. 4), form sealing coat 240；After forming sealing coat 240, remove first and cover
Film layer 221 (with reference to Fig. 4).
The material of described sealing coat 240 is silicon oxide.
The top surface of described sealing coat 240 is higher than the top surface of floating gate structural membrane 211；Or sealing coat 240
Top surface is higher than Semiconductor substrate 200 surface and the top surface less than floating gate structural membrane 211；Or sealing coat 240
Top surface flushes with the top surface of floating gate structural membrane 211.
In the present embodiment, the top surface of described sealing coat 240 is higher than the top surface of floating gate structural membrane 211.
In conjunction with being the profile obtained along line of cut A-A1 in Fig. 6 with reference to Fig. 6 and Fig. 7, Fig. 7, in Semiconductor substrate 200
With formation control gate structural membrane 250 in floating gate structural membrane 211.
Concrete, described control gate structural membrane 250 covers sealing coat 240 and floating gate structural membrane 211.
Described control gate structural membrane 250 includes control gate deielectric-coating and the control grid electrode being positioned on control gate deielectric-coating
Film.Described control gate deielectric-coating covers floating gate structural membrane 211 and sealing coat 240.
In the present embodiment, described control gate deielectric-coating is laminated construction, and described control gate deielectric-coating includes the first control gate
Deielectric-coating, it is positioned at the second control gate deielectric-coating on the first control gate deielectric-coating surface and is positioned on the second control gate deielectric-coating
3rd control gate deielectric-coating.
The material of described first control gate deielectric-coating and the 3rd control gate deielectric-coating is silicon oxide.Described second control gate is situated between
The material of plasma membrane is silicon nitride.
Described control gate deielectric-coating is that the advantage of laminated construction is: the dielectric constant making control gate deielectric-coating is relatively big, control
Gate electrode film processed, control gate deielectric-coating and and floating boom film constitute electric capacity numerical value increase, the voltage on subsequent control grid can
More it is coupled on floating boom, beneficially the carrying out of the programming of flash memory.
In other embodiments, described control gate deielectric-coating is single layer structure, and the material of described control gate deielectric-coating is oxygen
SiClx.
The material of described control grid electrode film is heavily doped polysilicon.
Form described first control gate deielectric-coating, the second control gate deielectric-coating and the 3rd control gate deielectric-coating and control gate electricity
The technique of pole film is depositing operation, and such as plasma activated chemical vapour deposition technique, atom layer deposition process, low pressure chemical phase sinks
Long-pending technique or sub-atmospheric pressure chemical vapor deposition method.
Continuing with reference to Fig. 6 and Fig. 7, control gate structural membrane 250 forms several discrete dielectric layers 260, phase
Between adjacent dielectric layer 260, there is the first opening 261.
Fig. 7 shows wordline bitline regions A and line floating gate region, source B.
Described dielectric layer 260 covers the control gate structural membrane 250 of wordline bitline regions A, and exposes line floating gate region, source B's
Control gate structural membrane 250.
The material of described dielectric layer 260 is silicon nitride or silicon oxynitride.
The method forming dielectric layer 260 includes: form deielectric-coating (not shown) in described control gate structural membrane 250；
Forming patterned second mask layer on described deielectric-coating, the second mask layer covers deielectric-coating and the exposure of wordline bitline regions A
Go out the deielectric-coating of line floating gate region, source B；Remove the deielectric-coating of line floating gate region, source B with the second mask layer for mask etching, form medium
Layer 260；Then the second mask layer is removed.
It is the schematic diagram on the basis of Fig. 7 with reference to Fig. 8, Fig. 8, forms the first side wall 270 at the first opening 261 sidewall.
The material of described first side wall 270 is silicon oxide or silicon oxynitride.
The method forming described first side wall 270 includes: at the sidewall of described first opening 261 and bottom and medium
The top surface of layer 260 forms the first side wall film (not shown)；Remove dielectric layer 260 top surface and first opening 261 end
The first side wall film in portion, forms the first side wall 270.
The technique forming described first side wall film is depositing operation, such as plasma activated chemical vapour deposition technique, low pressure
Learn gas-phase deposition, sub-atmospheric pressure chemical vapor deposition method or atom layer deposition process.
The technique of the first side wall film bottom removal dielectric layer 260 top surface and the first opening 261 is for being etched back to work
Skill.Concrete, the technique removing the first side wall film bottom dielectric layer 260 top surface and the first opening 261 can be certainly
Etched in alignment technique.
With reference to Fig. 9, remove the control gate structural membrane 250 bottom the first opening 261 with the first side wall 270 for mask and float
Grid structure film 211, forms the second opening 262 bottom the first opening 261.
With the first side wall 270 as mask, etch the control gate structural membrane 250 bottom the first opening 261 and floating gate knot
Structure film 211, until exposing the surface of Semiconductor substrate 200, forms the second opening 262 bottom the first opening 261.
With reference to Figure 10, the Semiconductor substrate 200 bottom the second opening 262 forms source region 280.
Described source region has source ion.
When the type of described flash memory is N-type, in described source region 280, the conduction type of source ion is N-type；Work as institute
Stating the type of flash memory when being p-type, in described source region 280, the conduction type of source ion is p-type.
The method forming source region 280 includes: with described first side wall 270 as mask, to partly leading bottom the second opening 262
Body substrate 200 carries out source ion injection, forms source dopant region；Then described source dopant region is carried out source annealing, forms source
District 280.
Described source annealing is for activating the source ion in source dopant region, and repairs the quasiconductor that source ion injection causes
Lattice damage in substrate 200.
After forming source region 280, the peak concentration position of the source ion in source region 280 is positioned at source region 280 near surface.
With reference to Figure 11, after forming source region 280, form the second side wall 271 at the second opening 262 sidewall.
The material of described second side wall 271 is silicon oxide or silicon oxynitride.
The method forming the second side wall 271 includes: at dielectric layer 260 and the first side wall 270 surface and the second opening
Second side wall film (not shown) is formed on 262 sidewalls and bottom；Etching removes dielectric layer 260 and the second of the first side wall 270 surface
Side wall film, forms the second side wall 271.
In the present embodiment, described second side wall 271 is different from the material of described first side wall 270, reduces and removes dielectric layer
260 and first side wall 270 surface the second side wall film during to first side wall 270 etching loss.
In the present embodiment, being initially formed source region 280, rear formation the second side wall 271, advantage is: make source region 280 vertically
Size in the second opening 262 sidewall direction is relatively big, and the electric capacity that source region 280 and follow-up floating gate structure are constituted increases, therefore
Voltage on subsequent source line layer more can be coupling in floating gate structure, to carry in programming process at flash memory
Voltage in high floating gate structure, beneficially Split-gate flash memory is programmed.
It should be noted that during forming the second side wall 271, the source region 280 exposed can cause etching damage
Consumption, easily removes region corresponding for the peak concentration of the source ion in source region 280, causes source region 280 and subsequent source line layer to connect
In the region touched, the concentration of source ion is less than described peak concentration, thus results in subsequent source line layer and the contact resistance of source region 280
Bigger.And then can cause follow-up less at flash memory electric current of reading during erasing operation.And flash memory
The size of the electric current whether erasing lost efficacy according to described reading judges.If the electric current of described reading is too small, then it is judged as quick flashing
Memorizer erasing was lost efficacy.Therefore, in the present embodiment, after forming the second side wall 271, follow-up doping compensation ion in source region 280.
With reference to Figure 12, after forming the second side wall 271, doping compensation ion in source region 280, the conduction of described counterion
Type is identical with the conduction type of source ion.
In source region 280, the technique of doping compensation ion is ion implantation technology.
Concrete, with dielectric layer the 260, first side wall 270 and the second side wall 271 as mask, use ion implantation technology to exist
Injecting compensating ion in source region 280, thus doping compensation ion in source region 280.
Doping compensation ion in source region 280, forms compensating basin, the surface of described compensating basin and source region in source region 280
The surface of 280 flushes.
When the conduction type of the source ion in described source region 280 is p-type, the conduction type of described counterion is p-type.
When the conduction type of the source ion in described source region 280 is N-type, the conduction type of described counterion is N-type.
If the energy of described ion implanting is too high, the degree of depth causing counterion injection source region 280 is excessive, and counterion is dense
Degree highest zone is excessive to the distance on source region 280 surface, and accordingly, counterion is in the concentration of source region 280 near-surface region
Too small.The contact resistance of the source line layer that therefore can not effectively reduce source region 280 and be subsequently formed.If the energy of described ion implanting
Measure too low, it is impossible to effectively counterion is injected in source region 280.And atomic mass corresponding to different counterion is not
With.In the case of the identical injection degree of depth, the counterion that atomic mass is bigger needs the energy of loss relatively greatly, therefore needs relatively
Big Implantation Energy.
If the implantation dosage of described ion implantation technology is too high, process costs is caused to increase；If described ion implantation technology
Implantation dosage too low, cause ion implanting post-compensation ion concentration in source region 280 too small, therefore can not effectively reduce
Source region 280 and the contact resistance of source line layer being subsequently formed.For the counterion that atomic mass is less, atomic mass is the least,
Counterion divergence loss in ion implantation process is the biggest.Therefore need to make up different counterions at ion implantation process
The divergence loss of middle correspondence.So for the counterion that atomic mass is less, atomic mass is the least, the implantation dosage phase of needs
To the biggest.
The implant angle of described ion implantation technology is relevant with Implantation Energy, and described implant angle is and Semiconductor substrate
Angle between 100 surfaces.In the case of certain injection degree of depth, Implantation Energy is the biggest, and the implant angle of needs is the least.
To sum up, the Implantation Energy of described ion implantation technology, implantation dosage and implant angle need to select suitable scope.
And atomic mass corresponding to different modified ion is different.In the case of the identical injection degree of depth, bigger the changing of atomic mass
Property ion need the energy of loss relatively big, therefore need bigger Implantation Energy.
When described counterion is boron ion, the parameter of described ion implantation technology includes: the ion of employing be boron from
Son, Implantation Energy is 2KeV～4KeV, and implantation dosage is 1E15atom/cm2～1E16atom/cm2, implant angle be 70 degree～
90 degree.
When described counterion is indium ion, the parameter of described ion implantation technology includes: Implantation Energy be 5KeV～
20KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
When described counterion is phosphonium ion, the parameter of described ion implantation technology includes: Implantation Energy be 2KeV～
5KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
When described counterion is arsenic ion, the parameter of described ion implantation technology includes: Implantation Energy be 3KeV～
15KeV, implantation dosage is 1E14atom/cm2～1E15atom/cm2, implant angle is 70 degree～90 degree.
After carrying out described ion implanting, make annealing treatment, to activate described counterion, and repair ion implanting and cause
The lattice damage of source region 280.
With reference to Figure 13, in source region 280 after doping compensation ion, at the first opening 261 (with reference to Figure 12) and the second opening
Formation source line layer 290 in 262 (with reference to Figure 12).
The material of described source line layer 290 is polysilicon.
The method of formation source line layer 290 includes: in the first opening 261 and the second opening 262 and the first side wall 270 and
Source line film (not shown) is formed on dielectric layer 260；Remove the source line film higher than dielectric layer 260 top surface, at the first opening 261
With formation source line layer 290 in the second opening 262.
The technique of formed source line film is depositing operation, such as plasma activated chemical vapour deposition technique, low pressure chemical phase
Depositing operation or sub-atmospheric pressure chemical vapor deposition method.
The technique removing the source line film higher than dielectric layer 260 top surface is flatening process, such as cmp work
Skill.
With reference to Figure 14, after forming source line layer 291, remove dielectric layer 260 (with reference to Figure 13) and the control gate of wordline bitline regions A
Electrode structure film 250 (with reference to Figure 13), forms control gate structure 251 bottom the first side wall 270.
Remove the technique of the dielectric layer 260 of wordline bitline regions A and control gate structural membrane 250 be wet-etching technology or
Dry etch process.
In the present embodiment, the dielectric layer 260 removing wordline bitline regions A is wet-etching technology, removes control gate structure
The technique of film 250 is dry etch process.
Described control gate structure 251 includes control gate dielectric layer and the control grid electrode being positioned on control gate dielectric layer
Layer.The corresponding described control gate deielectric-coating of described control gate dielectric layer, the corresponding described control grid electrode film of described control gate electrode layer.
In the present embodiment, described control gate dielectric layer is laminated construction, and described control gate dielectric layer includes the first control gate
Dielectric layer, it is positioned at the second control gate dielectric layer of first grid dielectric layer surface and is positioned at the 3rd on the second control gate dielectric layer
Control gate dielectric layer.The corresponding first control gate deielectric-coating of described first control gate dielectric layer, described second control gate dielectric layer pair
Answer the second control gate deielectric-coating, the corresponding 3rd control gate deielectric-coating of described 3rd control gate dielectric layer.
In other embodiments, when described control gate deielectric-coating is single layer structure, described control gate dielectric layer is monolayer
Structure.
With reference to Figure 15, form the 3rd side wall in described control gate structure 251 and the first side wall 270 sidewall.
In the present embodiment, described 3rd side wall includes that inside wall 301 and external wall 302, inside wall 301 are positioned at external wall
Between 302 and control gate structure 251 and between external wall 302 and the first side wall 270.
In the present embodiment, the forming method forming the 3rd side wall includes: in floating gate structural membrane the 211, first side wall, control
The surface of grid structure 251 and source line layer 290 forms the first side wall film (not shown)；It is etched back to described first side wall film, shape
Become the 3rd side wall.
Concrete, on floating gate structural membrane the 211, first side wall, control gate structure 251 and the surface of source line layer 290
Form inside wall film；Form external wall film on inside wall film surface, external wall film and inside wall film constitute the first side wall film.
The corresponding described inside wall film of described inside wall 301, the corresponding described external wall film of described external wall 302.
Described inside wall 301 is L-shaped, and described external wall 302 is positioned at " L " type surface of inside wall 301.
The material of described inside wall 301 is silicon oxide, and the material of described external wall 302 is silicon nitride.
In other embodiments, described 3rd side wall is single layer structure, and the material of described 3rd side wall is silicon oxide or nitrogen
Silicon oxide.
Owing to defining the 3rd side wall, hence in so that the floating gate structure being subsequently formed is being perpendicular to floating gate structure side wall
Size on direction is more than control gate structure 251 in the size being perpendicular in control gate structure 251 sidewall direction.Secondly,
Isolation performance between control gate structure 251 and the word line structure being subsequently formed is strengthened.
It should be noted that in the present embodiment, the 3rd side wall includes inside wall 301 and external wall 302, inside wall 301
Material is silicon oxide, and the material of described external wall 302 is silicon nitride.Control gate structure 251 can be improved and be subsequently formed
Isolation performance between word line structure, and avoid the 3rd side wall excessive to the stress of control gate structure 251, thus avoid described
The excessive lattice defect causing control gate structure 251 of stress.
With reference to Figure 16, with described first side wall 270, source line layer 290 and the 3rd side wall as mask, remove wordline bitline regions A
Part floating gate structural membrane 211, the bottom of control gate structure 251 and the 3rd side wall formed floating gate structure 212.
Described floating gate structure 212 includes floating gate dielectric layer and the floating boom being positioned on floating gate dielectric layer.Described floating gate dielectric
The corresponding described floating gate oxide film of layer, the corresponding described floating boom film of described floating boom.
Described floating gate structure 212 is positioned on the part semiconductor substrate 200 of described source line floating gate region B.
The technique of the floating gate structural membrane 211 removing wordline bitline regions A is wet-etching technology or dry etch process.
In the present embodiment, described floating gate structure 212 is more than in the size being perpendicular in floating gate structure 212 sidewall direction
Control gate structure 251 in the size being perpendicular in control gate structure 251 sidewall direction, advantage is: compile at flash memory
There is more electronics to be stored in floating gate structure 212 during journey, improve the programming efficiency of flash memory.
Then, with reference to Figure 17, word line structure is formed at the 3rd side wall sidewall exposed and floating gate structure 212 sidewall.
Described word line structure is positioned in the Semiconductor substrate 200 of part wordline bitline regions A.
Described word line structure includes wordline oxide layer 303 and wordline 304, and described wordline 304 is positioned at the sidewall of the 3rd side wall；
Described wordline oxide layer 303 is between the 3rd side wall and wordline 304, between floating gate structure 212 and wordline 304, Yi Jiban
Between conductor substrate 200 and wordline 304.
The material of described wordline oxide layer 303 is silicon oxide.
The material of described wordline 304 is polysilicon.
The method forming wordline oxide layer 303 and wordline 304 includes: in the Semiconductor substrate 200 of described wordline bitline regions A
The 3rd side wall sidewall that surface, wordline bitline regions A expose and floating gate structure 212 sidewall and source line layer 290 and the first side
Wordline oxide-film (not shown) is formed on wall 270；Described wordline oxide-film is formed wordline film；It is etched back to wordline film and wordline
Oxide-film, forms wordline oxide layer 300 and wordline 304.
The corresponding wordline oxide-film of described wordline oxide layer 303, the corresponding wordline film of described wordline 304.
Between described wordline 304 and source line layer 290 by wordline oxide layer the 300, the 3rd side wall and the first side wall 270 every
From.
Then, the sidewall in described wordline 304 forms wordline side wall 305；With described wordline side wall 305 and word line structure it is
Mask, carries out leaking ion implanting, at the quasiconductor of wordline side wall 305 sidepiece to the Semiconductor substrate 200 of wordline side wall 305 sidepiece
Substrate 200 is formed leakage doped region；Then described leakage doped region is carried out leakage annealing, forms drain region 281.
Described drain region 281 is between adjacent word line structure.Described drain region 281 is used for being electrically connected bit line.
It should be noted that in other embodiments, it is formed without the 3rd side wall.Accordingly, after forming source line layer, remove
The dielectric layer of wordline bitline regions, control gate structural membrane and floating gate structural membrane, formed and be positioned at the control gate bottom the first side wall
Electrode structure and be positioned at the floating gate structure of control gate structural base.In the case, floating gate structure is being perpendicular to floating boom
Size in electrode structure sidewall direction is equal to control gate structure in the size being perpendicular on control gate structure side wall direction.So
After, the sidewall in the first side wall exposed, control gate structure and floating gate structure forms word line structure；In word line structure side
Wall forms wordline side wall；Drain region is formed in the Semiconductor substrate of wordline side wall sidepiece.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Limit in the range of standard.
Claims (10)
1. the forming method of a flash memory, it is characterised in that including:
Semiconductor substrate is provided, described Semiconductor substrate has floating gate structural membrane and the control being positioned in floating gate structural membrane
Grid structural membrane；
Control gate structural membrane is formed several discrete dielectric layers, there is between adjacent dielectric the first opening；
The first side wall is formed at the first opening sidewalls；
Control gate structural membrane and the floating gate structural membrane of the first open bottom is removed, at the first opening with the first side wall for mask
Second opening is formed on bottom；
In the Semiconductor substrate of the second open bottom, form source region, source region has source ion；
After forming source region, form the second side wall at the second opening sidewalls；
After forming the second side wall, doping compensation ion in source region, the conduction type of described counterion and the conduction of source ion
Type is identical；
In source region after doping compensation ion, the first opening and the second opening form source line layer.
The forming method of flash memory the most according to claim 1, it is characterised in that doping compensation in described source region
The technique of ion is ion implantation technology.
The forming method of flash memory the most according to claim 2, it is characterised in that when the conductive-type of described source ion
When type is p-type, the conduction type of described counterion is p-type.
The forming method of flash memory the most according to claim 3, it is characterised in that the ginseng of described ion implantation technology
Number includes: the ion of employing is boron ion, and Implantation Energy is 2KeV～4KeV, and implantation dosage is 1E15atom/cm2~
1E16atom/cm2, implant angle is 70 degree～90 degree.
The forming method of flash memory the most according to claim 3, it is characterised in that the ginseng of described ion implantation technology
Number includes: the ion of employing is indium ion, and Implantation Energy is 5KeV～20KeV, and implantation dosage is 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree～90 degree.
The forming method of flash memory the most according to claim 2, it is characterised in that when the conductive-type of described source ion
When type is N-type, the conduction type of described counterion is N-type.
The forming method of flash memory the most according to claim 6, it is characterised in that the ginseng of described ion implantation technology
Number includes: the ion of employing is phosphonium ion, and Implantation Energy is 2KeV～5KeV, and implantation dosage is 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree～90 degree.
The forming method of flash memory the most according to claim 6, it is characterised in that the ginseng of described ion implantation technology
Number includes: the ion of employing is arsenic ion, and Implantation Energy is 3KeV～15KeV, and implantation dosage is 1E14atom/cm2~
1E15atom/cm2, implant angle is 70 degree～90 degree.
The forming method of flash memory the most according to claim 1, it is characterised in that described Semiconductor substrate has word
Line bitline regions and line floating gate region, source, line floating gate region, described source is between adjacent word line bitline regions；Described floating gate structural membrane position
In the Semiconductor substrate of line floating gate region, part source, and the floating gate structural membrane being positioned in the Semiconductor substrate of line floating gate region, source also extends
To the Semiconductor substrate of described wordline bitline regions；Described control gate structural membrane is positioned at Semiconductor substrate and floating gate structural membrane
On；Described dielectric layer covers the control gate structural membrane of wordline bitline regions.
The forming method of flash memory the most according to claim 9, it is characterised in that after forming described source line layer, also
Including: remove dielectric layer and the control gate structural membrane of wordline bitline regions, bottom the first side wall, form control gate structure；?
Described control gate structure and the first side wall sidewall form the 3rd side wall；With described first side wall, source line layer and the 3rd side wall it is
Mask, removes the part floating gate structural membrane of wordline bitline regions, forms floating boom in the bottom of control gate structure and the 3rd side wall
Electrode structure；Word line structure is formed at the 3rd side wall sidewall exposed and floating gate structure side wall.
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| CN109872994A (en) * | 2019-03-07 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN111653568A (en) * | 2020-06-01 | 2020-09-11 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof, DRAM (dynamic random Access memory) and semiconductor chip |
| CN111739892A (en) * | 2020-07-30 | 2020-10-02 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN112242398A (en) * | 2020-11-12 | 2021-01-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing memory |
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| CN109712981B (en) * | 2019-01-02 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
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