CN101625976A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN101625976A CN101625976A CN200810040355A CN200810040355A CN101625976A CN 101625976 A CN101625976 A CN 101625976A CN 200810040355 A CN200810040355 A CN 200810040355A CN 200810040355 A CN200810040355 A CN 200810040355A CN 101625976 A CN101625976 A CN 101625976A
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Abstract
The invention relates to a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is formed with a gate dielectric layer, a gate positioned on the gate dielectric layer, side walls positioned on the gate dielectric layer and the side wall of the gate, and a source electrode and a drain electrode which are positioned on two sides of the gate dielectric layer in the semiconductor substrate; forming ohmic contact areas on the source electrode, the drain electrode and the gate; performing plasma sputtering on the side walls at a temperature of between 200 and 300 DEG C; and washing the side walls by a wet method. The method for manufacturing the semiconductor device can completely remove or oxidize the metal remained on the side walls to avoid generating leakage current between arrays of the semiconductor device.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device.
Background technology
The device architecture of traditional semiconductor memory has gate dielectric 12 and grid 13 as shown in Figure 1 successively on the Semiconductor substrate 11, described gate dielectric 12 is silicon dioxide or silica-silicon-nitride and silicon oxide layer etc., and described grid 13 is a polysilicon layer.In the Semiconductor substrate 11 of gate dielectric 12 both sides, be formed with low doping source drain region 14, the both sides of gate dielectric 12 and grid 13 have side wall 15, described side wall 15 materials are silica etc. for example, is formed with source-drain electrode 16 in the Semiconductor substrate 11 of side wall 15 both sides.17 expressions when carrying out metal line with the interior ohmic contact regions that is connected Metal Contact of contact hole, described ohmic contact zone is metal silicide normally, for example nickle silicide etc.
The manufacture method of described semiconductor memory is: form gate dielectric 12 and grid 13 on Semiconductor substrate 11, be mask with grid 13 subsequently, carrying out ion in the Semiconductor substrate of grid both sides injects, form low doping source drain region 14, subsequently, sidewall at gate dielectric 12 and grid 13 adopts chemical vapour deposition technique to form side wall 15, afterwards, be mask with side wall 15 again, carrying out ion in the Semiconductor substrate of grid both sides injects, form source-drain electrode 16, subsequently, on source-drain electrode 16 and grid 13, form ohmic contact regions 17, subsequently by plasma sputtering technology, interlayer dielectric layer (ILD) can be on described semiconductor device, deposited, and interconnection structure for example connector or dual-damascene structure and the interconnection of described ohmic contact regions can be in interlayer dielectric layer, formed.
Along with size of semiconductor device is further dwindled, in the manufacture craft of described semiconductor device, because the size of side wall is more and more littler, after forming ohmic contact regions by plasma sputtering technology, in the insulating material that constitutes side wall, may produce the residual of described metal, when the several semiconductor device forms memory array, might produce electrical connection between the metal remained on the side wall of adjacent memory, thereby cause the leakage current generating between the adjacent memory.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of semiconductor device, avoids the leakage current that metal remained causes on the side wall of semiconductor device.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device, comprise the steps:
Semiconductor substrate is provided, is formed with gate dielectric and the grid that is positioned on the gate dielectric on the Semiconductor substrate, be positioned at the side wall of gate dielectric and gate lateral wall, be positioned at the source electrode and the drain electrode of the Semiconductor substrate of gate dielectric both sides; On described source electrode and drain electrode and grid, form ohmic contact regions; Under 200～300 ℃ temperature conditions, side wall is carried out plasma sputtering; The described side wall of wet-cleaned.
Optionally, the ion of described plasma sputtering is the oxidizability ion, as oxonium ion.
Optionally, the time of described plasma sputtering is 10～80 seconds.
Optionally, the reagent of described wet-cleaned is 95%～98% sulfuric acid solution.
Optionally, described ohmic contact regions material is a self-aligned metal silicate, and described metal silicide is cobalt silicide or nickle silicide.
Optionally, also be formed with the offset spacers that is positioned at gate dielectric and gate lateral wall and is surrounded on the described Semiconductor substrate, and be source electrode extension area and drain electrode extension area that mask forms in the Semiconductor substrate of gate dielectric both sides with the offset spacers by described side wall.
Compared with prior art, the present invention has the following advantages: the manufacture method of semiconductor device provided by the invention is carried out after the plasma sputtering under 200～300 ℃ temperature conditions, the described side wall of wet-cleaned again, can remove fully or oxide sidewall spacers on metal remained, avoid between array of semiconductor devices, producing leakage current.
Description of drawings
Fig. 1 is the structural representation of prior art semiconductor device;
Fig. 2 to Fig. 7 is each step structural representation of specific embodiment of the invention manufacturing method of semiconductor device;
Fig. 8 is the bridge joint leakage current between the semiconductor device under the specific embodiment of the invention different disposal condition.
Embodiment
The objective of the invention is to remove and form the metal residual that produces on the side wall after the ohmic contact regions, to produce leakage current between the adjacent memory of avoiding memory array by follow-up treatment process.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The invention provides a kind of manufacture method of semiconductor device, comprise the steps: to provide Semiconductor substrate, be formed with gate dielectric and the grid that is positioned on the gate dielectric on the Semiconductor substrate, be positioned at the side wall of gate dielectric and gate lateral wall, be positioned at the source electrode and the drain electrode of the Semiconductor substrate of gate dielectric both sides; On described source electrode and drain electrode and grid, form ohmic contact regions; Under 200～300 ℃ temperature conditions, side wall is carried out plasma sputtering; The described side wall of wet-cleaned.Further, described semiconductor device also comprises the offset spacers that is positioned at gate dielectric and gate lateral wall and is surrounded by described side wall, and is source electrode extension area and drain electrode extension area that mask forms with the offset spacers in the Semiconductor substrate of gate dielectric both sides.
Be elaborated below with reference to accompanying drawing 2 to 7 pairs of concrete technologies of the present invention of accompanying drawing, in the actual process, be on described Semiconductor substrate, to form the several semiconductor device, form the array of semiconductor device, because the structure and the formation method of described semiconductor device are all identical, in order to simplify, one of them semiconductor device unit only draws.
With reference to accompanying drawing 2, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 can be silicon, III-V family or II-VI compound semiconductor or silicon-on-insulator (SOI).Form isolation structure 101 in Semiconductor substrate, described isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Also be formed with the gate channel layer of various traps (well) structure and substrate surface in the described Semiconductor substrate 100.In general, the ion doping conduction type that forms trap (well) structure is identical with gate channel layer ion doping conduction type, and density is low than gate channel layer; The depth bounds that ion injects is wider, need reach the degree of depth greater than isolation structure simultaneously.In order to simplify, only with blank Semiconductor substrate 100 diagrams, should too not limit protection scope of the present invention herein at this.
Then, form gate dielectric layer 102 and grid 103 successively on Semiconductor substrate 100, described gate dielectric layer 102 constitutes grid structure with grid 103.Described gate dielectric layer 102 can be the composite construction of silica (SiO2) or silicon oxynitride (SiNO) or silicon-nitride and silicon oxide-silicon nitride.Gate dielectric layer 102 preferred high-k (high K) materials.Described hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.
In the optional technology, so that protect the edge of grid 103, the material of described offset spacers 104 is silicon nitride for example in polysilicon gate 103 peripheral formation offset spacers (OffsetSpacer) 104, can adopt the method for chemical vapour deposition (CVD) to form.
Forming after the skew side wall, in the preferred embodiment, with reference to accompanying drawing 2, is mask with offset spacers 104, carries out first ion and inject 106, formation source/drain extension region 105 in the Semiconductor substrate 100 of grid structure both sides.The conduction type of described source/drain extension region 105 is N type or P type, and promptly first ion can be any one in phosphonium ion, arsenic ion, boron fluoride ion, boron ion or the indium ion.
The technology of carrying out the injection of first ion is: when described first ion was arsenic ion, ion implantation energy was 2KeV to 5KeV, and ion implantation dosage is 5E14 to 2E15/cm
2When described first ion was phosphonium ion, first ion implantation energy was 1KeV to 4KeV, and ion implantation dosage is 5E14 to 2E15/cm
2
When described first ion was the boron ion, ion implantation energy was 0.5KeV to 2KeV, and ion implantation dosage is 5E14 to 2E15/cm
2When described first ion was the boron fluoride ion, first ion implantation energy was 1KeV to 4KeV, and ion implantation dosage is 5E14 to 2E15/cm
2
Another optional processing step with reference to accompanying drawing 3, carries out second ion and injects 107 in the Semiconductor substrate 100 that grid structure two is surveyed, form the bag shape injection region 108 that surrounds described source/drain extension region; It is that bag shape is injected (Pocket implant) that described second ion injects 107, generally adopts angle to inject between the ion of 0 to 45 degree, forms bag shape injection region.
Between the degree of depth circle Yu Yuan/drain extension region and source/drain electrode of described bag shape injection region 108, and, the conductivity type opposite of the ionic type of second ion and first ion, if first ion is a N type ion, then second ion is a P type ion, if first ion is a P type ion, then second ion is a N type ion.
Among the present invention, for first ion, the injection of second ion does not have strict the qualification in proper order, can carry out first ion earlier and inject, and carries out the injection of second ion again, can carry out second ion at first yet and inject, and carries out first ion again, decides according to the needs of technology.The injection technology of described second ion is a prior art, does not do at this and gives unnecessary details.
With reference to accompanying drawing 5, form side wall 111 in the grid structure both sides, described side wall 111 can be a kind of in silica, silicon nitride, the silicon oxynitride or constituting by them.Optimize execution mode for one as present embodiment, described side wall 111 is formed jointly for silica, silicon nitride, concrete technology is: adopting chemical vapour deposition technique to form first silicon oxide layer, first silicon nitride layer and second silicon oxide layer on the Semiconductor substrate 100 and on the silicon oxide layer 104, adopting etching (etch-back) method to form side wall then.
When described grid structure both sides were formed with the skew side wall, described side wall 111 was positioned at two surveys of skew side wall.
With reference to accompanying drawing 6, in grid structure both sides, Semiconductor substrate 100, carry out the 3rd ion and inject formation source/drain electrode 112.The ionic type of described the 3rd ion is identical with the ionic type of first ion.Subsequently, Semiconductor substrate 100 is annealed, make the various ions diffusion of injection even.
With reference to accompanying drawing 7, on described source electrode and drain electrode and grid, form ohmic contact regions 113, the material of described ohmic contact regions is self-aligned metal silicate (salicide), for example metal silicide of the metal silicide of the metal silicide of the metal silicide of the metal silicide of the metal silicide of cobalt, nickel, molybdenum, titanium, copper or niobium.
The formation technology of the metal silicide of described ohmic contact regions 113 is: under any one plasma atmosphere in containing argon ion and oxonium ion, nitrogen ion, hydrogen ion, splash-proofing sputtering metal for example cobalt, nickel, molybdenum, titanium, copper or niobium forms.
In the technology that forms described ohmic contact regions, owing to adopted the technology of splash-proofing sputtering metal material under the plasma atmosphere, therefore, form after the ohmic contact regions, on clearance wall, may there be the residual of institute's splash-proofing sputtering metal, when this residual meeting causes the several semiconductor device to form array, electrically contact between the adjacent semiconductor device, thereby produce electric leakage.
Residual in order to remove the splash-proofing sputtering metal that produces on the described side wall, those skilled in the art carry out plasma sputtering to side wall under 200～300 ℃ temperature conditions, the ion of described plasma sputtering is the oxidizability ion, as oxonium ion etc., sputtering time is decided according to the residual quantity of splash-proofing sputtering metal, and splash-proofing sputtering metal is for a long time residual, and the time is longer relatively, optionally, the time of described plasma sputtering is 10～80 seconds.Described plasma sputtering technology can remove or oxide sidewall spacers on the metal remained ion, avoid between adjacent semiconductor device, electrically contacting, thus the electric leakage that produces.
Under 200～300 ℃ temperature conditions, side wall is carried out after the plasma sputtering, adopt wet clean process that described side wall is cleaned, with possibility metal remained particulate on the further removal side wall, the reagent of described wet-cleaned is generally the oxidizability strong acid solution, for example 95～98% sulfuric acid solution.
In a specific embodiment of the present invention, under 230 ℃ temperature conditions, adopt the described side wall of oxygen plasma sputter, sputtering time is 20 seconds, afterwards, in 96% sulfuric acid solution, carry out wet-cleaned, last, by bridge joint (BRG) leakage current of measuring adjacent two semiconductor device, find that the semiconductor device that the relative prior art of leakage current is made obviously reduces.
In another specific embodiment of the present invention, under 280 ℃ temperature conditions, adopt the described side wall of oxygen plasma sputter, sputtering time is 30 seconds, afterwards, in 98% sulfuric acid solution, carry out wet-cleaned, last, by bridge joint (BRG) leakage current of measuring adjacent two semiconductor device, find that the semiconductor device that the relative prior art of leakage current is made also obviously reduces.
Adopt the above-mentioned technology of present embodiment to form after the described semiconductor device, can directly on described Semiconductor substrate and semiconductor device, adopt technology formation interlayer dielectric layers such as chemical vapour deposition technique, and in interlayer dielectric layer, form the interconnection structure that electrically contacts with ohmic contact regions, for example connector or dual-damascene structure.
8 be depicted as the bridge joint leakage current between the semiconductor device under the different disposal condition with reference to the accompanying drawings, abscissa in the accompanying drawing is represented the numbering of semiconductor device, provide semiconductor device in the accompanying drawing the 13rd to No. 25, leakage current under the ordinate representation unit grid length, in the accompanying drawing, the the 21st and No. 25 semiconductor device made for the process that adopts prior art, from accompanying drawing as can be seen: the bridge joint leakage current of the 21st and No. 25 semiconductor device is about 5 times of bridge joint leakage current that adopt the semiconductor device that process of the present invention makes.Explanation is after the metal silicide of semiconductor device forms, and through the sputter and the wet clean process of plasma, the leakage current between the semiconductor device has very large improvement.In the present embodiment, the gate pitch of described semiconductor device is about 90nm, and method of the present invention is equally applicable to the semiconductor device of gate pitch less than 90nm.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. the manufacture method of a semiconductor device is characterized in that, comprises the steps:
Semiconductor substrate is provided, is formed with gate dielectric and the grid that is positioned on the gate dielectric on the Semiconductor substrate, be positioned at the side wall of gate dielectric and gate lateral wall, be positioned at the source electrode and the drain electrode of the Semiconductor substrate of gate dielectric both sides;
On described source electrode and drain electrode and grid, form ohmic contact regions;
Under 200～300 ℃ temperature conditions, side wall is carried out plasma sputtering;
The described side wall of wet-cleaned.
2. according to the manufacture method of the described semiconductor device of claim 1, it is characterized in that the reagent of described wet-cleaned is 95%～98% sulfuric acid solution.
3. according to the manufacture method of the described semiconductor device of claim 1, it is characterized in that the ion of described plasma sputtering is the oxidizability ion.
4. according to the manufacture method of the described semiconductor device of claim 3, it is characterized in that described oxidizability ion is an oxonium ion.
5. according to the manufacture method of the described semiconductor device of claim 1, it is characterized in that the time of plasma sputtering is 10～80 seconds.
6. according to the manufacture method of the described semiconductor device of claim 1, it is characterized in that described ohmic contact regions material is a self-aligned metal silicate.
7. according to the manufacture method of the described semiconductor device of claim 6, it is characterized in that described metal silicide is cobalt silicide or nickle silicide.
8. according to the manufacture method of the described semiconductor device of claim 1, it is characterized in that, also be formed with the offset spacers that is positioned at gate dielectric and gate lateral wall and is surrounded on the described Semiconductor substrate, and be source electrode extension area and drain electrode extension area that mask forms in the Semiconductor substrate of gate dielectric both sides with the offset spacers by described side wall.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810040355A CN101625976A (en) | 2008-07-08 | 2008-07-08 | Method for manufacturing semiconductor device |
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| CN200810040355A CN101625976A (en) | 2008-07-08 | 2008-07-08 | Method for manufacturing semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298790A (en) * | 2016-09-18 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN110429034A (en) * | 2019-08-23 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | The method for forming high-pressure trap area |
-
2008
- 2008-07-08 CN CN200810040355A patent/CN101625976A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298790A (en) * | 2016-09-18 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN106298790B (en) * | 2016-09-18 | 2018-11-27 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN110429034A (en) * | 2019-08-23 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | The method for forming high-pressure trap area |
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Application publication date: 20100113 |