CN102024760B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN102024760B CN102024760B CN2009101959787A CN200910195978A CN102024760B CN 102024760 B CN102024760 B CN 102024760B CN 2009101959787 A CN2009101959787 A CN 2009101959787A CN 200910195978 A CN200910195978 A CN 200910195978A CN 102024760 B CN102024760 B CN 102024760B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises: providing a semiconductor substrate, and forming a field effect transistor on the semiconductor substrate; forming a barrier layer on the surface of the field effect transistor; irradiating the barrier layer with ultraviolet rays; forming a stress layer on the surface of the barrier layer; performing thermal annealing on the active region of the field effect transistor; removing the stress layer; forming an etching barrier layer on the surface of the field effect transistor; and forming a metal front medium layer on the surface of the etching barrier layer, making a contact hole in the metal front medium layer and the etching barrier layer, and leading an active interconnection cord out. In the invention, irradiated by the ultraviolet rays, the barrier layer has a compact structure and therefore can reduce or prevent doping ions in the active region from diffusing out and ensure the high insulation performance of the barrier layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacturing approach of the semiconductor device that has adopted the strain memory technique.
Background technology
At semiconductor device, especially in the MOS device, a kind of main method that improves the switching frequency of field-effect transistor is to improve drive current, and the main path that improves drive current is to improve carrier mobility.Existing a kind of technology that improves the field-effect transistor carrier mobility is strain memory technique (StressMemorization Technique; Be called for short SMT); Channel region through at field-effect transistor forms stable stress, improves the carrier mobility in the raceway groove.Usually tensile stress can be so that the molecules align in the channel region be more loose, thereby improves the mobility of electronics, is applicable to nmos pass transistor; And compression stress makes that the molecular arrangement in the channel region is tightr, helps to improve the mobility in hole, is applicable to the PMOS transistor.
Said strain memory technique specifically comprises employing S/D annealing process; Make stressor layers (ActivationCapping Layer; Be called for short ACL) the polysilicon gate crystallization again of bottom, make stress memory that stressor layers brings out in the MOS device, cause the electrical property of MOS device to improve 6%～10%.And to PMOS transistor and nmos pass transistor to the requirement of different stress, can also on the MOS device, carry out optionally local train, reach the purpose of the electrical property that improves the MOS device.
See the paper " Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-performanceStrained-Si Device Application " (coming from 2004 " Symposium on VLSI TechnologyDigest of Technical Papers ") that people such as Chien-Hao Chen deliver; Introduced a kind of production process of semiconductor device of typical strain memory effect, generalized section such as Fig. 1 are to shown in Figure 6.
As shown in Figure 1, the semiconductor-based end 10, at first be provided, on the semiconductor-based end 10, form nmos pass transistor M1 and PMOS transistor M2, and isolated between nmos pass transistor M1 and the PMOS transistor M2 through shallow trench 11.
As shown in Figure 2, form barrier layer 101 on the surface of said nmos pass transistor M1 and PMOS transistor M2, the material on said barrier layer 101 can be SiO
2, can form through chemical vapor deposition method or high-temperature thermal oxidation depositing operation.
As shown in Figure 3, form stressor layers 102 on the surface on said barrier layer 101, the material of said stressor layers 102 can be SiO
2, can through heat drive chemical vapor deposition method (Thermally-Driven CVD, TDCVD) or plasma reinforced chemical vapour deposition technology (Plasma Enhance CVD PECVD) forms.Through changing the parameter of said chemical vapour deposition (CVD), can regulate stress types and stress intensity that 102 pairs of bottom transistor of said stressor layers are brought out.Suppose that said stressor layers 102 provides tensile stress, thereby pair nmos transistor M1 produces beneficial effect.
As shown in Figure 4, use mask to carry out etching, optionally remove the stressor layers 102 on said PMOS transistor M2 surface, and keep the part stressor layers 102 that is positioned at nmos pass transistor M1 surface; Then transistorized grid and source/drain region are carried out thermal annealing.
As shown in Figure 5, remove stressor layers 102, pair nmos transistor M1 and PMOS transistor M2 carry out the rear end silicification technics, form metal silicide layer 103, are used for subsequent technique and form contact hole and draw interconnection line, reduce contact resistance.
As shown in Figure 6, form etching barrier layer 104 on the surface of nmos pass transistor M1 and PMOS transistor M2.The material of said etching barrier layer 104 also can be SiN, can drive chemical vapour deposition (CVD) or plasma reinforced chemical vapour deposition formation through heat.
As shown in Figure 7, form before-metal medium layer 104 on the surface of said etching barrier layer 104.In the subsequent technique, in before-metal medium layer 105, form contact hole 106, draw the active area interconnection line of semiconductor device.
There is following problem in the prior art: because molecules align is relatively loose in the said barrier layer 101; Therefore in carrying out thermal annealing process, the hydrogen ion in the said barrier layer 101 can impel dopant ion (the for example boron ion in the PMOS transistor) in the active area to outdiffusion.Like this, not only make said barrier layer 101, also make the doping content of said barrier layer 101 intermediate ions reduce, influence the performance of MOS transistor because of including the insulating capacity that dopant ion reduces self.Therefore press for and improve the conventional semiconductor device making method, address the above problem.
Summary of the invention
The problem that the present invention solves provides a kind of method, semi-conductor device manufacturing method, can reduce or prevent that dopant ion in the active area is to outdiffusion, to guarantee the electrical property of semiconductor device.
For addressing the above problem, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: the semiconductor-based end is provided, on the said semiconductor-based end, forms field-effect transistor; Surface at said field-effect transistor forms the barrier layer; Utilize ultraviolet ray, shine said barrier layer; Surface on said barrier layer forms stressor layers; Active area to said field-effect transistor carries out thermal annealing; Remove said stressor layers; Form etching barrier layer at said field effect transistor tube-surface; Surface at said etching barrier layer forms before-metal medium layer, in said before-metal medium layer and said etching barrier layer, makes contact hole, leads to the source region interconnection line.
Alternatively, said barrier layer comprises oxide material, forms through chemical vapor deposition method or high-temperature thermal oxidation depositing operation.
Alternatively, said oxide material is SiO
2
Alternatively, the thickness range on said barrier layer be 50
～200
Alternatively, the said technological parameter on the said barrier layer of ultraviolet irradiation that utilizes is: adopting wave-length coverage is the ultraviolet ray of 320nm～400nm, and irradiation temperature is 350 ℃～480 ℃, and irradiation time is 2min～7min.
Alternatively, said stressor layers comprises nitride material, drives chemical vapor deposition method or the formation of plasma enhancing gas-phase deposition through heat.
Alternatively, said nitride material is SiN.
Alternatively,, the active area to said field-effect transistor also comprises the step of optionally removing the stressor layers of field effect transistor tube-surface according to stress types before carrying out thermal annealing.
Alternatively, before said formation etching barrier layer, also comprise and carry out the rear end silicification technics to form the step of metal silicide layer in the surfaces of active regions of said field-effect transistor.
Compared with prior art, the present invention strengthens its compactness through using the said barrier layer of ultraviolet irradiation, thereby can reduce or prevent that dopant ion in the active area to outdiffusion, guaranteeing that said barrier layer can have preferable insulation property.
Description of drawings
Fig. 1 to Fig. 7 is the process for fabrication of semiconductor device sketch map of existing strain memory effect;
Fig. 8 is a method, semi-conductor device manufacturing method flow chart according to the invention;
Fig. 9 to Figure 19 is specific embodiment sketch map of process for fabrication of semiconductor device of strain memory effect according to the invention.
Embodiment
Can know from background technology; Inventor of the present invention finds in process for fabrication of semiconductor device; The barrier layer that includes oxide material that the transistor surface forms; In carrying out thermal annealing process, make dopant ion in the active area spread outward in the barrier layer easily and and then reduce the insulation property on said barrier layer, influence the electrical property of semiconductor device.
Inventor of the present invention creatively finds, can be finer and close through its molecules align after the dielectric layer that includes oxide material being carried out ultraviolet irradiation, improved its density.
Therefore in fabrication of semiconductor device; Be susceptible to and carry out ultraviolet irradiation to the barrier layer of semiconductor device; Make that the institutional framework on said barrier layer is finer and close; And then can reduce or prevent that dopant ion in the active area to outdiffusion, guaranteeing that said barrier layer can have preferable insulation property, makes its accord with expectation.
Below in conjunction with accompanying drawing content of the present invention is elaborated.
Based on above-mentioned consideration, in the following content of embodiment, a kind of method, semi-conductor device manufacturing method is provided, as shown in Figure 8, comprise step:
S101 provides the semiconductor-based end, on the semiconductor-based end, forms field-effect transistor;
S102 forms the barrier layer on the surface of said field-effect transistor;
S103 utilizes ultraviolet ray, shines said barrier layer;
S104 forms stressor layers on the surface on said barrier layer;
S105 optionally removes the stressor layers of field effect transistor tube-surface according to stress types;
S106 carries out thermal annealing to the active area of said field-effect transistor;
S107 removes remaining stressor layers;
S108 carries out the rear end silicification technics and forms metal silicide layer with the surfaces of active regions at said field-effect transistor;
S109 forms etching barrier layer at said field effect transistor tube-surface;
S110 forms before-metal medium layer on the surface of said etching barrier layer, in said before-metal medium layer and said etching barrier layer, makes contact hole, leads to the source region interconnection line.
Below in conjunction with accompanying drawing above-mentioned steps is elaborated.Fig. 9 to Figure 19 is the process schematic representation of a specific embodiment of method, semi-conductor device manufacturing method according to the invention.
At first execution in step S101 provides the semiconductor-based end 20, on the semiconductor-based end, forms field-effect transistor, forms structure as shown in Figure 9.Said field-effect transistor comprises nmos pass transistor M1 and PMOS transistor M2; Isolated between said nmos pass transistor M1 and the PMOS transistor M2 through shallow trench 21; Spacing between the grid of the grid of wherein said nmos pass transistor M1 and PMOS transistor M2 be not less than 1000
for nmos pass transistor, the ion that in Qi Yuan/drain region, mixes can be phosphonium ion or arsenic ion.When the injection ion was arsenic ion, ion implantation energy was 2KeV to 5KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2When the injection ion was phosphonium ion, ion implantation energy was 1KeV to 3KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2And for the PMOS transistor, the ion that in Qi Yuan/drain region, mixes can be boron difluoride ion, boron ion or indium ion.When the injection ion was the boron ion, ion implantation energy was 0.5KeV to 2KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2When the injection ion was the boron difluoride ion, ion implantation energy was 1KeV to 4KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2
Concrete formation technology is identical with prior art, can adopt conventional CMOS technology to make device architecture shown in Figure 9.In the present embodiment; Only to form a nmos pass transistor M1 and a PMOS transistor M2 is an example; Be not that the semiconductor device structure in the manufacturing approach according to the invention is made qualification; Those skilled in the art should spread to manufacturing approach according to the invention and be applied in the process for fabrication of semiconductor device of other structures, explanation hereby.
Then execution in step S102 forms barrier layer 201 on the surface of said nmos pass transistor M1 and PMOS transistor M2, forms structure shown in figure 10.The material on said barrier layer 201 can be SiO
2, and can form through chemical vapor deposition method or high-temperature thermal oxidation method technology.
In the present embodiment, said barrier layer 201 adopts chemical vapor deposition method to form, and material is SiO
2, thickness is not more than 200
Preferable range is 50
～200
Then execution in step S103 utilizes ultraviolet ray, shines said barrier layer 201, and is shown in figure 11.Specifically, in the present embodiment, the employing wave-length coverage is ultraviolet band (the light beam irradiates barrier layer 201 of 100nm～400nm); Preferably; Adopting wave-length coverage is the long wave ultraviolet of 320nm～400nm, and temperature rises to 350 ℃～480 ℃ during irradiation, and irradiation time is 2min～7min.Through said ultraviolet ray said barrier layer 201 is shone; Can be so that the molecules align on said barrier layer 201 be fine and close more; Thereby can reduce or prevent dopant ion (for example phosphonium ion in the nmos pass transistor or arsenic ion in the active area (comprising grid and source/drain region) of said barrier layer 201 under covering; Boron ion or indium ion in the PMOS transistor) to outdiffusion; Avoid the concentration of dopant ion in the said active area to descend, and guaranteed that said barrier layer can have preferable insulation property.
It should be noted that; In practical application; Be protection nmos pass transistor M1 and PMOS transistor M2, especially protection grid is not wherein damaged by ultraviolet irradiation, and the temperature and time of said ultraviolet irradiation can be according to factor such as the formation on said barrier layer 201 and thickness thereof and adjustment in good time.
Then execution in step S104 forms stressor layers 202 on the surface on said barrier layer 201, forms structure shown in figure 12.Said stressor layers 202 can drive chemical vapor deposition method or the formation of plasma reinforced chemical vapour deposition technology through heat.Through changing the parameter of said chemical vapour deposition (CVD), can regulate stress types and stress intensity that 202 pairs of bottom transistor of stressor layers are brought out.
In the present embodiment; The material of said stressor layers 202 is SiN; Adopt plasma reinforced chemical vapour deposition technology to form; Thickness be not less than 400
preferable range be 400
～1000
said stressor layers 202 stress types of being brought out is tensile stress, therefore can improve the carrier mobility of channel region among the nmos pass transistor M1.
Then execution in step S105 optionally removes the stressor layers of field effect transistor tube-surface according to stress types, forms structure shown in figure 13.As stated; In the present embodiment; Because it is tensile stress that stressor layers 202 is brought out stress types; Only pair nmos transistor M1 plays the beneficial effect that improves carrier mobility, and therefore said selective etch is specially: remove the stressor layers 202 on PMOS transistor M2 surface, and keep the part stressor layers 202 that is positioned at nmos pass transistor M1 surface; The parameter of said annealing is: temperature rises to 950 ℃～1100 ℃, annealing time 1.5s～2.5s.
Then execution in step S106 carries out thermal annealing to the active area of said field-effect transistor.Specifically, in the present embodiment, the active area of pair nmos transistor M1 and PMOS transistor M2, promptly thermal annealing is carried out in grid and source/drain region.The stress that said thermal annealing will make stressor layers 202 brought out is remembered to corresponding field-effect transistor, to improve the carrier mobility of channel region.
Then execution in step S107 removes remaining stressor layers 202, forms structure shown in figure 14.In the present embodiment, like Figure 13, the part on the only surplus nmos pass transistor M1 of said stressor layers 202 surface, material is SiN, and also has barrier layer 201 on the surface of nmos pass transistor M1 and PMOS transistor M2, and the material on said barrier layer 201 is SiO
2, therefore can adopt hot phosphoric acid to carry out the selectivity wet etching, remove said stressor layers 202, and utilize said barrier layer 201 to protect the field-effect transistor under it not to be corroded.
Then execution in step S108 removes barrier layer 201, and carries out the rear end silicification technics, and at the active area of nmos pass transistor M1 and PMOS transistor M2, the surface formation metal silicide layer 203 like grid and source/drain region forms structure shown in figure 15.The material of said metal silicide layer 203 can be tungsten silicide WSi
x, can adopt plasma doping to form.
It should be noted that in other embodiments said barrier layer 201 also can reserve part, plays the effect with each surfaces of active regions isolated insulation.
Then execution in step S109 forms etching barrier layer 204 at nmos pass transistor that carries out the rear end silicification technics and the transistorized surface of PMOS, forms structure shown in figure 16.In the present embodiment; Said etching barrier layer 204 also plays the effect of bringing out stress; And stress types is identical with stressor layers 202; Can drive chemical vapor deposition method or plasma through heat and strengthen gas-phase deposition and form, and the technological parameter adjustment etching barrier layer 204 through regulating deposition bring out stress types and stress intensity.
In the present embodiment; The material of said etching barrier layer 204 is SiN; Form through plasma reinforced chemical vapour deposition; Thickness be not less than 300
preferable range be 300
～800
make keep between the grid of nmos pass transistor M1 and PMOS transistor M2 150
～300
spacing, bringing out stress types is tensile stress.
Execution in step S110 forms before-metal medium layer 205 on the surface of said etching barrier layer 204, forms structure shown in figure 17.
In the present embodiment, the material of said before-metal medium layer 205 can be SiO
2Can drive chemical vapor deposition method or the formation of plasma enhancing gas-phase deposition through heat; Owing to kept enough spacings between the grid of nmos pass transistor M1 and PMOS transistor M2; Therefore further reduced interstitial possibility between the grid of nmos pass transistor M1 and PMOS transistor M2, the thickness range of said before-metal medium layer 205 is 2000
～3000
Then continue execution in step S110, the said before-metal medium layer 205 of etching forms contact hole 206 until exposing etching barrier layer 204, and said contact hole 206 is aimed at the metal silicide layer 203 of each surfaces of active regions, forms structure shown in figure 18.
Further, the etching barrier layer 204 of etching contact hole 206 bottoms is filled interconnecting metal then until exposing metal silicide layer 203 in contact hole 206, forms interconnection line., form structure shown in figure 19.
In the present embodiment, said etching barrier layer 204 is SiN, and said before-metal medium layer 205 is SiO
2So, adopting the etching barrier layer 204 of hot phosphoric acid etching contact hole 206 bottoms, said interconnection line material can be Cu or Al, can or electroplate with chemical vapour deposition (CVD) to form.
In the above-described embodiments; Only form tensile stress with the semiconductor device surface at the strain memory effect, carrier mobility is that example describes among the raising nmos pass transistor M1, but not as limit; In other embodiments; Form compression stress if desired to improve carrier mobility among the PMOS transistor M2, the stress types that its manufacturing process only need change stressor layers 202 and etching barrier layer 204 gets final product, and concrete manufacturing process is similar; Those skilled in the art of the present invention should push away easily, repeat no more here.
Further; The manufacturing process of above-mentioned different stress types is combined, field-effect transistors dissimilar on the semiconductor device is carried out local strain memory processing procedure, and then carry out the rear end silicification technics; Make interconnection line, just can promote the overall performance electrical performance of semiconductor device.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. a method, semi-conductor device manufacturing method is characterized in that, comprising:
The semiconductor-based end, be provided, on the said semiconductor-based end, form field-effect transistor;
Surface at said field-effect transistor forms the barrier layer;
Utilize ultraviolet ray, shine said barrier layer;
Surface on said barrier layer forms stressor layers;
Active area to said field-effect transistor carries out thermal annealing;
Remove said stressor layers;
Carry out the rear end silicification technics and form metal silicide layer with surfaces of active regions at field-effect transistor;
Form etching barrier layer at said field effect transistor tube-surface;
Surface at said etching barrier layer forms before-metal medium layer, in said before-metal medium layer and said etching barrier layer, makes contact hole, leads to the source region interconnection line.
2. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that said barrier layer comprises oxide material, forms through chemical vapor deposition method or high-temperature thermal oxidation depositing operation.
3. method, semi-conductor device manufacturing method as claimed in claim 2 is characterized in that, said oxide material is SiO
2
4. according to claim 1 or claim 2 method, semi-conductor device manufacturing method; It is characterized in that the thickness range on said barrier layer is
5. method, semi-conductor device manufacturing method as claimed in claim 1; It is characterized in that; The said technological parameter on the said barrier layer of ultraviolet irradiation that utilizes is: adopting wave-length coverage is the ultraviolet ray of 320nm ~ 400nm, and irradiation temperature is 350 ° of C ~ 480 ° C, and irradiation time is 2min ~ 7min.
6. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that said stressor layers comprises nitride material, drives chemical vapor deposition method or the formation of plasma enhancing gas-phase deposition through heat.
7. method, semi-conductor device manufacturing method as claimed in claim 6 is characterized in that, said nitride material is SiN.
8. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, before the active area to said field-effect transistor carries out thermal annealing, also comprises the step of optionally removing the stressor layers of field effect transistor tube-surface according to stress types.
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|---|---|---|---|
| CN2009101959787A CN102024760B (en) | 2009-09-18 | 2009-09-18 | Method for manufacturing semiconductor device |
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| CN102024760B true CN102024760B (en) | 2012-10-31 |
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| CN102420119B (en) * | 2011-04-29 | 2013-06-26 | 上海华力微电子有限公司 | Gate polysilicon etching method for enhancing stress memorization technique |
| CN103378003A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS device by means of stress memorization technique |
| CN103928306B (en) * | 2013-01-10 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | The forming method of dual metal gate structure and CMOS transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080044967A1 (en) * | 2006-08-19 | 2008-02-21 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system having strained transistor |
| CN101320711A (en) * | 2007-06-05 | 2008-12-10 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and preparation thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080044967A1 (en) * | 2006-08-19 | 2008-02-21 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system having strained transistor |
| CN101320711A (en) * | 2007-06-05 | 2008-12-10 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and preparation thereof |
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| JP特开2008-147325A 2008.06.26 |
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Effective date of registration: 20121115 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |