CN101989574B - Method for manufacturing semiconductor device with strain memory action - Google Patents
Method for manufacturing semiconductor device with strain memory action Download PDFInfo
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- CN101989574B CN101989574B CN2009100560233A CN200910056023A CN101989574B CN 101989574 B CN101989574 B CN 101989574B CN 2009100560233 A CN2009100560233 A CN 2009100560233A CN 200910056023 A CN200910056023 A CN 200910056023A CN 101989574 B CN101989574 B CN 101989574B
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Abstract
The invention relates to a method for manufacturing a semiconductor device with strain memory action, which comprises the following steps of: providing a semiconductor substrate, and forming a field effect transistor on the semiconductor substrate; forming an irradiation barrier layer on the surface of the field effect transistor; forming a stress top covering layer on the surface of the irradiation barrier layer, and irradiating the stress top covering layer by using ultraviolet rays; thermally annealing an active region of the field effect transistor; removing the stress top covering layer; forming an etching barrier layer on the surface of the field effect transistor, wherein the etching barrier layer has the same induced stress type to the stress top covering layer; forming a metal former dielectric layer on the surface of the etching barrier layer, and manufacturing contact holes in the metal former dielectric layer and the etching barrier layer so as to lead out an interconnecting wire of the active region. The stress inducing effect of the stress top covering layer is enhanced through ultraviolet irradiation, and the thickness of the etching barrier layer is properly reduced. The electrical properties of the semiconductor device are maintained, and meanwhile, the problem that a gap is easy to form between adjacent grid electrodes is solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacturing approach of the semiconductor device that has adopted the strain memory technique.
Background technology
In semiconductor device especially MOS device, a kind of main method that improves the switching frequency of field-effect transistor is to improve drive current, and the main path of raising drive current is to improve carrier mobility.Existing a kind of technology that improves the field-effect transistor carrier mobility is strain memory technique (StressMemorization Technique; Be called for short SMT); Channel region through at field-effect transistor forms stable stress, improves the carrier mobility in the raceway groove.Usually tensile stress can be so that the molecules align in the channel region be more loose, thereby improves the mobility of electronics, is applicable to nmos pass transistor; And compression stress makes that the molecular arrangement in the channel region is tightr, helps to improve the mobility in hole, is applicable to the PMOS transistor.
Said strain memory technique SMT specifically comprises employing S/D annealing process; Make stress cap layer (Activation Capping Layer; Abbreviation ACL) the polysilicon gate crystallization again of bottom; Make the stress that stress cap layer ACL is brought out, remember in the MOS device, cause the electrical property of MOS device to improve 6～10%.And to PMOS transistor and nmos pass transistor to the requirement of different stress, can also on the MOS device, carry out optionally local train, reach the purpose of the electrical property that improves the MOS device.
See the paper " Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-performanceStrained-Si Device Application " (coming from 2004 " Symposium on VLSI TechnologyDigest of Technical Papers ") that people such as Chien-Hao Chen deliver; Introduced a kind of production process of semiconductor device of typical strain memory effect, generalized section such as Fig. 1 are to shown in Figure 6.
As shown in Figure 1, the semiconductor-based end 10, at first be provided, on the semiconductor-based end 10, form nmos pass transistor N1 and PMOS transistor N2, and isolated between nmos pass transistor N1 and the PMOS transistor N2 through shallow trench 11.
As shown in Figure 2; Surface at said nmos pass transistor N1 and PMOS transistor N2 forms stress cap layer 101; The material of said stress cap layer 101 can be SiN, can drive chemical vapour deposition (CVD) (TDCVD) or plasma reinforced chemical vapour deposition (PECVD) formation through heat.Through changing the parameter of said chemical vapour deposition (CVD), can regulate stress types and stress intensity that 101 pairs of bottom transistor of stress cap layer are brought out.Suppose that said stress cap layer 101 provides tensile stress, thereby pair nmos transistor N1 produces useful influence.
As shown in Figure 3, use mask to carry out etching, optionally remove the stress cap layer 101 on said PMOS transistor N2 surface, and keep the part stress cap layer 101 that is positioned at nmos pass transistor N1 surface; Then transistorized grid and source, drain region are carried out thermal annealing.
In above-mentioned annealing process; Since only there is nmos pass transistor N1 surface to have stress cap layer 101, after therefore annealing, the tensile stress that stress cap layer 101 is brought out; To be retained among the nmos pass transistor N1, thereby improve the carrier mobility of nmos pass transistor N1 channel region.
As shown in Figure 4, remove stress cap layer 101, pair nmos transistor N1 and PMOS transistor N2 carry out the rear end silicification technics, form metal silicide layer 201, are used for subsequent technique and form contact hole and draw interconnection line, reduce contact resistance.
As shown in Figure 5, form etching barrier layer 102 on the surface of nmos pass transistor N1 and PMOS transistor N2.The material of said etching barrier layer 102 also can be SiN, can through heat drive chemical vapour deposition (CVD) (Thermally-Driven CVD, TDCVD) or plasma reinforced chemical vapour deposition (PlasmaEnhance CVD PECVD) forms.Except playing the effect that etching stops in the process that forms contact hole at subsequent technique, also play the effect of bringing out transistor stress on the other hand.The stress types of said etching barrier layer 102 is identical with stress cap layer 101, makes the stress effect that produces superpose, and further improves the electrical property of device.
As shown in Figure 6, form before-metal medium layer 202 on the surface of said etching barrier layer 102.In the subsequent technique, in before-metal medium layer 202, form contact hole 203, draw the active area interconnection line of semiconductor device.
There is following problem in the prior art: if the thickness of etching barrier layer 102 is blocked up; Can make that the depth-to-width ratio in gap becomes big between the grid of adjacent transistor; Cause when etching barrier layer 102 surface deposition before-metal medium layers 202, the space is formed on the bottom between the grid of adjacent transistor easily.Therefore in order to guarantee yields, the thickness of said etching barrier layer 102 should be as far as possible little, yet the thickness of simple attenuate etching barrier layer 102 can directly weaken the stress effect of being brought out on the respective fields effect transistor, causes the electrical property of semiconductor device to descend.Therefore press for the method, semi-conductor device manufacturing method that improves existing strain memory effect, address the above problem.
Summary of the invention
The problem that the present invention solves provides a kind of method, semi-conductor device manufacturing method of strain memory effect; Can be when the plated metal front medium layer; Avoid that the space is formed on the bottom between the grid of adjacent transistor; On the other hand transistor is produced good stress effect, to guarantee the electrical property of semiconductor device.
For addressing the above problem, the invention provides a kind of method, semi-conductor device manufacturing method of strain memory effect, comprising:
The semiconductor-based end, be provided, on the semiconductor-based end, form field-effect transistor;
Form the irradiation barrier layer on the surface of said field-effect transistor;
Surface on said irradiation barrier layer forms the stress cap layer, and uses the said stress cap layer of ultraviolet irradiation;
Active area to said field-effect transistor carries out thermal annealing;
Remove said stress cap layer;
Form etching barrier layer on field-effect transistor surface, said etching barrier layer to bring out stress types identical with the stress cap layer;
Surface at etching barrier layer forms before-metal medium layer, in said before-metal medium layer and etching barrier layer, makes contact hole, leads to the source region interconnection line.
As possibility, said between the grid of opposite field effect transistor at the semiconductor-based end spacing be not less than
As possibility, the material on said irradiation barrier layer is SiO
2, forming through chemical vapour deposition (CVD) or high-temperature thermal oxidation deposition, thickness is not more than
Concrete scope does
As possibility; The material of said stress cap layer is SiN; Drive chemical vapour deposition (CVD) or plasma enhancing vapour deposition formation through heat, thickness is not less than
, and specifically scope is
As possibility; The technological parameter of said use ultraviolet irradiation stress cap layer is: adopting wave-length coverage is the ultraviolet ray of 320～400nm; Temperature rises to 350-480C during irradiation, irradiation 2-7min, and the stress intensity that brings out of stress cap layer is 1.2GPa～1.7GPa.
As possibility, before said thermal annealing, also comprise step according to the stress cap layer of stress types selective removal field effect transistor tube-surface.
As possibility, before said formation etching barrier layer, also comprise the step of carrying out the rear end silicification technics, at the surfaces of active regions formation metal silicide layer of field-effect transistor.
As possibility; The material of said etching barrier layer is SiN; Drive chemical vapour deposition (CVD) or plasma enhancing vapour deposition formation through heat, thickness is not less than
, and concrete scope is 1.0GPa～1.7GPa for
brings out stress intensity;
As possibility; After the field-effect transistor surface formed etching barrier layer, the spacing that is kept between the grid of adjacent transistor was
As possibility, the material of said before-metal medium layer is SiO
2, driving chemical vapour deposition (CVD) or plasma enhancing vapour deposition formation through heat, thickness range does
Compared with prior art, the present invention brings out the effect of stress through using ultraviolet irradiation stress cap layer to strengthen it, thus the suitable thickness of attenuate etching barrier layer.On the one hand can keep the semiconductor device good electrical properties, easy interstitial problem when having solved between the transistorized neighboring gates plated metal front medium layer on the other hand.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purposes, characteristic and advantage of the present invention will be more clear.The parts identical with prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size of layer with the zone.
Fig. 1 to Fig. 6 is the process for fabrication of semiconductor device sketch map of existing strain memory effect;
Fig. 7 is the method, semi-conductor device manufacturing method flow chart of strain memory effect according to the invention;
Fig. 8 to Figure 18 is specific embodiment sketch map of process for fabrication of semiconductor device of strain memory effect according to the invention.
Embodiment
Can know from background technology, in the process for fabrication of semiconductor device of strain memory effect,, when plated metal front medium layer PMD, make that easily the space is formed on the bottom between the grid of adjacent transistor if transistor surface forms blocked up etching barrier layer; And only the attenuate etching barrier layer causes the surface to bring out stress decrease, can influence the electrical property of semiconductor device again.The present invention in the said etching barrier layer of attenuate as far as possible, the stress effect that provides in the continuous strain memory processing procedure before having improved, thus the balance semiconductor device is because the electrical property loss that the attenuate etching barrier layer is brought.
As shown in Figure 7, the method, semi-conductor device manufacturing method of strain memory effect according to the invention, basic procedure comprises:
S1, be provided the semiconductor-based end, on the semiconductor-based end, form field-effect transistor.Said field-effect transistor comprises nmos pass transistor and PMOS transistor, and is isolated through shallow trench between the two.
S2, form the irradiation barrier layer on the surface of said field-effect transistor.The material on said irradiation barrier layer can be SiO
2, can form through chemical vapour deposition (CVD) CVD or high-temperature thermal oxidation deposition.
S3, at the surface deposition stress cap layer on said irradiation barrier layer.Said stress cap layer ACL material can be SiN; Can drive chemical vapour deposition (CVD) TDCVD or plasma through heat and strengthen vapour deposition PECVD and form, and the technological parameter adjustment stress cap layer through regulating deposition bring out stress types and stress intensity.
S4, the said stress cap layer of use ultraviolet irradiation strengthen the effect that the stress cap layer brings out stress.
S5, to the active area of said field-effect transistor, carry out thermal annealing like zones such as grid and source, leakages.
As possibility; Before annealing, also comprise step according to the stress cap layer of stress types selective removal field effect transistor tube-surface; For example: if the stress types that the stress cap layer brings out is a tensile stress; Need to remove the part that the stress cap layer is positioned at PMOS transistor surface, and keep the part that is positioned at the nmos pass transistor surface; If the stress types that the stress cap layer brings out is a compression stress, then need removes the part that the stress cap layer is positioned at the nmos pass transistor surface, and keep the part that is positioned at PMOS transistor surface.
S6, removing said stress cap layer, and carry out the rear end silicification technics, is that the surface in grid and source, drain region forms metal silicide layer at the active area of field-effect transistor.
S7, form etching barrier layer CESL at the field effect transistor tube-surface that is carrying out the rear end silicification technics; Said etching barrier layer CESL to bring out stress types identical with the stress cap layer; Material can be SiN; Thinner thickness; Make enough spacings of reservation between the field-effect transistor neighboring gates, can drive chemical vapour deposition (CVD) TDCVD or plasma through heat and strengthen vapour deposition PECVD and form, and the technological parameter adjustment etching barrier layer CESL through regulating deposition bring out stress types and stress intensity.
S8, form before-metal medium layer PMD on the surface of said etching barrier layer CESL; In before-metal medium layer PMD, form contact hole then, draw the active area interconnection line of field-effect transistor.As possibility, the material of said before-metal medium layer PMD can be SiO
2, can drive chemical vapour deposition (CVD) TDCVD or plasma reinforced chemical vapour deposition PECVD forms through heat, when further reducing deposition between the grid of field-effect transistor the interstitial possibility in bottom.
Compared with prior art, in the above-mentioned manufacturing approach, through ultraviolet irradiation stress cap layer ACL, strengthen the effect bring out stress, the stress that makes annealing back field-effect transistor remember increases, thus the suitable thickness of attenuate etching barrier layer CESL.Therefore the semiconductor device of strain memory effect provided by the present invention can keep good electrical properties on the one hand, easy interstitial problem when solving between the grid of field-effect transistor the plated metal front medium layer on the other hand.
Below in conjunction with specific embodiment, the present invention is done further introduction.Fig. 8 to Figure 18 is the process schematic representation of a specific embodiment of method, semi-conductor device manufacturing method of strain memory effect according to the invention.
As shown in Figure 8; The semiconductor-based end 10, be provided; Form nmos pass transistor and N1 and PMOS transistor N2 at the semiconductor-based end 10; Isolated through shallow trench 11 between said nmos pass transistor N1 and the PMOS transistor N2, wherein spacing is not less than
between the grid
Concrete formation technology is identical with prior art, can adopt conventional CMOS technology to make device architecture shown in Figure 8.In the present embodiment; Only to form a nmos pass transistor N1 and a PMOS transistor N2 is an example; Be not that the semiconductor device structure in the manufacturing approach according to the invention is made qualification; Those skilled in the art should spread to manufacturing approach according to the invention and be applied in the process for fabrication of semiconductor device of other structures, explanation hereby.
As shown in Figure 9, form irradiation barrier layer 200 on the surface of said nmos pass transistor N1 and PMOS transistor N2.The material on said irradiation barrier layer 200 can be SiO
2, can form through chemical vapour deposition (CVD) or high-temperature thermal oxidation method.
In the present embodiment, said irradiation barrier layer 200 adopts chemical vapour deposition (CVD) CVD to form, and material is SiO
2, thickness is not more than
Preferable range does
Shown in figure 10, form stress cap layer 101 on the surface on said irradiation barrier layer 200, said stress cap layer 101 can drive chemical vapour deposition (CVD) (TDCVD) or plasma reinforced chemical vapour deposition (PECVD) formation through heat.Through changing the parameter of said chemical vapour deposition (CVD), can regulate stress types and stress intensity that 101 pairs of bottom transistor of stress cap layer are brought out.
In the present embodiment; The material of said stress cap layer 101 is SiN; Adopt plasma reinforced chemical vapour deposition (PECVD) to form; It is tensile stress that thickness is not less than the stress types that
preferable range brought out for
stress cap layer 101, therefore can improve the carrier mobility of channel region among the nmos pass transistor N1.
Shown in figure 11, use the said stress cap layer 101 of ultraviolet irradiation (being UV Cure Process), strengthen the stress of bringing out of stress cap layer 101.
In the present embodiment; Adopting wave-length coverage is the light beam irradiates stress cap layer 101 of ultraviolet band; Preferably, adopting wave-length coverage is the ultraviolet ray of 320～400nm, and temperature rises to 350-480C during irradiation; Irradiation 2-7min makes the stress that brings out of said stress cap layer 101 reach 1.2GPa～1.7GPa.And nmos pass transistor N1 and PMOS transistor N2 can be protected in said irradiation barrier layer 200, especially protect grid not damaged by ultraviolet irradiation.
Shown in figure 12, use mask that said stress cap layer 101 is carried out selective etch, the active area of pair nmos transistor N1 and PMOS transistor N2 then, promptly thermal annealing is carried out in zones such as grid and source, leakage.The stress that said thermal annealing will make stress cap layer 101 brought out is remembered to corresponding field-effect transistor, to improve the carrier mobility of channel region.
In the present embodiment; Because it is tensile stress that stress cap layer 101 brings out stress types; Only pair nmos transistor N1 plays the beneficial effect that improves carrier mobility; Therefore said selective etch is specially: remove the stress cap layer 101 on PMOS transistor N2 surface, and keep the part stress cap layer 101 that is positioned at nmos pass transistor N1 surface; The parameter of said annealing is: temperature rises to 950-1100C, annealing time 1.5s-2.5s.
Shown in figure 13, remove remaining stress cap layer 101.In the present embodiment, the part on the only surplus nmos pass transistor N1 of said stress cap layer 101 surface, material is SiN, and also has irradiation barrier layer 200 on the surface of field-effect transistor, and the material on said irradiation barrier layer 200 is SiO
2, therefore can adopt hot phosphoric acid to carry out the selectivity wet etching, remove stress cap layer 101, irradiation barrier layer 200 protection field-effect transistors are not corroded.
Shown in figure 14, remove irradiation barrier layer 200, and carry out the rear end silicification technics, at the active area of nmos pass transistor N1 and PMOS transistor N2, form metal silicide layer 201 like the surface in grid and source, drain region.
As possibility, said irradiation barrier layer 200 also can reserve part, plays the effect with each surfaces of active regions isolated insulation; Said metal silicide layer 201 materials can be tungsten silicide WSi
x, can adopt plasma doping to form.
Shown in figure 15, form etching barrier layer 102 at nmos pass transistor that carries out the rear end silicification technics and the transistorized surface of PMOS.Said etching barrier layer 102 also plays the effect of bringing out stress; And stress types is identical with stress cap layer 101; Can drive chemical vapour deposition (CVD) TDCVD or plasma through heat and strengthen vapour deposition PECVD and form, and the technological parameter adjustment etching barrier layer 102 through regulating deposition bring out stress types and stress intensity.
In the present embodiment; The material of said etching barrier layer 102 is SiN; Form through plasma reinforced chemical vapour deposition PECVD; Thickness is not less than
preferable range makes reservation
between the grid of nmos pass transistor N1 and PMOS transistor N2 for
spacing; Bringing out stress types is tensile stress, and stress intensity is about 1.0-1.7GPa.
Shown in figure 16, form before-metal medium layer 202 on the surface of said etching barrier layer 102.
In the present embodiment, the material of said before-metal medium layer 202 can be SiO
2Can drive chemical vapour deposition (CVD) TDCVD or plasma enhancing vapour deposition PECVD formation through heat; Owing to kept enough spacings between the grid of nmos pass transistor N1 and PMOS transistor N2; Therefore further reduced interstitial possibility between the grid of nmos pass transistor N1 and PMOS transistor N2, the thickness range of said before-metal medium layer 202 does
Shown in figure 17, the said before-metal medium layer 202 of etching forms contact hole 203 until exposing etching barrier layer 102, and said contact hole 203 is aimed at the metal silicide layer 201 of each surfaces of active regions.
Shown in figure 18, the etching barrier layer 102 of etching contact hole 203 bottoms is filled interconnecting metal then until exposing metal silicide layer 201 in contact hole 203, forms interconnection line.
In the present embodiment, said etching barrier layer 102 is SiN, and before-metal medium layer 202 is SiO
2So, adopting the etching barrier layer 102 of hot phosphoric acid etching contact hole 203 bottoms, said interconnection line material can be Cu or Al, can or electroplate with chemical vapour deposition (CVD) to form.
The foregoing description only forms tensile stress with the semiconductor device surface at the strain memory effect, and carrier mobility is an example among the raising nmos pass transistor N1; Form compression stress if desired to improve carrier mobility among the PMOS transistor N2; The stress types that its manufacturing process only need change stress cap layer 101 and etching barrier layer 102 gets final product; Concrete manufacturing process is similar; Those skilled in the art of the present invention should push away easily, repeat no more here.
Further; The manufacturing process of above-mentioned different stress types is combined, field-effect transistors dissimilar on the semiconductor device is carried out local strain memory processing procedure, and then carry out the rear end silicification technics; Make interconnection line, just can promote the overall performance electrical performance of semiconductor device.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. the method, semi-conductor device manufacturing method of a strain memory effect is characterized in that, comprising:
The semiconductor-based end, be provided, on the semiconductor-based end, form field-effect transistor;
Form the irradiation barrier layer on the surface of said field-effect transistor;
Surface on said irradiation barrier layer forms the stress cap layer; And the said stress cap layer of use ultraviolet irradiation; The technological parameter of said use ultraviolet irradiation stress cap layer is: adopting wave-length coverage is the ultraviolet ray of 320 ~ 400nm; Temperature rises to 350-480 ℃ during irradiation, irradiation 2-7min, and the stress intensity that brings out of stress cap layer is 1.2GPa ~ 1.7GPa;
Use after the said stress cap layer of ultraviolet irradiation, according to the stress cap layer of stress types selective removal field effect transistor tube-surface;
Active area to said field-effect transistor carries out thermal annealing;
Remove remaining said stress cap layer;
Form etching barrier layer on field-effect transistor surface, said etching barrier layer to bring out stress types identical with the stress cap layer;
Surface at etching barrier layer forms before-metal medium layer, in said before-metal medium layer and etching barrier layer, makes contact hole, leads to the source region interconnection line.
2. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 1; It is characterized in that;, spacing is not less than
between the grid of opposite field effect transistor at said the semiconductor-based end
3. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 1 is characterized in that,
The material on said irradiation barrier layer is SiO
2, forming through chemical vapour deposition (CVD) or high-temperature thermal oxidation deposition, thickness is not more than
4. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 3; It is characterized in that the thickness range on irradiation barrier layer is
5. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 1; It is characterized in that; The material of said stress cap layer is SiN; Drive chemical vapour deposition (CVD) through heat and form, thickness is not less than
6. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 5, the thickness range that it is characterized in that said stress cap layer is
7. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 1 is characterized in that, before said formation etching barrier layer, also comprises the step of carrying out the rear end silicification technics, at the surfaces of active regions formation metal silicide layer of field-effect transistor.
8. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 1; It is characterized in that; The material of said etching barrier layer is SiN; Drive chemical vapour deposition (CVD) through heat and form, thickness is not less than
to bring out stress intensity be 1.0GPa ~ 1.7GPa.
9. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 8; It is characterized in that the thickness range of said etching barrier layer is
10. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 7 is characterized in that,
After the field-effect transistor surface formed etching barrier layer, the spacing that is kept between the grid of adjacent transistor was
11. the method, semi-conductor device manufacturing method of strain memory effect as claimed in claim 8 is characterized in that, the material of said before-metal medium layer is SiO
2, driving chemical vapour deposition (CVD) or plasma reinforced chemical vapour deposition formation through heat, thickness range does
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| CN104465517B (en) * | 2013-09-23 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN104733389B (en) * | 2013-12-20 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
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| CN1877834A (en) * | 2005-06-08 | 2006-12-13 | 三星电子株式会社 | Semiconductor integrated circuit device and method for fabricating the same |
| CN101197324A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | CMOS device and method for forming its stress film |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1877834A (en) * | 2005-06-08 | 2006-12-13 | 三星电子株式会社 | Semiconductor integrated circuit device and method for fabricating the same |
| CN101197324A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | CMOS device and method for forming its stress film |
| CN101266949A (en) * | 2007-03-16 | 2008-09-17 | 联华电子股份有限公司 | Method for making strain silicon CMOS transistor |
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