CN102054776A - Method for manufacturing stress memorization effect semiconductor device - Google Patents
Method for manufacturing stress memorization effect semiconductor device Download PDFInfo
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- CN102054776A CN102054776A CN2009101978152A CN200910197815A CN102054776A CN 102054776 A CN102054776 A CN 102054776A CN 2009101978152 A CN2009101978152 A CN 2009101978152A CN 200910197815 A CN200910197815 A CN 200910197815A CN 102054776 A CN102054776 A CN 102054776A
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Abstract
The invention relates to a method for manufacturing a stress memorization effect semiconductor device. The method comprises the following steps of: providing a semiconductor substrate and forming a transistor on the semiconductor substrate; depositing a stress transfer layer on the surface of the transistor; depositing a stress layer on the surface of the stress transfer layer; performing thermal annealing on an active area of the transistor; removing the stress layer; and manufacturing an interconnection structure. Compared with the prior art, the deposition of the stress layer is carried out under the condition of the temperature of 350 to 450 DEG C and the power of 50 to 150 W. By the method, the stress of the stress layer subjected to the thermal annealing is much greater than the stress of the stress layer subjected to the deposition, and is improved to more than 1.5 GPa. The great improvement on the stress of the stress layer can enable the source and the drain of the transistor to memorize a larger pressure to enhance the mobility, increase the guide current and enhance the response speed of the device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of manufacture method that has adopted the semiconductor device of stress memory technique.
Background technology
Along with semiconductor technology enters the sub-micron epoch, the drive current of MOS device promotes problem and obtains day by day paying attention to, and the lifting of drive current will improve the time of delay (time delay) of element, the speed of response of raising element greatly.
Control stress and be the mutual conductance (perhaps reducing serial resistance) that improves carrier mobility in MOS device, the especially field-effect transistor and increase the MOS device, and then improve the effective means of drive current.
When stress is applied to the raceway groove of semiconductor transistor, the mobility of charge carrier rate changes from their original values under unstressed semiconductor context, thereby transistorized mutual conductance and conducting electric current also change from their original values under unstressed semiconductor context.This is because the stress that applies in raceway groove and the effective mass that can influence bandgap structure (that is, destroying the degeneracy of band structure) and change charge carrier the stress that semiconductor structure produces.For nmos pass transistor, be subjected to along the tensile stress of channel direction (being the moving direction in hole or the direction that drain electrode is connected to source electrode), can be so that the molecules align in the channel region be more loose, thus improve the mobility of electronics; Otherwise, for the PMOS transistor, being subjected to compression stress along channel direction, the molecular arrangement that can get in the channel region is tightr, helps to improve the mobility in hole.
In the prior art, the method that semiconductor transistor is exerted pressure mainly contains two kinds, and a kind of is " overall stress ", and another kind is " local stress ".
" overall stress " produces, is applied to the stress in whole transistor device zone from substrate, for example is that the structure by sige-on-insulator structure, SiGe Stress Release resilient coating or SiC Stress Release resilient coating and so on produces." local stress " is the stress that only is applied to the regional area of contiguous raceway groove from partial structurtes, and the method that applies local stress comprises " stress memory technique (Stress Memorization Technique is called for short SMT) ".
The typical process method of stress memory technique is: at first, stressor layers is deposited on the semiconductor device (for example, field-effect transistor) that will be applied in tension stress; Secondly, carry out thermal annealing, during thermal annealing, the stress that stressor layers has himself is applied to following semiconductor device, and after thermal annealing, the stress that is applied on the semiconductor device is frozen, perhaps by " memory ", so this technology is called stress memory technique; Then, remove stressor layers, this moment, semiconductor device still kept the stress remembered.The common used material of described stressor layers is a nitride film, and for example, silicon nitride is that a kind of good tension stress produces film, and Refractory Metal Nitride is good compression generation film.
In the prior art, the tension stress that the silicon nitride stressor layers can cause is generally below 1.2GPa, this area engineer attempts to make great efforts to adjust production technology from all angles, to promote the tension stress that the silicon nitride stressor layers is caused, for example publication number is the Chinese patent application " manufacture method of silicon nitride layer and the manufacture method of semiconductor element " of CN1949464A, by adopting the pressure below atmospheric pressure environment, silicon nitride layer is carried out UV-irradiation handle, the tension stress that the silicon nitride stressor layers can be caused is promoted to 1.6GPa.The present invention by the adjustment to production technology, promotes the tension stress that stressor layers caused from other angle.
Summary of the invention
Technical problem to be solved by this invention is to improve the manufacture method of stress memory effect semiconductor device to promote the tension stress that stressor layers was caused.
For achieving the above object, the technical solution adopted in the present invention is: a kind of manufacture method of stress memory effect semiconductor device, comprise the steps: to provide the semiconductor-based end, and on the described semiconductor-based end, form transistor; At described transistorized surface deposition Stress Transfer layer; Surface deposition stressor layers at described Stress Transfer layer; Described transistorized active area is carried out thermal annealing; Remove stressor layers; Make interconnection structure.With prior art difference be that described deposition stressor layers is carried out under the condition of power 50～150W 350～450 ℃ of temperature.
Optionally, the material of described Stress Transfer layer is SiO
2Or the SiO that mixes
2
Optionally, the material of described stressor layers is a silicon nitride.
Optionally, described transistor comprises nmos pass transistor and PMOS transistor, and described stressor layers is a tension stress layer, after the surface deposition stressor layers of described Stress Transfer layer, also comprises the step of the stressor layers on the selective removal PMOS transistor.
Optionally, described deposition stressor layers is for adopting the mode of plasma reinforced chemical vapour deposition.
Optionally, described deposition stressor layers exists: carry out under reaction chamber pressure 4～10Torr condition.
Optionally, the raw material that adopted of described deposition stressor layers is: SiH
4Flow 50～100sccm, NH
3Flow 400～700sccm, N
2Flow 800～1500sccm.
Optionally, the thickness of described stressor layers be 300～
Optionally, the stress value of described stressor layers is 500～800MPa.
Optionally, the described technological parameter that carries out thermal annealing is: temperature rises to 950 ℃～1200 ℃, annealing time 1s～2.5s.
Optionally, carry out after the thermal annealing, the stress value of described stressor layers is greater than 1200MPa.
Optionally, the Si-H key of post-depositional stressor layers and N-H key are more than the stressor layers after annealing; The Si-N key is more than post-depositional stressor layers in the stressor layers after the annealing.
The invention has the advantages that: the stressor layers that adopts low temperature and low-power deposition, protium content in the stressor layers improves, then the stressor layers quality is loose, stress is less, after the annealing, hydrogen bond in the stressor layers breaks, lattice structure in the stressor layers rearranges neatly, makes that the stressor layers quality is tight, stress significantly promotes, and can be promoted to more than the 1.5GPa.The stress of stressor layers significantly promotes, and can increase the conducting electric current, improve response device speed so that the bigger pressure of memory on the transistorized source, drain electrode can strengthen the mobility of charge carrier rate.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the manufacture method flow chart of stress memory effect semiconductor device of the present invention;
Fig. 2 to Fig. 8 is the specific embodiment schematic diagram of method shown in Figure 1.
Embodiment
In order to improve the compression that the silicon nitride stressor layers can cause, the present invention proposes the manufacture method of stress memory effect semiconductor device shown in Figure 1, comprises the steps:
S1 provides the semiconductor-based end, forms field-effect transistor on the described semiconductor-based end;
S2 forms the Stress Transfer layer on the surface of described field-effect transistor;
S3 is in the surface deposition stressor layers of described Stress Transfer layer;
S4 carries out thermal annealing to the active area of described field-effect transistor;
S5 removes stressor layers;
S6 makes interconnection structure.
Above-mentioned steps is elaborated to specific embodiment shown in Figure 8 below in conjunction with Fig. 2.
S1 provides the semiconductor-based end, forms field-effect transistor on the described semiconductor-based end.
Referring to Fig. 2, the semiconductor-based end 10, be provided, the described semiconductor-based end 10, can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.Optionally, the overall stress at the described semiconductor-based end 10 can be ignored.
Form field-effect transistor on the semiconductor-based end 10, present embodiment is the example explanation with nmos pass transistor N1 and PMOS transistor P1 only.Described nmos pass transistor N1 and PMOS transistor P1 include grid 110 and are formed on the source electrode 111 at the semiconductor-based end, grid 110 both sides 10 and drain 112.Isolated between described nmos pass transistor N1 and the PMOS transistor P1 by shallow trench 11, be filled with dielectric in the described shallow trench 11.Spacing between the grid of the grid of described nmos pass transistor N1 and PMOS transistor P1 is not less than
For nmos pass transistor, the ion that mixes in Qi Yuan/drain region can be phosphonium ion or arsenic ion.When the injection ion was arsenic ion, ion implantation energy was 2KeV to 5KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2When the injection ion was phosphonium ion, ion implantation energy was 1KeV to 3KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2And for the PMOS transistor, the ion that mixes in Qi Yuan/drain region can be boron difluoride ion, boron ion or indium ion.When the injection ion was the boron ion, ion implantation energy was 0.5KeV to 2KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2When the injection ion was the boron difluoride ion, ion implantation energy was 1KeV to 4KeV, and ion implantation dosage is 5 * 10
14/ cm
2To 2 * 10
15/ cm
2
The concrete formation technology of nmos pass transistor N1 and PMOS transistor P1 is same as the prior art, can adopt conventional CMOS technology to make device architecture shown in Figure 2.In the present embodiment, only to form a nmos pass transistor N1 and a PMOS transistor P1 is an example, be not that the semiconductor device structure in the manufacture method of the present invention is made qualification, those skilled in the art should spread to manufacture method of the present invention and be applied in the process for fabrication of semiconductor device of other structures, explanation hereby.
S2 forms the Stress Transfer layer on the surface of described field-effect transistor.
Referring to Fig. 3, form Stress Transfer layer 12 on the surface of described nmos pass transistor N1 and PMOS transistor P1.Described Stress Transfer layer 12 does not have big internal stress, and for example its internal stress is less than 100MPa, but these Stress Transfer layer 12 compact structures have higher Young's modulus, for example greater than 10GPa.The material of described Stress Transfer layer 201 can be SiO
2Or the SiO that mixes
2When the material of Stress Transfer layer 201 is SiO
2In time, can form by chemical vapor deposition method or high-temperature thermal oxidation method technology.In the present embodiment, described Stress Transfer layer 201 adopts chemical vapor deposition method to form, and material is SiO
2, thickness is not more than
Preferable range is
Described Stress Transfer layer 12 can also be as the barrier layer, can reduce or prevent dopant ion (for example phosphonium ion in the nmos pass transistor or arsenic ion in Stress Transfer layer 12 active area (comprising grid and source/drain region) under covering, boron ion or indium ion in the PMOS transistor) to outdiffusion, avoid the concentration of dopant ion in the described active area to descend, and guaranteed the insulation property of semiconductor device.
S3 is in the surface deposition stressor layers of described Stress Transfer layer.
Referring to Fig. 4, form stressor layers 13 on the surface of described Stress Transfer layer 12.In the present embodiment, the material of described stressor layers 13 is a silicon nitride.Described stressor layers 13 mainly can form by PECVD (plasma reinforced chemical vapour deposition) mode.By changing the parameter of described chemical vapour deposition (CVD), can regulate stress types and stress intensity that 13 pairs of bottom transistor of stressor layers are brought out.
The thickness of stressor layers 13 is not less than
Preferable range is
The stress types that described stressor layers 13 is brought out is a tensile stress, therefore can improve the carrier mobility of channel region among the nmos pass transistor N1.
In existing technology, technical staff's viewpoint is that the stress value that promotes stressor layers is so that after the thermal annealing by the improvement technological parameter, and transistor can obtain bigger stress.In some concrete case, the stress value of stressor layers can be promoted to 1220MPa.
The present invention when deposition stressor layers 13, adopts lower temperature then from opposite angles, and for example 350～450 ℃, lower-wattage 50～150W improves the protium content in the stressor layers 13, then forms more N-H key and Si-H key in the stressor layers 13.
For example, adopt pecvd process, reaction chamber pressure 4～10Torr (holder), power 50～150W, 350～450 ℃ of temperature, SiH
4Flow 50～100sccm (standard cubic centimeter per minute), NH
3Flow 400～700sccm, N
2Flow 800-1500sccm, formation has
Stressor layers 13.This stressor layers 13 has lower pressure, for example between 500～800MPa.
Referring to Fig. 5, in the present embodiment, also need optionally to remove the stressor layers of field effect transistor tube-surface according to stress types.As mentioned above, in the present embodiment, because it is tensile stress that stressor layers 13 is brought out stress types, only pair nmos transistor N1 plays the beneficial effect that improves carrier mobility, therefore described selective etch is specially: spin coating photoresist on nmos pass transistor N1 and PMOS transistor P1, making light see through mask exposes to photoresist, by the photoresist on the removal nmos pass transistor N1 that develops, remove the stressor layers 13 on PMOS transistor P1 surface again by dry etching, and keep the part stressor layers 13 that is positioned at nmos pass transistor N1 surface.
S4 carries out thermal annealing to the active area of described field-effect transistor;
The active area of pair nmos transistor N1 and PMOS transistor P1, promptly thermal annealing is carried out in grid and source/drain region.The stress that described thermal annealing will make stressor layers 13 be brought out is remembered to corresponding field-effect transistor, to improve the carrier mobility of channel region.The parameter of described annealing is: temperature rises to 950 ℃～1200 ℃, annealing time 1s～2.5s.
The existing formed stressor layers of technology is the few Si of hydrogen content
3N
4, through after the thermal annealing, the stress value of stressor layers can slightly reduce.For example, original pressure is the stressor layers of 1220MPa, and the pressure after the annealing is 1150MPa, referring to the FilmA in the table one.
And stressor layers of the present invention 13 annealed after, N-H key and Si-H key break, and form Si again
3N
4, and, annealed formed Si
3N
4Compare the formed Si of deposition
3N
4Lattice structure is arranged regular, fine and close, can significantly improve the stress of stressor layers 13.In a specific embodiment, original pressure is the stressor layers 13 of 698MPa, and pressure is increased to 1538MPa after the annealing, referring to the Film B in the table one.
Table one
The tension stress layer of silicon nitride material can will be transferred in the semiconductor device by Stress Transfer layer 12 with the stress of stressor layers after annealing, when having higher stress after stressor layers 13 annealing, to remember bigger stress on the nmos pass transistor N1, bigger stress can strengthen the mobility of charge carrier rate, increases the conducting electric current, improves response device speed.
The inventor is by analyzing the stressor layers performance that adopts different deposition temperatures, identical anneal processes, sum up as can be known in the enforceable thickness range of stressor layers (300～
), adopt low temperature low-power deposition stressor layers can improve device mobility of charge carrier speed, device electrical performance (for example speed of response) can improve 4～10%.
The inventor finds depositing temperature in 350 ℃ to 450 ℃ scopes through experiment, and power is in the low scope of 50～150W, and the hydrogen content in the stressor layers improves, and the stress of annealing back stressor layers can reach more than the 1.5GPa.
S5 removes stressor layers.
In the present embodiment, described stressor layers 13 is the part on surplus nmos pass transistor N1 surface only, only needs to remove nmos pass transistor N1 and goes up remaining stressor layers 13, forms structure shown in Figure 6.The material of described stressor layers 13 is a silicon nitride, and also has Stress Transfer layer 12 on the surface of nmos pass transistor N1 and PMOS transistor P1, and the material of described Stress Transfer layer 12 is SiO
2, therefore can adopt selective etch, remove described stressor layers 13, and utilize described Stress Transfer layer 12 to protect the field-effect transistor under it not to be corroded.
S6 makes interconnection structure.
Before making interconnection structure, can comprise the step of all or part of removal Stress Transfer layer 12, for example can remove Stress Transfer layer 12, form structure shown in Figure 7 by etching.
Then,, can carry out the making of rear end silication technique for metal and multilayer interconnect structure, not repeat them here referring to Fig. 8.
In the present embodiment, because when deposition stressor layers 13, adopt the low temperature low-power, make stressor layers 13 be the more low-pressure state of hydrogen content, after the annealing, shell of compression 13 compact structures, pressure significantly promote, and make the bigger stress of memory on the source, drain electrode of nmos pass transistor, can strengthen the mobility of charge carrier rate, increase the conducting electric current, improve response device speed.
Present embodiment is the influence of example explanation low temperature depositing to device performance with the tension stress layer only, one skilled in the art will appreciate that, this method can also be applied on the compressive stress layer, in the time of on being applied to compressive stress layer, need the material prescription of counter stress layer to adjust, for example adopt metal silicide (can be the Chinese invention patent " semiconductor structure and method thereof " of CN101320713A referring to publication number).Range of application of the present invention also is not limited only to field-effect transistor, and should be understood to, and all can use in field of semiconductor manufacture.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the manufacture method of a stress memory effect semiconductor device comprises the steps: to provide the semiconductor-based end, forms transistor on the described semiconductor-based end; At described transistorized surface deposition Stress Transfer layer; Surface deposition stressor layers at described Stress Transfer layer; Described transistorized active area is carried out thermal annealing; Remove stressor layers; Make interconnection structure, it is characterized in that: described deposition stressor layers is carried out under power 50～150W condition 350～450 ℃ of temperature.
2. method according to claim 1 is characterized in that: the material of described Stress Transfer layer is SiO
2Or the SiO that mixes
2
3. method according to claim 1 is characterized in that: the material of described stressor layers is a silicon nitride.
4. method according to claim 1, it is characterized in that: described transistor comprises nmos pass transistor and PMOS transistor, described stressor layers is a tension stress layer, after the surface deposition stressor layers of described Stress Transfer layer, also comprise the step of the stressor layers on the selective removal PMOS transistor.
5. method according to claim 1 is characterized in that: described deposition stressor layers is for adopting the mode of plasma reinforced chemical vapour deposition.
6. method according to claim 5 is characterized in that: described deposition stressor layers exists: carry out under reaction chamber pressure 4～10Torr condition.
7. according to claim 1 or 6 described methods, it is characterized in that: the raw material that described deposition stressor layers is adopted is: SiH
4Flow 50～100sccm, NH
3Flow 400～700sccm, N
2Flow 800～1500sccm.
8. method according to claim 1 is characterized in that: the thickness of described stressor layers is 300～
9. method according to claim 1 is characterized in that: after the deposition stressor layers, the stress value of described stressor layers is 500～800MPa.
10. method according to claim 1 is characterized in that: the described technological parameter that carries out thermal annealing is: temperature rises to 950 ℃～1200 ℃, annealing time 1s～2.5s.
11. method according to claim 1 is characterized in that: carry out after the thermal annealing, the stress value of described stressor layers is greater than 1200MPa.
12. method according to claim 1 is characterized in that: the Si-H key of post-depositional stressor layers and N-H key are more than the stressor layers after annealing; The Si-N key is more than post-depositional stressor layers in the stressor layers after the annealing.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102412203A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving stress memorization technical effect of semiconductor device |
| CN102427043A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102446918A (en) * | 2011-08-17 | 2012-05-09 | 上海华力微电子有限公司 | Structure for preventing etch stop layer from cracking and method for forming structure |
| CN102543887A (en) * | 2012-02-28 | 2012-07-04 | 上海华力微电子有限公司 | Method for improving operating speed of SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing channel stress |
| CN102709178A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Method for forming double-stress-layer silicon nitride thin film |
| CN103094108A (en) * | 2011-10-29 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN111856229A (en) * | 2019-04-12 | 2020-10-30 | 华北电力大学 | High-temperature reverse bias test method for compression joint type insulated gate bipolar transistor with mechanical stress acceleration |
| CN114373717A (en) * | 2021-12-10 | 2022-04-19 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for fabricating the same |
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2009
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| CN102412203A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving stress memorization technical effect of semiconductor device |
| CN102427043A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102427043B (en) * | 2011-08-04 | 2015-06-17 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102446918A (en) * | 2011-08-17 | 2012-05-09 | 上海华力微电子有限公司 | Structure for preventing etch stop layer from cracking and method for forming structure |
| CN103094108A (en) * | 2011-10-29 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN103094108B (en) * | 2011-10-29 | 2015-12-02 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN102543887A (en) * | 2012-02-28 | 2012-07-04 | 上海华力微电子有限公司 | Method for improving operating speed of SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing channel stress |
| CN102709178A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Method for forming double-stress-layer silicon nitride thin film |
| CN102709178B (en) * | 2012-05-22 | 2015-08-19 | 上海华力微电子有限公司 | A kind of method forming dual stressed layers silicon nitride film |
| CN111856229A (en) * | 2019-04-12 | 2020-10-30 | 华北电力大学 | High-temperature reverse bias test method for compression joint type insulated gate bipolar transistor with mechanical stress acceleration |
| CN111856229B (en) * | 2019-04-12 | 2023-08-15 | 华北电力大学 | Crimping type insulated gate bipolar transistor high-temperature reverse bias test method |
| CN114373717A (en) * | 2021-12-10 | 2022-04-19 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for fabricating the same |
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Application publication date: 20110511 |