CN102543887A - Method for improving operating speed of SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing channel stress - Google Patents

Method for improving operating speed of SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing channel stress Download PDF

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CN102543887A
CN102543887A CN2012100473538A CN201210047353A CN102543887A CN 102543887 A CN102543887 A CN 102543887A CN 2012100473538 A CN2012100473538 A CN 2012100473538A CN 201210047353 A CN201210047353 A CN 201210047353A CN 102543887 A CN102543887 A CN 102543887A
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sonos
stress
channel
silicon
nitride layer
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黄奕仙
杨斌
郭明升
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

The invention provides a method for improving an operating speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing a channel stress. The method comprises the following steps of: (1) depositing a silicon nitride layer on the surface of the SONOS device after finishing source and drain end injection; (2) changing stress in a channel of the SONOS device; and (3) removing the silicon nitride layer covering the surface of the SONOS device. According to the method for improving the operating speed of the SONOS device by changing the channel stress, disclosed by the invention, one silicon nitride layer with high tensile stress is deposited after the source and drain end injection of the SONOS device is finished through channel stress engineering, and the channel of the SONOS device generates the tensile stress through stress memory, thus energy band of silicon is broken up so that effective mass of electron in the direction of the channel is reduced; simultaneously, energy valley scattering probability of the electron is also reduced, and mobility of the electron of the SONOS unit transistor is remarkably improved, thus channel current is increased, and the SONOS programming efficiency and speed of a hot electron injection mechanism are improved.

Description

A kind of through changing the method that channel stress improves SONOS device operating rate
Technical field
The present invention relates to improve device speed of service method in a kind of semiconductor applications, relate in particular to a kind of method of utilizing the channel stress engineering to improve the program speed of SONOS.
Background technology
The basic functional principle of non-volatile semiconductor memory is at a metal-oxide half field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, stored charge in gate medium MOSFET).Wherein the device that is stored in the trapping centre of separation of a suitable dielectric layer of electric charge is called as the electric charge capture device.The most frequently used in this type device is silicon-silica-silicon-nitride and silicon oxide-silicon (Silicon Oxide Nitride Oxide Silicon, SONOS) memory.
The main two kinds of memory mechanisms that are used for the storage data of flash memory cells are that channel hot electron (CHE) injects and the F-N tunneling effect.Channel hot electron injects and is considered to after through long-term circulation, remain quite reliable, and reason is that it does not apply very big stress on tunnel oxide.But the shortcoming of CHE is that programming efficiency is low.It is that transverse electric field with raceway groove comes accelerated electron that channel hot electron injects, and obtains one when being enough to overcome the high-energy of potential barrier when electronics is accelerated to, and the hot electron injection will take place.During programming, drain and gate all will apply relative higher voltage, and drain electrode directly links to each other with voltage source, and grid voltage then depends on capacitive coupling.For effective programming, transistor should be biased in the saturation region, makes the electronics that passes pinch-off point in the drain terminal depletion region, set up big transverse electric field.This bias state of grid makes near the channel inversion layer broad the source, and along with the convergence pinch-off point, it is narrower that channel inversion layer becomes, so that pass in the high electric field of electronics in the drain terminal depletion region of pinch-off point by strong acceleration.When portions of electronics obtains enough high-energy like this, hot electron just takes place inject, but because to have only the sub-fraction raceway groove be effectively to programming, so hot electron injection programming efficient is not high.
Summary of the invention
The present invention is in order to improve SONOS programming efficiency and the speed that hot electron injects mechanism; The method of channel stress in a kind of SONOS of change device is provided; The electron mobility of SONOS cell transistor is significantly improved, thereby improve channel current and improve SONOS programming efficiency and the speed that hot electron injects mechanism.
To achieve these goals, it is a kind of through changing the method that channel stress improves SONOS device operating rate that the present invention provides, and comprises following sequential steps:
Step 1: surface deposition one deck silicon nitride layer of the SONOS device that drain terminal injects in the source of completion.
Step 2: the stress in the raceway groove of change SONOS device.
Step 3: remove the silicon nitride layer that covers on the SONOS device surface.
In the above-mentioned method that provides, has high tensile stress in the wherein said silicon nitride layer.
In the above-mentioned method that provides, the thickness of wherein said silicon nitride layer is between 300 ~ 600 dusts.In the preferred version, deposit forms the thickness of silicon nitride layer between 400 ~ 500 dusts.
In the above-mentioned method that provides, wherein adopt the spike mode to change the stress in the SNONS device channel.The temperature of spike preferably is controlled between 1000 ~ 1050 ℃.
In the above-mentioned method that provides, wherein adopt dry etching or wet etching to remove silicon nitride layer.
The method of channel stress in the change SONOS device provided by the invention; Utilize channel stress engineering deposit one deck after the injection completion is leaked in the SONOS source to have the silicon nitride layer of high tensile stress; Make the SONOS cell channel produce tensile stress through stress memory; Being with of silicon divided, and the result of division causes reducing along the electron effective mass of channel direction, and the energy valley of electronics sees that probability of scattering also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve channel current and improve SONOS programming efficiency and the speed that hot electron injects mechanism.
Description of drawings
Fig. 1 is the SONOS device architecture figure that is deposited with silicon nitride layer among the present invention.
Fig. 2 implants SONOS device architecture figure behind the stress among the present invention.
Fig. 3 is the SONOS device that is had tensile stress by the formed raceway groove of method provided by the invention.
Embodiment
It is a kind of through changing the method that channel stress improves SONOS device operating rate that the present invention provides; May further comprise the steps: earlier will be at surface deposition one deck silicon nitride layer of accomplishing the SONOS device that the source drain terminal injects; Stress in the raceway groove of change SONOS device is removed the silicon nitride layer that covers on the SONOS device surface at last.
The present invention sets about a little improving SONOS device operating rate from the angle that improves the channel carrier mobility.Carrier mobility can be by equation
Figure 2012100473538100002DEST_PATH_IMAGE002
Decision, wherein qBe electron charge, m* be the charge carrier effective mass, t is the average life span between double scattering.Therefore, probability of scattering is 1/t.This patent utilizes the channel stress engineering; Deposit one deck has the silicon nitride layer of high tensile stress after the SONOS device source is leaked the injection completion; Make the SONOS device channel produce tensile stress through stress memory; Being with of silicon divided, and the result of division causes reducing along the electron effective mass of channel direction, and the energy valley of electronics sees that probability of scattering also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve channel current and improve SONOS device programming efficient and the speed that hot electron injects mechanism.
Below be described further through changing the method that channel stress improves SONOS device operating rate provided by the invention through embodiment so that better understand the content of the invention, do not require protection range but the content of embodiment does not limit the invention.
As shown in Figure 1, surface deposition one deck of the SONOS device that drain terminal injects in the source of completion has high tensile stress silicon nitride layer 1, and the silicon nitride layer thickness that deposit forms is between 400 ~ 500 dusts (A).3 is the source end among Fig. 1, and 4 is drain terminal.
Adopt the spike mode stress to be implanted in the raceway groove of SONOS device, the temperature of spike is controlled at about 1000 ~ 1050 ℃.Fig. 2 is SONOS device architecture figure behind the implantation stress, and wherein 2 for having the raceway groove of a tensile stress.
Adopt dry method or wet-etching technology that the silicon nitride layer that covers on the SONOS device is removed, then form the SONOS unit component that raceway groove has tensile stress, its structure is as shown in Figure 3.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims (7)

1. the method through change channel stress raising SONOS device operating rate is characterized in that, comprises following sequential steps:
Step 1: surface deposition one deck silicon nitride layer of the SONOS device that drain terminal injects in the source of completion;
Step 2: the stress in the raceway groove of change SONOS device;
Step 3: remove the silicon nitride layer that covers on the SONOS device surface.
2. method according to claim 1 is characterized in that, has high tensile stress in the said silicon nitride layer.
3. method according to claim 1 is characterized in that, the thickness of said silicon nitride layer is 300 ~ 600 dusts.
4. method according to claim 3 is characterized in that, the thickness of said silicon nitride layer is 400 ~ 500 dusts.
5. method according to claim 1 is characterized in that, adopts the spike mode to change the stress in the SNONS device channel.
6. method according to claim 5 is characterized in that, the temperature of said spike is 1000 ~ 1050 ℃.
7. method according to claim 1 is characterized in that, adopts dry etching or wet etching to remove silicon nitride layer.
CN2012100473538A 2012-02-28 2012-02-28 Method for improving operating speed of SONOS (Silicon Oxide Nitride Oxide Silicon) device by changing channel stress Pending CN102543887A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508961A (en) * 2020-04-27 2020-08-07 复旦大学 High-tunneling-efficiency semi-floating gate memory and preparation method thereof

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Publication number Priority date Publication date Assignee Title
US20080090350A1 (en) * 2006-10-12 2008-04-17 Jiang Yan Strained semiconductor device and method of making same
CN101563783A (en) * 2005-09-23 2009-10-21 Nxp股份有限公司 Memory device with improved performance and method of manufacturing such a memory device
CN101606236A (en) * 2007-05-25 2009-12-16 赛普拉斯半导体公司 The integrated device of Nonvolatile charge trap memory device and logic CMOS device
CN102054776A (en) * 2009-10-28 2011-05-11 中芯国际集成电路制造(上海)有限公司 Method for manufacturing stress memorization effect semiconductor device
CN102244098A (en) * 2010-05-14 2011-11-16 台湾积体电路制造股份有限公司 Semiconducotor device and manufacturing method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101563783A (en) * 2005-09-23 2009-10-21 Nxp股份有限公司 Memory device with improved performance and method of manufacturing such a memory device
US20080090350A1 (en) * 2006-10-12 2008-04-17 Jiang Yan Strained semiconductor device and method of making same
CN101606236A (en) * 2007-05-25 2009-12-16 赛普拉斯半导体公司 The integrated device of Nonvolatile charge trap memory device and logic CMOS device
CN102054776A (en) * 2009-10-28 2011-05-11 中芯国际集成电路制造(上海)有限公司 Method for manufacturing stress memorization effect semiconductor device
CN102244098A (en) * 2010-05-14 2011-11-16 台湾积体电路制造股份有限公司 Semiconducotor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508961A (en) * 2020-04-27 2020-08-07 复旦大学 High-tunneling-efficiency semi-floating gate memory and preparation method thereof

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Application publication date: 20120704