CN104157655B

CN104157655B - SONOS flash memory device and compiling method thereof

Info

Publication number: CN104157655B
Application number: CN201410427471.0A
Authority: CN
Inventors: 顾经纶
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2014-08-27
Filing date: 2014-08-27
Publication date: 2020-02-21
Anticipated expiration: 2034-08-27
Also published as: CN104157655A

Abstract

The invention discloses a SONOS flash memory device which comprises a substrate and a split gate structure positioned on the substrate. The split gate structure includes a first oxide layer in contact with a semiconductor substrate, a polysilicon control gate and a silicon nitride gate on the first oxide layer, and a second oxide layer isolating the polysilicon control gate from the silicon nitride gate. When the SONOS flash memory device is compiled, electrons of a channel electron layer induced in a semiconductor substrate below a polysilicon control gate under the action of a first gate voltage are accelerated under the action of the substrate bias voltage and are injected into the silicon nitride gate under the action of a second gate voltage by applying the first gate voltage which is larger than or equal to a threshold voltage on the polysilicon control gate, applying a second gate voltage which is larger than the first gate voltage on the silicon nitride gate and applying a positive substrate bias voltage on the semiconductor substrate. The invention can improve the channel hot electron injection efficiency, reduce the current power consumption and reduce the size of the device.

Description

SONOS flash memory device and compiling method thereof

Technical Field

The present invention relates to a memory, and more particularly, to a SONOS flash memory device and a compiling method thereof.

Background

Since a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure gradually replaces a polysilicon floating gate flash memory structure as a main flash memory structure of a nonvolatile memory, research on how to improve the compiling speed of the SONOS structure is increasing.

One of the main compiling mechanisms for SONOS flash memory devices is the Channel Hot Electron (CHE) injection effect. Channel hot electron injection is considered to be fairly reliable over long cycles because it does not place significant stress on the tunnel oxide. But the CHE has the disadvantage of inefficient injection of the compilation. This is because the direction of the channel's electric field at the injection point near the drain end does not facilitate the collection of electrons. In conventional MOS devices, the lateral electric field is a decreasing function of the gate voltage, while the longitudinal electric field rises with increasing gate voltage. Therefore, to generate a large number of hot electrons, a low gate voltage and a high drain voltage are applied to the device. However, in order to inject and collect electrons in the memory device, a high gate voltage and a low drain voltage are applied. As a compromise, the SONOS flash memory device using CHEI as a coding mechanism must apply high voltage to both the drain and the gate, but this also results in low channel hot electron injection efficiency and large current consumption.

To solve this problem, it is necessary to provide a SONOS flash memory device with low power and high speed.

Disclosure of Invention

The present invention is directed to overcoming the drawbacks of the prior art and providing a SONOS flash memory device that can solve the erase saturation problem.

The invention is realized by the following technical scheme:

a SONOS flash memory device, comprising: a semiconductor substrate including a source region and a drain region; the split gate structure comprises a first oxide layer, a polysilicon control gate, a silicon nitride gate and a second oxide layer, wherein the first oxide layer is in contact with the semiconductor substrate, the polysilicon control gate and the silicon nitride gate are positioned on the first oxide layer, and the second oxide layer is used for isolating the polysilicon control gate from the silicon nitride gate; the first oxide layer, the silicon nitride gate and the second oxide layer form an ONO dielectric structure; when the SONOS flash memory device is compiled, electrons of a channel electron layer induced in the semiconductor substrate below the polysilicon control gate under the action of the first gate voltage are accelerated under the action of the substrate bias voltage and are injected into the silicon nitride gate under the action of the second gate voltage by applying a first gate voltage which is greater than or equal to a threshold voltage on the polysilicon control gate, applying a second gate voltage which is greater than the first gate voltage on the silicon nitride gate and applying a positive substrate bias voltage on the semiconductor substrate.

Preferably, the polysilicon control gate at least partially covers the silicon nitride gate.

Preferably, the second gate voltage is at least twice the first gate voltage.

Preferably, the SONOS flash memory device is an n-channel device, the silicon nitride gate is closer to the drain region than the polysilicon control gate, when the SONOS flash memory device is compiled, a source voltage of 0V is applied to the source region, and a positive drain voltage is applied to the drain region.

Preferably, the first grid voltage is 0.7-1V, the second grid voltage is 2-3V, the drain voltage is 2-3V, and the substrate bias voltage is 1-1.5V.

Preferably, the thickness of the first oxide layer is 2-3.5 nm, the thickness of the silicon nitride gate is 50-90 nm, the thickness of the second oxide layer is 3-5 nm, and the thickness of the polysilicon control gate is 80-120 nm.

Further, the present invention also provides a compiling method of the SONOS flash memory device, which includes a semiconductor substrate having a source region and a drain region therein, and a split gate structure located between the source region and the drain region on the semiconductor substrate, the split gate structure including a first oxide layer in contact with the semiconductor substrate, a polysilicon control gate and a silicon nitride gate located on the first oxide layer, and a second oxide layer isolating the polysilicon control gate and the silicon nitride gate; the first oxide layer, the silicon nitride gate and the second oxide layer form an ONO dielectric structure, and the compiling method comprises the following steps: and applying a first gate voltage which is greater than or equal to a threshold voltage to the polysilicon control gate, applying a second gate voltage which is greater than the first gate voltage to the silicon nitride gate, and applying a positive substrate bias voltage to the semiconductor substrate, so that electrons of a channel electron layer induced in the semiconductor substrate below the polysilicon control gate under the action of the first gate voltage are accelerated under the action of the substrate bias voltage and are injected into the silicon nitride gate under the action of the second gate voltage.

Preferably, the second gate voltage is at least twice the first gate voltage.

Preferably, the SONOS flash memory device is an n-channel device, the silicon nitride gate is closer to the drain region than the polysilicon control gate, and the compiling method further includes applying a source voltage of 0V to the source region and applying a positive drain voltage to the drain region; the first grid voltage is 0.7-1V, the second grid voltage is 2-3V, the drain voltage is 2-3V, and the substrate bias voltage is 1-1.5V.

The invention has the advantages that the SONOS device with the split gate structure applies low voltage to the polysilicon control gate and applies high voltage to the silicon nitride gate, so that the channel hot electron injection efficiency can be improved, the current power consumption is reduced, the defects of low compiling injection efficiency and large current power consumption of the traditional SONOS flash memory utilizing a CHE mechanism can be solved, and on the other hand, the invention can reduce the drain voltage by applying positive bias voltage on the substrate, thereby avoiding the situation that the drain region is contacted with the depletion region to cause the punch-through and failure of the device due to the fact that the drain region extends to the width of the depletion layer of the substrate is too large. Therefore, further reduction in device size is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a SONOS flash memory device according to an embodiment of the present invention.

Detailed Description

In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.

Fig. 1 is a schematic structural diagram of a SONOS flash memory device according to an embodiment of the present invention, and as shown in fig. 1, the SONOS flash memory device is an n-channel device, and includes a p-type semiconductor substrate 10, n-type doped source and

drain regions

15a and 15b located in the p-type semiconductor substrate 10, and a split gate structure located between the source and drain regions on the semiconductor substrate. The split gate structure includes a first oxide layer 11 in contact with a semiconductor substrate 10, a polysilicon control gate 14 and a silicon nitride gate 12 on the first oxide layer 11, and a second oxide layer 13 isolating the polysilicon control gate 14 and the silicon nitride gate 12. Wherein the polysilicon control gate 14 is closer to the source region 15a than the silicon nitride gate 12. The first oxide layer 11 serves as a tunnel oxide, the silicon nitride gate 12 as a charge storage layer, and the second oxide layer 13 as a blocking oxide, thereby forming an ONO dielectric structure. The materials of the first oxide layer 11 and the second oxide layer 13 are both silicon dioxide. As shown, the polysilicon control gate 14 at least partially covers the silicon nitride gate 12 and has a zigzag shape, and in other embodiments, the polysilicon control gate 14 may not cover the silicon nitride gate 12. The thickness of the first oxide layer 11 is 2-3.5 nm, the thickness of the silicon nitride gate 12 is 50-90 nm, the thickness of the second oxide layer 13 is 3-5 nm, and the thickness of the polysilicon control gate 14 is 80-120 nm. In a preferred embodiment, the length of the polysilicon gate of the split gate structure is 10nm, the thickness of the polysilicon gate is 90nm, the length of the silicon nitride gate is 40nm, the height of the silicon nitride gate is 70nm, the thickness of the first oxide layer is 2.5nm, and the thickness of the second oxide layer is 3 nm. The split gate structure can be completed by using a conventional CMOS process without great modification, and can be produced by a common semiconductor manufacturing company.

The compilation process of the SONOS flash memory device of the present invention will be described below. When the SONOS flash memory device is compiled, a first gate voltage Vg equal to or larger than the threshold voltage is applied to the polysilicon control gate 14_SiApplying a second gate voltage Vg greater than the first gate voltage to the silicon nitride gate 12_SiNA positive substrate bias voltage Vb is applied to the p-type substrate 10, and a source voltage V of 0V is applied to the source region 15a_sAnd applying a positive drain voltage Vd to the drain region. Preferably, the first gate voltage Vg_SiThe first grid voltage is 0.7-1V when the threshold voltage is close to the threshold voltage, such as 0.7V; second gate voltage Vg_SiNAt least a first gate voltage Vg_SiAbout 2 to 3V, and a substrate bias of 1 to 1.5V. At a first gate voltage Vg_SiInduces a thin channel electron layer in the region of the substrate under the polysilicon control gate 14, at a second gate voltage Vg_SiNInduces a thicker channel electron shell in the substrate region below the silicon nitride gate 12. The substrate bias Vb accelerates electrons e in the thinner channel electron layer under the polysilicon control gate 14 to gain enough energy and inject the silicon nitride gate 12 under the second gate voltage to complete the programming. The drain voltage Vd is due to a positive substrate bias Vb applied across the substrateCan be smaller, such as 2-3V. Therefore, the phenomenon that the device is pierced and failed due to the fact that the width of the depletion layer of the drain region is too large due to too large drain voltage can be avoided, and the size of the SONOS flash memory device can be further reduced to be 50nm or below.

In summary, the SONOS flash memory device of the present invention, by providing the split gate structure, and applying a smaller and larger voltage to the polysilicon control gate and the silicon nitride gate of the split gate structure and applying a positive bias voltage to the substrate during programming, can not only improve the channel hot electron injection efficiency and reduce the current power consumption, but also overcome the defects of low coding injection efficiency and large current power consumption of the conventional SONOS flash memory using the CHE mechanism, and further reduce the drain voltage by using the back gate bias assist mechanism, thereby avoiding the punch-through and failure of the device caused by the contact between the drain region and the depletion region due to the fact that the drain region extends to the width of the depletion layer of the substrate is too large, and facilitating the further reduction of the device size.

Although the present invention has been described with reference to preferred embodiments, it is to be understood that the foregoing is illustrative and not restrictive, and that various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A SONOS flash memory device, comprising:

a semiconductor substrate including a source region and a drain region; and

the split gate structure is positioned between the source region and the drain region on the semiconductor substrate and comprises a first oxide layer, a polycrystalline silicon control gate, a silicon nitride gate and a second oxide layer, wherein the first oxide layer is in contact with the semiconductor substrate; the first oxide layer, the silicon nitride gate and the second oxide layer form an ONO dielectric structure;

when the SONOS flash memory device is compiled, by applying a first gate voltage which is greater than or equal to a threshold voltage on the polysilicon control gate, applying a second gate voltage which is greater than the first gate voltage on the silicon nitride gate and applying a positive substrate bias voltage on the semiconductor substrate, electrons of a channel electron layer induced under the first gate voltage in the semiconductor substrate below the polysilicon control gate are accelerated towards the substrate under the substrate bias voltage and are injected into the silicon nitride gate under the second gate voltage after the acceleration.

2. The SONOS flash memory device of claim 1, wherein the polysilicon control gate at least partially overlies the silicon nitride gate.

3. The SONOS flash memory device of claim 1, wherein the second gate voltage is at least twice the first gate voltage.

4. The SONOS flash memory device of claim 3, wherein the SONOS flash memory device is an n-channel device, wherein the silicon nitride gate is closer to the drain region than the polysilicon control gate, wherein the source region applies a source voltage of 0V and the drain region applies a positive drain voltage when the SONOS flash memory device is compiled.

5. The SONOS flash memory device of claim 4, wherein the first gate voltage is 0.7-1V, the second gate voltage is 2-3V, the drain voltage is 2-3V, and the substrate bias voltage is 1-1.5V.

6. The SONOS flash memory device of claim 1 or 2, wherein the first oxide layer has a thickness of 2-3.5 nm, the silicon nitride gate has a thickness of 50-90 nm, the second oxide layer has a thickness of 3-5 nm, and the polysilicon control gate has a thickness of 80-120 nm.

7. A compiling method of an SONOS flash memory device comprises a semiconductor substrate with a source region and a drain region, and a split gate structure located between the source region and the drain region on the semiconductor substrate, wherein the split gate structure comprises a first oxide layer in contact with the semiconductor substrate, a polysilicon control gate and a silicon nitride gate located on the first oxide layer, and a second oxide layer for isolating the polysilicon control gate and the silicon nitride gate; the first oxide layer, the silicon nitride gate and the second oxide layer form an ONO dielectric structure, and the compiling method is characterized by comprising the following steps:

applying a first gate voltage which is greater than or equal to a threshold voltage to the polysilicon control gate, applying a second gate voltage which is greater than the first gate voltage to the silicon nitride gate, and applying a positive substrate bias voltage to the semiconductor substrate, so that electrons of a channel electron layer induced in the semiconductor substrate below the polysilicon control gate under the action of the first gate voltage are accelerated towards the substrate under the action of the substrate bias voltage, and are injected into the silicon nitride gate under the action of the second gate voltage after the electrons are accelerated.

8. The compiling method of claim 7 wherein the polysilicon control gate at least partially overlies the silicon nitride gate.

9. The compiling method of claim 7 wherein the second gate voltage is at least twice the first gate voltage.

10. The compiling method of claim 9 wherein the SONOS flash memory device is an n-channel device, the silicon nitride gate being closer to the drain region than the polysilicon control gate, the compiling method further comprising applying a source voltage of 0V to the source region and applying a positive drain voltage to the drain region; the first grid voltage is 0.7-1V, the second grid voltage is 2-3V, the drain voltage is 2-3V, and the substrate bias voltage is 1-1.5V.