TWI419166B - Low - pressure rapid erasure of nonvolatile memory - Google Patents

Description

Low-voltage rapid erasing method for non-volatile memory

The invention relates to a non-volatile memory (Non-Volatile Memory) low-voltage rapid erasing method, in particular to a low-voltage fast wiping method for generating a proper amount of thermoelectric holes at a low voltage by reverse bias voltage and switching gate voltage. A low voltage fast erase method other than the operation of non-volatile memory.

According to Complementary Metal Oxide Semiconductor (CMOS) process technology, it has become a common manufacturing method for application specific integrated circuits (ASICs). In today's computer information products, Electronically Erasable Programmable Read Only Memory (EEPROM) has a non-volatile memory function that electrically writes and erases data, and is powered off. After the loss, the data will not disappear, so it is widely used in electronic products.

The non-volatile memory system is programmable to store charge to change the gate voltage of the transistor of the memory or to store the charge to leave the gate voltage of the transistor of the original memory. The erase operation removes all of the charge stored in the non-volatile memory, causing all of the non-volatile memory to return to the gate voltage of the transistor of the original memory. In the structure of conventional non-volatile memory, the erase voltage often exceeds 10 volts, and the erase time often requires microsecond (ms) level, which not only increases the cost of the boosted area, but also fails to achieve low voltage fast erase. The purpose, and advanced process technology, in addition to volatile memory, in order to reduce the effect of oxide on the erase voltage and time, it is often necessary to increase the tunneling oxide, which not only increases the difficulty of manufacturing. Degree also increases production costs.

In view of the above problems, the main object of the present invention is to provide a low-voltage rapid erasing method for non-volatile memory, by raising the gate voltage and changing the gate voltage to generate an appropriate amount of thermoelectric holes for erasing, Achieve low pressure and high speed erase.

Another object of the present invention is to provide a low-voltage fast erasing method for non-volatile memory, which uses positive and negative voltages to achieve ultra-low operating voltage, low operating current, high reliability, and overall non-volatile memory. The volume of the body can be miniaturized.

Therefore, in order to achieve the above object, the low-voltage fast erase method of the non-volatile memory disclosed in the present invention is applied to a non-volatile memory, and the non-volatile memory is provided with a stacked gate structure in a semiconductor substrate. The stacked gate structure comprises a floating gate and a control gate separated by a dielectric layer between the gates on the surface of the tunneling dielectric layer, the tunneling dielectric layer is located on the semiconductor substrate or in the isolation well, and the source and the gate are The pole is located on the two sides of the gate stack structure. Wherein, the semiconductor substrate or the isolation well is P-type, the source and the anode are N-type; or, the semiconductor substrate or the isolation well may be N-type, and the source and the anode are P-type.

The low-voltage rapid erasing method of the non-volatile memory includes changing the gate voltage during erasing, and 汲 is extremely greater than the source voltage to generate a proper amount of hot hole to be quickly erased, or using a vacuum device to achieve Ultra low operating voltage, low operating current. The invention can speed up the erasing speed by 10~100 times and reduce the erasing voltage. It is within the scope of the invention to perform the operation of erasing non-volatile memory elements with different structural changes by means of the present invention.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a non-volatile memory provided in a first embodiment of the present invention. The non-volatile memory structure 100 includes a stacked gate structure in a P-type semiconductor substrate 130. The stacked gate structure includes a floating gate 112 overlying the tunneling dielectric layer 111 and a control gate 117. A gate dielectric layer 116 is disposed over the floating gate 112, and a source 113 and a drain 114 are disposed within the P-type semiconductor substrate 130. The source 113 and the drain 114 are N-type ion doped regions.

The non-volatile memory structure 100 is a structure having four end points. As shown in FIG. 1 , the four end points are a source, a drain, a control gate, and a base connection structure, respectively. The source voltage V _sub , the source voltage V _s , the drain voltage V _d and the control gate voltage V _c are respectively applied to the source 113, the drain 114, and the control gate 117; and FIG. 2 is an equivalent circuit thereof. The conditions of the low voltage fast erase process of this non-volatile memory structure 100 are as follows:

a. V _sub is grounded (=0);

b. V _d >5V, V _{s is} close to or equal to 0; and

c. V _d >V _c ≧0, V _c decreases with the erasing time.

The non-volatile memory structure 100, during the operation from writing to erasing, raises the drain voltage, and the drain-induced barrier lowering effect (DIBL) is induced during driving. ) effects, and the element in a saturation mode, the voltage saturation drain voltage V _dsat V _d is greater than the element, and _{(V c -V s)> V} ths, saturated threshold voltage V _ths less than the maximum threshold voltage V _thmax. Then, due to the thermal energy gain of the potential energy difference of V _d -V _dsat, a drain-avalanche-hot hole injection (DAHHI) is generated to the floating gate. Then, the electrons stored in the floating gate are reduced, so that the threshold voltage _{Vth is} lowered and the source-drain current is increased. Thereafter, the control gate voltage V _{c is} gradually lowered to reduce the source-drain current while maintaining the erase speed. Alternatively, when the non-volatile memory structure 100 satisfies the following conditions, low voltage and fast erase can also be achieved:

a. V _sub is negative pressure;

b. V _{s is} close to or equal to V _sub ; and

c. V _d >V _c , V _c decreases with the erasing time.

Figure 3 is a cross-sectional view showing the structure of a non-volatile memory provided by a second embodiment of the present invention. The non-volatile memory structure 200 of the present invention may also be formed by a stacked gate structure on an N-type semiconductor substrate 230. The source 213 and the drain 214 are P-type ion doped regions, and the stacked gate structure includes A floating gate 212 and a control gate 217 are stacked.

When the low-voltage fast erase process is performed on the non-volatile memory structure 200, the substrate voltage V _sub , the source voltage V _s , and the drain voltage are respectively applied to the substrate 230 , the source 213 , the drain 214 , and the control gate 217 . V _d and the control gate voltage V _c ; Figure 4 is its equivalent circuit. The conditions are as follows:

a. V _sub and V _s >5V;

b. V _{d is} close to or equal to 0; and

c. V _c >V _d , V _c increases with the erasing time.

The non-volatile memory structure 200 increases the voltage difference between the source and the drain during the operation from the writing to the erasing, and the channel barrier effect is reduced due to the drain voltage during driving (drain-induced Barrier lowering effect, DIBL), and the component is in saturation mode, so the drain-source voltage difference V _{ds is} greater than the saturation voltage V _{dsat of the} component, and |Vc-Vs|>|Vths|, the saturation threshold voltage V _ths The absolute value will be less than the maximum threshold voltage V _thmax . Then, due to the thermal electron energy gain of the potential energy difference of V _d -V _dsat, a drain-avalanche-hot electron injection (DAHEI) is generated to the floating gate. Then, the hole stored in the floating gate is reduced, so the threshold voltage V _th rises and the source-drain current increases. Thereafter, the control gate voltage V _{c is} gradually increased to reduce the source-drain current while maintaining the erase speed.

Figure 5 is a cross-sectional view showing the structure of a non-volatile memory provided by a third embodiment of the present invention. The non-volatile memory structure 300 includes a stacked gate structure in an N-type semiconductor substrate 330. The source 313 and the drain 314 are P-type ion doped regions, and the source 313 and the drain 314 further include a P-type. Well 316, and the stacked gate structure includes a floating gate 312 and a control gate 317.

For the low-voltage fast erase process of the non-volatile memory structure 300, the substrate voltage V _sub and the P-type well voltage V are respectively applied to the substrate 330, the P-type well 316, the source 313, the drain 314, and the control gate 317. _Pwell , source voltage V _s , gate voltage V _d and control gate voltage V _c are as follows:

a. V _pwell is grounded (=0);

b. V _d >5V, V _{s is} close to or equal to 0; and

c. V _d >V _c ≧0, V _c decreases with the erasing time.

Alternatively, when the non-volatile memory structure 300 satisfies the following conditions, a low voltage and rapid erase can be achieved:

a. V _pwell is negative pressure;

b. V _{s is} close to or equal to V _pwell ; and

c. V _d >V _c , V _c decreases with the erasing time.

Figure 6 is a cross-sectional view showing the structure of a non-volatile memory provided by a fourth embodiment of the present invention. The non-volatile memory structure 400 includes a stacked gate structure in a P-type semiconductor substrate 430, a source 413 and a drain 414 are N-type ion doped regions, and the source 413 and the drain 414 further include an N-type well. 416, and the stacked gate structure includes a floating gate 412 and a control gate 417 stacked.

For the low-voltage fast erase process of the single-gate non-volatile memory structure 400, the substrate voltage V _sub and the N-type are applied to the substrate 430, the N-type well 416, the source 413, the drain 414, and the control gate 417, respectively. The well voltage V _nwell , the source voltage V _s , the drain voltage V _d and the control gate voltage V _c are as follows:

a. V _nwell and V _s >5V;

b. V _nwell ≧V _s ;

c. V _{d is} close to or equal to 0; and

d. V _nwell ≧V _c >V _d , V _c increases with the erasing time.

According to the low-voltage fast erasing method of the non-volatile memory provided by the present invention, an appropriate amount of thermoelectric holes can be generated to perform a low-voltage rapid erasing operation by increasing the voltage difference between the source and the drain and converting the gate voltage. Achieve high-speed erase effect. In addition, an appropriate amount of thermoelectric holes can be generated by applying positive and negative voltages to the drain, the gate, and the semiconductor substrate or the well region to reduce the absolute voltage and achieve the purpose of reducing the voltage. Thereby, the invention can speed up the erasing speed by 10 to 100 times and reduce the erasing voltage.

The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

100. . . Non-volatile memory structure

111. . . Tunneling dielectric layer

112. . . Floating gate

113. . . Source

114. . . Bungee

116. . . Dielectric layer

117. . . Control gate

130. . . P-type semiconductor substrate

200. . . Non-volatile memory structure

212. . . Floating gate

213. . . Source

214. . . Bungee

217. . . Control gate

230. . . N-type semiconductor substrate

300. . . Non-volatile memory structure

312. . . Floating gate

313. . . Source

314. . . Bungee

316. . . P-well

317. . . Control gate

330. . . N-type semiconductor substrate

400. . . Non-volatile memory structure

412. . . Floating gate

413. . . Source

414. . . Bungee

416. . . N-type well

417. . . Control gate

430. . . P-type semiconductor substrate

Figure 1 is a cross-sectional view showing the structure of a non-volatile memory of a first embodiment of the present invention.

Fig. 2 is an equivalent circuit of the structure of the first embodiment of the present invention.

Figure 3 is a cross-sectional view showing the structure of a non-volatile memory of a second embodiment of the present invention.

Fig. 4 is an equivalent circuit of the structure of the second embodiment of the present invention.

Figure 5 is a cross-sectional view showing the structure of a non-volatile memory of a third embodiment of the present invention.

Figure 6 is a cross-sectional view showing the structure of a non-volatile memory of a fourth embodiment of the present invention.

100. . . Non-volatile memory structure

111. . . Tunneling dielectric layer

112. . . Floating gate

113. . . Source

114. . . Bungee

116. . . Dielectric layer

117. . . Control gate

130. . . P-type semiconductor substrate

Claims (6)

A low-voltage rapid erasing method for non-volatile memory, the non-volatile memory system includes a stacked gate structure disposed on a P-type semiconductor substrate, and a source and a drain are respectively disposed on the gate stack structure In the P-type semiconductor substrate on the side, the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low voltage fast erase method includes: on the P-type semiconductor substrate, A source voltage V _sub , a source voltage V _s , a drain voltage V _d and a control gate voltage V _c are respectively applied to the source, the drain and the control gate, and the following conditions are met: a. V _Sub is ground (=0); b. V _d >5V, V _{s is} close to or equal to 0; and c. V _d >V _c ≧0, V _c decreases with erase time. A low-voltage rapid erasing method for non-volatile memory, the non-volatile memory system includes a P-type well disposed in an N-type semiconductor substrate, a stacked gate structure disposed on the P-type well, a source and a drain The poles are respectively disposed in the P-type wells on both sides of the gate stack structure, and the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low voltage fast erase method The method includes: applying a base voltage V _sub , a P-type well voltage V _pwell , a source voltage V _s , and a first to the N-type semiconductor substrate, the P-type well, the source, the drain, and the control gate The drain voltage V _d and a control gate voltage V _c satisfy the following conditions: a. V _pwell is ground (=0); b. V _d >5V, V _{s is} close to or equal to 0; and c. V _d > V _c ≧ 0, V _c decreases with the erase time. A low-voltage rapid erasing method for non-volatile memory, the non-volatile memory system includes a stacked gate structure disposed on a P-type semiconductor substrate, and a source and a drain are respectively disposed on the gate stack structure In the P-type semiconductor substrate on the side, the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low voltage fast erase method includes: on the P-type semiconductor substrate, A source voltage V _sub , a source voltage V _s , a drain voltage V _d and a control gate voltage V _c are respectively applied to the source, the drain and the control gate, and the following conditions are met: a. V _Sub is a negative pressure; b. V _{s is} close to or equal to V _sub ; and c. V _d >V _c , and V _c decreases with the erasing time. A low-voltage rapid erasing method for non-volatile memory, the non-volatile memory system includes a P-type well disposed in an N-type semiconductor substrate, a stacked gate structure disposed on the P-type well, a source and a drain The poles are respectively disposed in the P-type wells on both sides of the gate stack structure, and the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low voltage fast erase method The method includes: applying a base voltage V _sub or a P-type well voltage V _pwell , a source voltage V _s , and a first to the N-type semiconductor substrate, the P-type well, the source, the drain, and the control gate. The drain voltage V _d and a control gate voltage V _c satisfy the following conditions: a. V _pwell is a negative pressure; b. V _{s is} close to or equal to V _pwell ; and c. V _d >V _c , V _c with an erase In addition to time decrement. A low-voltage rapid erasing method for non-volatile memory, wherein the non-volatile memory system comprises a stacked gate structure disposed on an N-type semiconductor substrate, and a source and a drain are respectively disposed on the gate stack structure In the N-type semiconductor substrate on the side, the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low voltage fast erase method includes: on the N-type semiconductor substrate, A source voltage V _sub , a source voltage V _s , a drain voltage V _d and a control gate voltage V _c are respectively applied to the source, the drain and the control gate, and the following conditions are met: a. V _Sub and V _s >5V; b. V _{d is} close to or equal to 0; and c. V _c >V _d , V _c increases with the erasing time. A low-voltage rapid erasing method for non-volatile memory, the non-volatile memory system comprising an N-type well disposed in a P-type semiconductor substrate, a stacked gate structure disposed on the N-type well, a source and a drain The N-type wells are respectively disposed on the two sides of the gate stack structure, and the gate stack structure includes at least one floating gate and one control gate on the floating gate; the low-voltage fast erase method includes Applying a base voltage V _sub , an N-type well voltage V _nwell , a source voltage V _s , and a _分别 to the P-type semiconductor substrate, the N-type well, the source, the drain, and the control gate. The pole voltage V _d and a control gate voltage V _c satisfy the following conditions: a. V _nwell and V _s >5V; b. V _nwell ≧V _s ; c. V _{d is} close to or equal to 0; and d. V _nwell ≧V _c >V _d , V _c increases with the erasing time.