KR101700992B1 - Non-volatile memory and method for manufacturing non-volatile memory - Google Patents

Abstract

A nonvolatile memory and a method for manufacturing the nonvolatile memory are disclosed. According to one embodiment, a non-volatile memory includes: a deep well formed in a substrate; A first well formed in the deep well region; A second well formed in the deep well region and spaced apart from the first well; A first MOSFET formed on the first well; And a second MOSFET formed on the second well. A method of fabricating a non-volatile memory according to one embodiment includes sharing a well region of a control MOSFET with a well region of a control MOSFET of an adjacent memory cell or a well region of a tunneling MOSFET with a well region of a tunneling MOSFET of an adjacent memory cell The area of the memory cell can be reduced. The nonvolatile memory according to an exemplary embodiment of the present invention is a nonvolatile memory according to an exemplary embodiment of the present invention. In the nonvolatile memory according to an embodiment, the voltage of the shared well region in the tunneling MOSFET is kept constant and the voltage of the source / drain is made different from that of the adjacent cells. Or erase the recorded data.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a non-volatile memory and a nonvolatile memory,

The following description relates to a method of manufacturing a nonvolatile memory and a nonvolatile memory, and more particularly to a structure, a manufacturing method, and an operation method of a single poly type EEPROM (EEPROM) for performing write, erase and read operations at a low voltage .

In general, a non-volatile memory device using a silicon semiconductor process is a dual polysilicon (polysilicon) device in which two layers of polysilicon are stacked and used as a floating gate and a control gate Dual Polysilicon) EEPROM or Flash Memory is often used. Such a stacked gate type memory device has a small cell size, but is complicated in circuit and manufacturing process, and is not suitable for low density and low cost memory devices.

RFID tag chips and the like require a memory device having a relatively small memory capacity and a low cost. To this end, a single poly silicon (EEPROM) compatible with a CMOS process is mainly used.

The programming of a single polysilicon EEPROM device can be performed in two ways. The first method is to use channel hot electron injection. A programming method using channel hot electron injection forms a strong electric field in a channel region between a source electrode and a drain electrode of a metal oxide semiconductor field effect transistor (MOSFET), and a part of electrons having high kinetic energy due to a strong electric field, And is injected into the floating gate. Electrons injected into the floating gate are isolated by the potential barrier of the insulating film, and as a result, the threshold voltage of the MOS can be increased.

The second method is to use F-N tunneling (Fowler-Nordheim Tunneling). The programming method using F-N tunneling is a method in which the tunneling current increases exponentially with respect to the electric field when a high electric field is applied to the oxide film between the gate and the source / drain / well electrode. The high electric field causes the F-N tunneling phenomenon of the electrons in the MOS, so that electrons can be injected into the floating gate, so that the threshold voltage of the MOS can be increased

The present invention also provides a method of manufacturing a nonvolatile memory that can be manufactured through a CMOS process without any additional process.

A nonvolatile memory is provided that can operate at low voltages using control MOS capacitors and tunneling MOS capacitors formed on two isolated wells.

The area of the memory cell is reduced by sharing the well region of the control MOS capacitor with the well region of the control MOS capacitor of the adjacent memory cell or by sharing the well region of the tunneling MOS capacitor with the well region of the tunneling MOS capacitor of the adjacent memory cell Volatile memory device.

In a tunneling MOS capacitor, a method of operating a nonvolatile memory is provided in which data can be written or erased only in a selected memory cell by maintaining the voltage of the shared well region constant and making the voltage of the source / drain different from that of adjacent cells.

There is provided a nonvolatile memory manufacturing method capable of reducing the area of a memory cell by incorporating a MOS transistor necessary for a read operation into a well region of a tunneling MOS capacitor or by using a tunneling MOS capacitor as a MOS transistor for a read operation.

According to one embodiment, a non-volatile memory includes: a deep well formed in a substrate; A first well formed in the deep well region; A second well formed in the deep well region and spaced apart from the first well; A first MOSFET formed on the first well; And a second MOSFET formed on the second well.

The nonvolatile memory according to an embodiment is configured to share a well region of a first MOSFET (control MOS) with a well region of a first MOSFET of an adjacent memory cell, or to share a well region of a second MOSFET (tunneling MOS) The area of the memory cell can be reduced.

In the nonvolatile memory according to the embodiment, the voltage of the well region shared in the second MOSFET is kept constant, and the voltage of the source / drain is made different from that of the adjacent cells so that data is written only to the selected memory cell Or delete it.

A method of writing data to a memory cell according to an exemplary embodiment may use data in an F-N tunneling manner by maintaining the voltage of the shared well region constant and varying the source / drain voltage. In addition, data can be recorded by the channel hot electron injection method by keeping the voltage of the shared well and the source constant and by changing the voltage of the drain.

A method of erasing data in a memory cell according to an exemplary embodiment may erase data in an F-N tunneling manner by maintaining the voltage of the shared well region constant and varying the voltage of the source / drain. In addition, data can be erased in a band-to-band tunneling manner by maintaining the voltage of the shared well and the source constant and varying the voltage of the drain.

The nonvolatile memory according to an exemplary embodiment may further include a select transistor formed on the second well.

A method of manufacturing a non-volatile memory according to an embodiment includes: forming a deep well on a substrate; Forming a first well in the deep well region and a second well spaced apart from the first well; Forming a gate insulating layer over the first and second wells, forming a floating gate over the gate insulating layer, and forming a diffusion region in the deep well region, the first well region, and the second well region . ≪ / RTI >

The method of fabricating a non-volatile memory according to an embodiment may further comprise forming a third well shallower than the deep well between the first well region and the second well region in the deep well region .

According to another embodiment, a non-volatile memory includes: a first deep well formed in a substrate; A first well formed in the first deep well region; A first MOSFET formed on the first well; A second deep well formed on the substrate so as to be spaced apart from the first deep well; A second well formed in the second deep well region; And a second MOSFET formed on the second well.

The non-volatile memory according to another embodiment may further include a third well formed between the first deep well and the second deep well to separate the first deep well and the second deep well.

A method of manufacturing a non-volatile memory according to another embodiment includes: forming first and second deep wells on a substrate; Forming a first well in the first deep well region and forming a second well in the second deep well region; Forming a gate insulation layer over the first and second wells, forming a floating gate over the gate insulation layer, and forming a diffusion region in the first and second deep well regions, the first and second well regions, .

The method of manufacturing a nonvolatile memory according to another embodiment may further include forming a third well between the first deep well and the second deep well.

A nonvolatile memory according to an exemplary embodiment of the present invention can fabricate a nonvolatile memory that can operate at a low voltage through a CMOS process without any additional process.

A non-volatile memory, according to one embodiment, may operate at low voltages through control MOS capacitors and tunneling MOS capacitors formed on two isolated wells.

A method for fabricating a nonvolatile memory according to an embodiment is a method for manufacturing a nonvolatile memory in which a well region of a control MOS capacitor is shared with a well region of a control MOS capacitor of an adjacent memory cell or a well region of a tunneling MOS capacitor is connected to a tunneling MOS capacitor of an adjacent memory cell By sharing with the well region, the area of the memory cell can be reduced.

A nonvolatile memory according to an embodiment is a memory cell in which a well region is shared by keeping the voltage of the shared well region in the tunneling MOSFET constant and the voltage of the source / drain different from that of adjacent cells, You can delete it.

A method of manufacturing a nonvolatile memory according to an embodiment includes reducing a size of a memory cell by incorporating a MOS transistor necessary for a read operation into a well region of a tunneling MOS capacitor or using a tunneling MOS capacitor as a MOS transistor for a read operation .

1 is a top view illustrating a nonvolatile memory structure according to one embodiment.
2 is a side view illustrating a nonvolatile memory structure according to one embodiment.
3 is a top view illustrating the structure of a nonvolatile memory in which a plurality of memory cells are arranged in an array form according to an embodiment.
4 to 7 are diagrams showing various examples of the structure of the first MOSFET.
8 is a side view showing a structure of a nonvolatile memory according to another embodiment.
FIG. 9 is a top view illustrating a nonvolatile memory structure of a memory cell unit according to another embodiment.
10 is a flowchart illustrating a method of manufacturing a nonvolatile memory according to an embodiment.
11 is a flowchart for explaining a method of manufacturing a nonvolatile memory according to another embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions below are merely illustrative for purposes of illustrating embodiments of the invention and are not to be construed as limiting the scope of the invention to the embodiments described in the text. Like reference symbols in the drawings denote like elements.

In the following description, the non-volatile memory may be a single polysilicon non-volatile memory of a single gate structure.

1 is a top view illustrating a nonvolatile memory structure of a memory cell unit 100 according to an embodiment.

1, a nonvolatile memory in units of memory cells 100 includes a substrate 105, a conductive type deep well 110, a conductive first well 120, a conductive second well 125, A floating gate 180, a first MOSFET 135 and a second MOSFET 140. The first MOSFET 135 may be on the conductive first well 120 and the second MOSFET 140 may be on the conductive second well 125.

Hereinafter, for convenience of explanation, the substrate 105 is a P type substrate, the conductive type deep well 110 is an N type deep well, the conductive first well 120 and the conductive second well 125 are P It is assumed that the type well, the first MOSFET 135 and the second MOSFET 140 are each an N-type MOSFET (NMOS). However, the above assumption is for convenience of description, and the scope of the embodiments should not be construed to be limited by the above assumptions, and the same can also be performed in the opposite type. For example, the substrate 105 is an N-type substrate, the conductive deep-well 110 is a deep P-well, the conductive first well 120 and the conductive second well 125 are N-type wells, The MOSFET 135 and the second MOSFET 140 may each be a P-type MOSFET (PMOS).

The deep well 110 may be formed in the substrate 105 and the first well 120 and the second well 125 may be formed in the deep well 110 region. An area not corresponding to the first well 120 and the second well 125 in the region of the deep well 110 is the same type as the deep well 110 and the third well 160 which is shallower than the deep well 110 ) May be additionally formed.

Also, the deep well 110 may include the same type of diffusion region 145 for deep well 110 tie. For example, if deep well 110 is N type, then diffusion region 145 may also be N type. When the first MOSFET 135 is an NMOS, the first MOSFET 135 may include an N-type drain 115, an N-type source 155, and a P-type tie 150. At this time, terminals electrically connected to the drain 115, the source 155, and the tie 150 of the first MOSFET 135 may be formed by separately forming electrical wiring lines or by connecting a plurality of terminals.

When the second MOSFET 140 is an NMOS, the second MOSFET 140 includes an N-type drain 130, an N-type source 175, and a P-type tie 170, similar to the first MOSFET 135 .

The operation of the memory cell 100 can be controlled through the first MOSFET 135 and the second MOSFET 140 can store data in the memory cell 100 or delete data stored in the memory cell 100 .

The first well 120 may be spaced apart from the second well 125 and may include a first MOSFET 135 formed on the first well 120 and a second MOSFET 140 formed on the second well 125. [ ) Can operate as control MOS capacitors and tunneling MOS capacitors, respectively.

At least one of the first well 120 and the second well 125 may be shared between adjacent memory cells in the non-volatile memory. For example, a first well 120 may be shared with a first well 120 of an adjacent memory cell (not shown), and a second well 125 may also be shared with a second well 120 of a neighboring memory cell 125, respectively. As a result, the size of the nonvolatile memory including a plurality of memory cells can be reduced.

2 is a side view showing a structure of a nonvolatile memory in units of memory cells according to an embodiment. 2 is a side view of the nonvolatile memory shown in FIG. 1 viewed from the display lines A1-A2.

2, a nonvolatile memory in units of memory cells 200 includes a substrate 205, a conductive deep-well 210, a conductive first well 220, a conductive second well 225, a floating gate 255, a first MOSFET 230, and a second MOSFET 235. The first MOSFET 230 may be on the conductive first well 220 and the second MOSFET 235 may be on the conductive second well 225.

Also, the deep well 210 may include a diffusion region 240 of the same type for deep well 210 ties. For example, if deep well 210 is N type, then diffusion region 240 may also be N type. If the first MOSFET 230 is an NMOS, the first MOSFET 230 may include an N type drain 260, an N type source 250, and a P type tie 245. When the second MOSFET 235 is an NMOS, the second MOSFET 235 includes an N-type drain 265, an N-type source 270, and a P-type tie 275, similar to the first MOSFET 230 . An area not corresponding to the first well 220 and the second well 225 in the region of the deep well 210 is of the same type as the deep well 210 and is of the same type as the deep well 210, (Not shown) may be additionally formed.

2, an operation of writing data into the memory cell 200 included in the nonvolatile memory or deleting the written data, and a process of reading the data written in the memory cell 200 Explain the operation.

(Fowler-Nordheim Tunneling) or channel hot electron injection (Channel Hot Electrojection) may be used to write (or program) data to the memory cell 200 included in the non-volatile memory.

First, the operation of writing data to the memory cell 200 using the F-N tunneling according to an embodiment will be described.

A positive voltage is applied to the terminal DNW connected to the diffusion region 240 in the deep well 210 and a terminal ND1 connected to the drain 260 of the first MOSFET 230 and a terminal NS1 connected to the source 250, (The voltage corresponding to the data writing) to at least one of the terminals PW1 connected to the data line 245. [ Then, 0 V or a negative program voltage is applied to the terminal PW2 connected to the tie 275 of the second MOSFET 235. The diffusion region 240 for the deep well 210 tie may be floating.

In addition, in the memory cell 200 selected by the program (selected to record data), at least one of the terminal ND2 connected to the drain 265 of the second MOSFET 235 and the terminal NS2 connected to the source 270 The program voltage is applied. Then, the terminal connected to the drain of the second MOSFET (not shown) included in another memory cell (not shown) not selected as the program and the terminal connected to the source float or apply the ground voltage (0 V).

A positive voltage is applied to the floating gate 255 of the second MOSFET 235 according to the coupling ratio of the first MOSFET 230 and the second MOSFET 235 in the memory cell 200 selected by the program And the channel region formed between the drain 265 and the source 270 of the second MOSFET 235 is in the inversion state. Electrons can be supplied from either the drain 265 or the source 270 or the drain 265 and the source 270 of the second MOSFET 235 to which the negative program voltage is applied. A large electric field can be formed in the direction of the channel region formed between the drain 265, the source 270, the drain 265 and the source 270 of the MOSFET 235. [ The F-N tunneling is generated by the electric field formed in the direction of the channel region and the drain 265 of the second MOSFET 235, the source 270, and electrons can be injected into the floating gate 255.

On the other hand, in the case of the memory cell 200 not selected as a program, a positive voltage is induced in the floating gate 255 of the second MOSFET 235, but the drain 265 and the source of the second MOSFET 235 Electrons are not supplied to the channel region between the drain 260 and the source 270 of the second MOSFET 235 because the second MOSFET 235 is floating or connected to the ground. Therefore, in the memory cell 200 not selected as a program, the channel region of the second MOSFET 235 becomes a deep depletion state. In this case, since the magnitude of the electric field formed in the direction from the floating gate 255 to the drain 265, the source 257 and the channel region of the second MOSFET 235 is not enough to cause FN tunneling, Electrons are not injected into the floating gate 255 of the memory cell 200. [

Next, an operation of writing data to the memory cell 200 using channel hot electron injection according to an embodiment will be described.

A positive voltage is applied to the terminal DNW connected to the diffusion region 240 in the deep well 210 and a terminal ND1 connected to the drain 260 of the first MOSFET 230 and a terminal NS1 connected to the source 250, (The voltage corresponding to the data writing) to at least one of the terminals PW1 connected to the data line 245. [ The terminal PW2 connected to the tie 275 of the second MOSFET 235 and the terminal NS2 connected to the source 270 are connected to the ground (0 V). The diffusion region 240 for the deep well 210 tie may be floated.

In the memory cell 200 selected by the program, a positive program voltage is applied to the terminal ND2 connected to the drain 265 of the second MOSFET 235 and is stored in another memory cell (not shown) not selected by the program The terminal connected to the drain of the second MOSFET (not shown) floats or applies a ground voltage (0 V).

A positive voltage is applied to the floating gate 255 of the second MOSFET 235 according to the coupling ratio of the first MOSFET 230 and the second MOSFET 235 in the memory cell 200 selected by the program And the channel region formed between the drain 265 and the source 270 of the second MOSFET 235 satisfies the condition of the inversion state. The second MOSFET 235 is turned on and the current flows from the drain 265 of the second MOSFET 235 to the source 270 by the program voltage applied to the terminal ND2 of the second MOSFET 235. [ Can flow. Channel hot electrons (electrons having a high kinetic energy in the channel) generated in the drain junction region of the second MOSFET 235 or the channel region between the drain 265 and the source 270 are supplied to the second MOSFET 235 may be injected into the floating gate 255. As the channel hot electrons are injected into the floating gate 255, the threshold voltage of the second MOSFET 235 can be raised.

On the other hand, in the case of the memory cell 200 not selected as a program, since the drain 265 of the second MOSFET 235 is floating or connected to the ground, the drain 265 of the second MOSFET 235, The current does not flow to the capacitor 270. Therefore, channel hot electrons are not generated and electrons are not injected into the floating gate 255.

Next, an operation of deleting data recorded in the memory cell 200 included in the non-volatile memory will be described with reference to FIG. F-N tunneling or band-to-band tunneling may be used to erase data recorded in the memory cell 200 included in the non-volatile memory.

First, an operation of deleting data recorded in the memory cell 200 using F-N tunneling according to an embodiment will be described.

A voltage of 0V is applied or floated to the terminal DNW connected to the diffusion region 240 in the deep well 210 and connected to the terminal ND1 and the source 250 connected to the drain 260 of the first MOSFET 230 Terminal NS1, and a terminal PW1 connected to the tie 245. The negative program voltage (the voltage corresponding to data erasure) Then, the terminal PW2 connected to the tie 275 of the second MOSFET 235 applies or floats a voltage of 0V.

A positive program voltage is also applied to at least one of the terminal ND2 connected to the drain 265 of the second MOSFET 235 and the terminal NS2 connected to the source 270 in the memory cell 200 selected to be erased. Then, the terminal connected to the drain of the second MOSFET (not shown) included in another memory cell (not shown) not selected for deletion and the terminal connected to the source float or apply the ground voltage (0 V).

In the memory cell 200 selected to be erased, the floating gate 255 of the second MOSFET 235 is charged with a negative voltage V2 according to the coupling ratio of the first MOSFET 230 and the second MOSFET 235, . An electric field large in the direction from the drain 265 or the source 270 of the second MOSFET 235 to which the positive voltage is applied in the direction of the floating gate 255 is formed so that electrons of the floating gate 255 are removed by FN tunneling can do.

On the other hand, in the case of the memory cell 200 not selected for erasure, a negative voltage is induced in the floating gate 255 of the second MOSFET 235. However, since the drain 265 and the source 270 of the second MOSFET 235 are floating or connected to the ground, the drain 265 or the source 270 of the second MOSFET 235 is connected to the floating gate 255, Direction is not sufficient to cause FN tunneling. Therefore, the electrons present in the floating gate 255 of the memory cell 200 not selected for erasure are not removed.

The operation of deleting data recorded in the memory cell 200 using interband tunneling according to an embodiment will be described.

A voltage of 0V is applied to or floating on the terminal DNW connected to the diffusion region 240 in the deep well 210 and the terminal ND1 connected to the drain 260 of the first MOSFET 230 is connected to the terminal NS1 connected to the source 250, (Voltage corresponding to data erasure) to at least one of the terminals PW1 connected to the tie 245 and the terminal PW1 connected to the tie 245. [ Then, the terminal PW2 connected to the tie 275 of the second MOSFET 235 floats or applies a negative program voltage.

In the memory cell 200 selected to be erased, a positive program voltage is applied to the terminal ND2 connected to the drain 265 of the second MOSFET 235, and a ground voltage is applied to the terminal NS2 connected to the source 270. [ do. Then, the terminal connected to the drain of the second MOSFET (not shown) included in another memory cell (not shown) not selected for deletion and the terminal connected to the source float or apply the ground voltage (0 V).

In the memory cell 200 selected to be erased, the floating gate 255 of the second MOSFET 235 is charged with a negative voltage V2 according to the coupling ratio of the first MOSFET 230 and the second MOSFET 235, . A hole is accumulated in the channel region of the second MOSFET 235 by the negative voltage induced in the floating gate 255 of the second MOSFET 235 and the second MOSFET 235, A reverse bias is applied to the PN junction region with the drain region 265 of the gate electrode 265. Further, the electric field in the region of the drain 265 of the second MOSFET 235 becomes larger due to the negative voltage induced in the floating gate 255 of the two MOSFETs.

The electric field in the drain 265 region of the second MOSFET 235 creates an electron-hole pair by interband tunneling in the junction region between the drain 265 region and the channel region of the second MOSFET 235, Electrons move to the drain of the second MOSFET 235. Then, the generated holes are moved along the channel to generate electron-hole pairs by impact ionization, and holes obtained by energy are injected into the floating gate 255 of the second MOSFET 235, . (I.e., the electrons are removed by the holes)

Finally, an operation of reading data recorded in the memory cell 200 according to an embodiment will be described.

The terminal DNW connected to the diffusion region 240 in the deep well 210, the terminal ND1 connected to the drain 260 of the first MOSFET 230, the terminal NS1 connected to the source 250 and the terminal PW1 connected to the tie 245 Each of them is floated or a positive voltage is applied. A ground voltage is applied to the terminal NS2 connected to the source 270 of the second MOSFET 235 and a terminal PW2 connected to the tie 275 and a positive read voltage is applied to the terminal ND2 connected to the drain 265. [

When the memory cell 200 is programmed (that is, when electrons are injected into the floating gate 255), the second MOSFET 235 is turned off, A current does not flow between the drain 265 and the source 270 of the gate electrode 235. Further, when the data written to the memory cell 200 is deleted (that is, when electrons are removed from the floating gate 255), the second MOSFET 235 is turned on, A current flows between the drain 265 and the source 270 of the transistor 235. Since the flow of current between the source 270 and the drain 265 of the second MOSFET 235 is determined depending on whether electrons are injected into the floating gate 255 as described above, Is programmed or the data in the memory cell 200 is erased.

Up to this point, the operation of writing data to the memory cell 200 of the nonvolatile memory or erasing or reading the recorded data has been described with reference to Fig. This can be summarized as Table 1 below.

division DNW PW1 NS1 ND1 PW2 NS2 ND2 1) F-N Tunneling  Used recording operation The first memory cell + V11 or Floating 0V to + V1 + V1 + V1 - V2  ~ 0V - V2 - V2 The second memory cell + V11 or Floating 0V to + V1 + V1 + V1 - V2  ~ 0V 0V or Floating 0V or Floating 2) Write operation using channel hot electron injection The first memory cell + V11 or Floating 0V to + V3 + V3 + V3 0V 0V + V4 The second memory cell + V11 or Floating 0V to + V3 + V3 + V3 0V 0V or Floating 0V or Floating 3) F-N Tunneling  Delete operation used The first memory cell 0V or Floating - V5 - V5 - V5 0V or Floating + V6 + V6 The second memory cell 0V or Floating - V5 - V5 - V5 0V or Floating 0V or Floating 0V or Floating 4) Deletion operation using interband tunneling The first memory cell 0V or Floating - V7 - V7 - V7 Floating or
- VDNW
(0V to - V7 ) 0V + V8 The second memory cell 0V or Floating - V7 - V7 - V7 Floating or
- VDNW
(0V to - V7 ) 0V or Floating 0V or Floating 5) Read operation The first memory cell V9 or Floating + V9  or Floating + V9  or Floating + V9  or Floating 0V 0V + V10

In Table 1, the voltages V1 to V11 are voltages applied to the respective terminals of the first MOSFET 230 or the second MOSFET 235 according to the write / erase / read operation, and represent voltages of predetermined magnitudes.

The operation of writing data in the memory cell 200 can be performed through a combination of the methods 1) and 2) in Table 1. For example, data may be written to the memory cell 200 using F-N tunneling for a predetermined time and data may be written to the memory cell 200 using channel hot electron injection for another time.

The operation of deleting data recorded in the memory cell 200 can also be performed by combining one or more of the methods 3) to 5) of Table 1. For example, data recorded in the memory cell 200 may be erased using F-N tunneling for a predetermined time, and data recorded using inter-band tunneling may be erased during another time.

The nonvolatile memory described above can be fabricated as a single poly cone, and the operation of writing / erasing / reading data at a low voltage is possible. Accordingly, there is no need for a separate device capable of withstanding a high voltage such as an LDMOSFET (Laterally Diffused MOSFET), and a nonvolatile memory device can be manufactured without a separate additional process in a CMOS process.

Also, the nonvolatile memory consumes less power because FN tunneling, FN tunneling, and interband tunneling, or FN tunneling and channel hot electron injection can be used to perform data write / erase operations.

The second MOSFET 235 serving as a tunneling region serves as a transistor for reading data and the power of the second well 225 and the source 270 / drain 265 region of the tunneling region are separately It is possible to share the second well 225 with adjacent memory cells, thereby reducing the size of the nonvolatile memory.

3 is a top view illustrating the structure of a nonvolatile memory in which a plurality of memory cells are arranged in an array form according to an embodiment.

The non-volatile memory 300 of FIG. 3 shows a case where one memory cell described in FIGS. 1 and 2 is composed of a plurality of memory cells. Specifically, the non-volatile memory 300 shown in FIG. 3 includes four memory cells 310, 320, 330, and 340.

A plurality of memory cells 310, 320, 330, 340 may share a second well with one another. The plurality of memory cells 310, 330 or 320, 340 adjacent to each other above / below can share the first wells with each other. In this way, the size of the non-volatile memory including a plurality of memory cells can be reduced. Adjacent memory cells may have symmetrical structures or have the same structure.

4 to 7 are diagrams showing various examples of the structure of the first MOSFET.

In Figs. 4 to 7, the first MOSFET is assumed to be an NMOS for convenience of explanation. 4 to 7, when the same voltage is applied to the drain, source, and tie of the first MOSFET, the first MOSFET may have a MOS capacitor structure. Also, the first MOSFET may include at least one of one or more n + type diffusion regions and one or more p + type diffusion regions.

For example, referring to FIG. 4, the first MOSFET 400 may include a P + type diffusion region 420 and an n + type diffusion region 430. At this time, the floating gate 410 may overlap with the n + -type diffusion region 430 or may be formed apart from the p + -type diffusion region 430. Referring to FIG. 5, the first MOSFET 500 may include a floating gate 510 and a p + -type diffusion region 520. 6, the first MOSFET 600 includes n + -type diffusion regions 620 and p + -type diffusion regions 630 overlapping with floating gates, respectively, on both sides of the floating gate 610, The first MOSFET 700 may be comprised of a floating gate 710 and two n + type diffusion regions 720 and 730.

8 is a side view showing a structure of a nonvolatile memory in units of memory cells according to another embodiment.

8, a non-volatile memory in the memory cell 800 unit may include a first deep well 810 and a second deep well 805 and may include a first deep well 810 and a second deep well 810. [ (805) may include a first well (815) and a second well (820), respectively. In addition, the memory cell 800 may include a floating gate 875, a first MOSFET 830, and a second MOSFET 835. The first MOSFET 830 may be on the first well 815 and the second MOSFET 535 may be on the conductive second well 820.

Also, the first deep well 810 may include the same type of diffusion region 840 for the first deep well 810 tie. For example, if first deep well 810 is N type, then diffusion region 840 may also be N type. The second deep well 805 may also include the same type of diffusion region 892 for the second deep well 805 tie.

When the first MOSFET 830 is an NMOS, the first MOSFET 830 may include an N-type drain 860, an N-type source 850, and a P-type tie 845. When the second MOSFET 835 is an NMOS, the second MOSFET 835 includes an N-type drain 885, an N-type source 890, and a P-type tie 891, similar to the first MOSFET 830 . The region of the first well 815 corresponding to the first well 815 does not correspond to the first deep well 810 and is of the same type as the first deep well 810, ) May be additionally formed.

The non-volatile memory may also include at least one of the third well 825 or the diffusion region 870 between the first deep well 810 and the second deep well 805. The third well 825 or diffusion region 870 formed between the first deep well 810 and the second deep well 805 effectively separates the first deep well 810 and the second deep well 805 And stably provide the potential of the substrate.

For example, the first deep well 810 and the second deep well 805 are N-type and the first well 815, the second well 820, the third well 825, and the first deep well 810) and the second deep well 805 may be of the P type. In this case, the terminal DNW1 connected to the first deep well 810 and the DNW2 connected to the second deep well 805 in the operation of writing, erasing and reading data in the memory cell 800 included in the nonvolatile memory 1 may be applied to the deep well 810 and the second deep well 805 so that a certain voltage is not applied to the forward diode voltage.

FIG. 9 is a top view illustrating a nonvolatile memory structure of a memory cell unit according to another embodiment.

9, a nonvolatile memory in units of memory cells 900 includes a substrate 910, a conductive deep-well 920, a conductive first well 915, a conductive second well 925, a floating gate (not shown) 980), a first MOSFET 945, and a second MOSFET 950. In addition, the memory cell 900 may further include a select transistor (Selector Transistor) The first MOSFET 945 may be on the conductive first well 905 and the second MOSFET 950 may be on the conductive second well 925.

Also, the deep well 920 may include the same type of diffusion region 965 for the deep well 920 tie. If the first MOSFET 945 is an NMOS, the first MOSFET 945 may include an N-type drain 905, an N-type source 975, and a P-type tie 970. When the second MOSFET 9500 is an NMOS, the second MOSFET 950 includes an N-type drain 930, an N-type source 940, and a P-type tie 935, similar to the first MOSFET 945 . The region not corresponding to the first well 915 and the second well 925 in the region of the deep well 920 is of the same type as the deep well 920 and is of the same type as the deep well 920, (955) may be additionally formed.

The memory cell 900 included in the nonvolatile memory of FIG. 9 has a structure in which the select transistor 960 is further included compared to the memory cell of FIG. In FIG. 9, a description overlapping with that of FIG. 1 will be omitted. The select transistor 960 can make the design of the driving circuit more easy by varying the method of applying power to the memory cell during data write and erase operations.

10 is a flowchart illustrating a method of manufacturing a nonvolatile memory according to an embodiment.

First, at step 1010, a conductive deep-well may be formed on the substrate. For example, an N type deep well may be formed on a P type substrate.

In step 1020, the first well and the second well may be formed spaced apart from each other in the deep well region. Alternatively, a third well shallower than the deep well may be additionally formed without overlapping the first well region and the second well region in the deep well region.

At this time, when the non-volatile memory includes a plurality of memory cells, at least one of the first well and the second well may be shared among the plurality of memory cells. For example, memory cells included in a non-volatile memory and adjacent to each other may share a first well, a second well, or a first well and a second well. Likewise, the first memory cell and the second memory cell may share a second well.

In step 1030, a gate insulating layer may be formed over the first well and the second well, and a floating gate may be formed over the gate insulating layer. The floating gate formed on the first well and the floating gate formed on the second well may be electrically connected to each other.

Then, in step 1040, a diffusion region may be formed in the deep well, the first well, and the second well. Deep wells may include the same type of diffusion region for deep well ties. For example, if the deep well is N type, the diffusion region may also be N type.

For the first MOSFET to be formed in the first well, at least one of an n + type diffusion region and at least one p + type diffusion region may be formed in the first well. Likewise, for the second MOSFET to be formed in the second well, at least one of the n + type diffusion region and the at least one p + type diffusion region may be formed in the second well. Alternatively, a diffusion region for ties may be formed in the first well and the second well.

A terminal to which a voltage is applied may be connected to each diffusion region, and each terminal may be formed by separately forming electrical wiring, or may be formed by connecting a plurality of terminals.

At this time, the operation of writing data to the nonvolatile memory can be performed by injecting electrons into the floating gate using F-N tunneling, channel hot electron injection based on the voltages applied to the first MOSFET and the second MOSFET. In addition, the operation of deleting data recorded in the nonvolatile memory can be performed by removing electrons injected into the floating gate using F-N tunneling, interband tunneling. The operation of reading the data recorded in the nonvolatile memory can be performed by determining whether the second MOSFET is turned on or off based on the presence or absence of electrons injected into the floating gate.

For example, in step 1010 to step 1040, an N type deep well may be formed on a P type substrate. Thereafter, P-type first wells and P-type second wells isolated from each other may be formed in the N-type deep well region. An N-type third well shallower than the deep well may be additionally formed in the deep well region as an area not corresponding to the first well and the second well. Next, a gate insulating layer is formed on the first well and the second well, and a floating gate may be formed on the gate insulating layer. Next, an n + type diffusion region may be formed in the deep well region, and a p + type tie region, an n + type source region, and an n + type drain region may be formed in the first well. Also in the second well, a p + type tie region, an n + type source region, and an n + type drain region may be formed.

11 is a flowchart for explaining a method of manufacturing a nonvolatile memory according to another embodiment.

First, in step 1110, a first deep well and a second deep well may be formed on the substrate so as to be spaced apart from each other. For example, an N-type first deep well and an N-type first deep well may be formed on a substrate.

In step 1120, a first well may be formed in the first deep well region and a second well may be formed in the second deep well region. In addition, a third well may be formed in a region between the first deep well and the second deep well. The third well may be located between the first well and the second well and may have a structure electrically separated from each well.

In step 1130, a gate insulating layer may be formed over the first well and the second well, and a floating gate may be formed over the gate insulating layer. The floating gate formed on the first well and the floating gate formed on the second well may be electrically connected to each other.

Then, in step 1140, a diffusion region may be formed in the deep well, the first well, the second well, and the third well region. Deep wells may include the same type of diffusion region for deep well ties. For example, if the deep well is N type, the diffusion region may also be N type.

For the first MOSFET to be formed in the first well, at least one of an n + type diffusion region and at least one p + type diffusion region may be formed in the first well. Likewise, for the second MOSFET to be formed in the second well, at least one of the n + type diffusion region and the at least one p + type diffusion region may be formed in the second well. Alternatively, a diffusion region for ties may be formed in the first well and the second well. In addition, a p < + > -type diffusion region can be formed in the third well region.

A terminal to which a voltage is applied may be connected to each diffusion region, and each terminal may be formed by separately forming electrical wiring, or may be formed by connecting a plurality of terminals.

For example, in steps 1010 to 1040, N type first deep wells and second deep wells may be formed on a P type substrate. A first well of the P type may then be formed in the first deep well region, and a second well of the P type may be formed in the second deep well region. Then, a P-type third well may be formed between the first deep well and the second deep well. Next, a gate insulating layer is formed on the first well and the second well, and a floating gate may be formed on the gate insulating layer. Next, an n + type diffusion region may be formed in the first deep well and the second deep well region, and a p + type tie region, an n + type source region, and an n + type drain region may be formed in the first well. Also in the second well, a p + type tie region, an n + type source region, and an n + type drain region may be formed. Then, ap + -type diffusion region may be formed in the third well region.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (16)

delete delete delete delete In a non-volatile memory,
A deep well formed on the substrate;
A first well formed in the deep well region;
A second well formed in the deep well region and spaced apart from the first well;
A first MOSFET formed on the first well; And
And a second MOSFET formed on the second well
A first voltage corresponding to data writing is applied to at least one of a source region, a drain region, and a well region of the first MOSFET to write data into the memory,
A program voltage of 0 V or a negative voltage is applied to a second well region shared by the memory cell included in the nonvolatile memory and the memory cell adjacent to the memory cell,
Applying a negative program voltage to at least one of a source region and a drain region of the second MOSFET,
By controlling or floating the source region and the drain region of the second MOSFET included in the memory cell which is not selected to record the data to 0 V by tunneling to the floating gate of the second MOSFET, To be injected. In a non-volatile memory,
A deep well formed on the substrate;
A first well formed in the deep well region;
A second well formed in the deep well region and spaced apart from the first well;
A first MOSFET formed on the first well; And
And a second MOSFET formed on the second well
A first voltage corresponding to data writing is applied to at least one of a source region, a drain region, and a well region of the first MOSFET to write data into the memory,
A voltage of 0V is applied to a second well region shared by a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell,
A voltage of 0V is applied to the source region of the second MOSFET,
Applying a first voltage to a drain region of the second MOSFET,
The channel hot electrons generated in the channel region of the second MOSFET are transferred to the floating gate of the second MOSFET by controlling or floating the drain region of the second MOSFET included in the memory cell that is not selected to record the data to 0V A non-volatile memory for controlling to be implanted. In a non-volatile memory,
A deep well formed on the substrate;
A first well formed in the deep well region;
A second well formed in the deep well region and spaced apart from the first well;
A first MOSFET formed on the first well; And
And a second MOSFET formed on the second well
Applying a second voltage corresponding to data erasure to at least one of a source region, a drain region and a well region of the first MOSFET to erase data written in the memory,
A voltage of 0V is applied to a second well region shared by a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell,
Applying a positive program voltage in at least one of a source region and a drain region of the second MOSFET,
Volatile memory that controls electrons to be removed by tunneling from the floating gate of the second MOSFET by controlling or floating the source and drain regions of the second MOSFET included in the memory cell that is not selected by erasing the data to 0 V, Memory. In a non-volatile memory,
A deep well formed on the substrate;
A first well formed in the deep well region;
A second well formed in the deep well region and spaced apart from the first well;
A first MOSFET formed on the first well; And
And a second MOSFET formed on the second well
Applying a second voltage corresponding to data erasure to at least one of a source region, a drain region and a well region of the first MOSFET to erase data written in the memory,
Applying or floating a negative program voltage to a second well region shared by a memory cell included in the nonvolatile memory and a memory cell adjacent to the memory cell,
A voltage of 0V is applied to the source region of the second MOSFET,
Applying a positive program voltage to the drain region of the second MOSFET,
A negative voltage is induced in the floating gate of the second MOSFET by controlling or floating the drain region of the second MOSFET included in the memory cell which is not selected by erasing the data to 0 V, Wherein a hole formed by the impact ionization is injected into the floating gate of the second MOSFET in the non-volatile memory. 9. The method according to any one of claims 5 to 8,
Wherein the first MOSFET comprises:
At least one of at least one n + type diffusion region and at least one p + type diffusion region. 9. The method according to any one of claims 5 to 8,
A select transistor formed on the second well,
And a nonvolatile memory.
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