JP6783447B2 - Data writing method for non-volatile semiconductor storage device - Google Patents

Description

The present invention relates to a data writing method for a non-volatile semiconductor storage device.

As a conventional non-volatile semiconductor storage device, a non-volatile semiconductor storage device in which MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory transistors are arranged in a matrix is known (see, for example, Patent Document 1). In such a non-volatile semiconductor storage device, data is written by injecting a charge into the charge storage layer, while data is erased by extracting the charge in the charge storage layer.

In practice, when injecting charge into the charge storage layer, a low voltage write voltage is applied from the bit line to the wells of the memory transistor and a high charge charge storage gate voltage is applied to the gate electrode via the selection transistor. Then, the charge is injected into the charge storage layer by the quantum tunnel effect generated by the potential difference between the well and the gate electrode.

In such a conventional non-volatile semiconductor storage device, a memory gate line to which a high voltage charge storage gate voltage is applied is shared by a plurality of memory cells. Therefore, the memory gate voltage for injecting charge into the charge storage layer of the write selection memory cell is also applied to the write non-selection memory cell sharing the memory gate line.

In order to prevent charge from being injected into the charge storage layer of the write-unselected memory cell, a high write-blocking voltage is applied from the bit line to the well of the memory transistor via the selection transistor, and the well and gate are used. The potential difference between the electrodes is small, and as a result, the quantum tunneling effect is prevented.

Japanese Unexamined Patent Publication No. 2011-129816

As described above, in the conventional non-volatile semiconductor storage device, in order to prevent charge injection into the charge storage layer of the write-unselected memory cell, a high voltage is applied from the bit line to the well in accordance with the high voltage memory gate voltage. It was necessary to apply a write blocking voltage. Therefore, in a memory cell having such a configuration, it is necessary to thicken the selection gate insulating film of the selection transistor connected to the bit line so as to withstand a high write-blocking voltage, and the high-speed operation can be performed accordingly. There was a problem that it was difficult to realize.

Therefore, the present invention has been made in consideration of the above points, and an object of the present invention is to propose a data writing method of a non-volatile semiconductor storage device capable of realizing higher speed operation than before.

In order to solve such a problem, in the data writing method of the non-volatile semiconductor storage device according to the present invention, the first selection transistor, the memory transistor provided with the charge storage layer, and the second selection transistor are connected in series in this order to form a matrix. A bit line shared by a plurality of arranged memory cells, a memory cell column, and connected to the drain region of the first selection transistor, and a memory cell row, and the first selection of the first selection transistor. The first selection gate wire connected to the gate electrode, the second selection gate wire connected to the second selection gate electrode of the second selection transistor, and the source line connected to the source region of the second selection transistor. A data writing method for a non-volatile semiconductor storage device including a memory gate wire connected to a memory gate electrode of the memory transistor, which is necessary for injecting a charge into the charge storage layer by a quantum tunnel effect. In a write-non-selective memory cell in which a charge storage gate voltage is applied from the memory gate line to the memory gate electrode and no charge is injected into the charge storage layer, the voltage applied to the bit line and the first selection gate line causes the charge storage gate voltage. The first selection transistor is turned off to cut off the connection between the memory transistor and the bit line, and the second selection transistor is turned off by the voltage applied to the source line and the second selection gate line. By cutting off the connection between the memory transistor and the source line, a depleted layer is formed in the memory well immediately below the memory gate electrode, and the quantum tunnel effect does not occur between the memory gate electrode and the memory well. The voltage difference is characterized by preventing charge injection into the charge storage layer.

According to the present invention, since writing by the quantum tunnel effect is prevented by forming a depletion layer in the memory well of the memory transistor, the bit line, the source line and the first-choice gate line are not constrained by the charge storage gate voltage. And the voltage applied to the 2nd selection gate line can be reduced to the voltage value that can turn the 1st selection transistor and the 2nd selection transistor on and off, so that the 1st selection transistor and the 2nd selection transistor can be operated accordingly. The thickness of the gate insulating film can be reduced, and higher speed operation can be realized than before.

It is a circuit diagram which shows the circuit structure of the non-volatile semiconductor storage device of this invention, and is the table which showed the voltage applied to each part in the 1st data writing method. It is sectional drawing which shows the side sectional structure of the memory cell. It is a circuit diagram which shows the circuit structure of the non-volatile semiconductor storage device of this invention, and is the table which showed the voltage applied to each part in the 2nd data writing method. It is a circuit diagram which shows the circuit structure of the non-volatile semiconductor storage device of this invention, and is the table which showed the voltage applied to each part in the data batch writing method.

Hereinafter, modes for carrying out the present invention will be described. The description will be given in the order shown below.
<1. Overall configuration of non-volatile semiconductor storage device>
<2. Detailed configuration of memory cells>
<3. First data writing method>
3-1. Write selection memory cell 3-2. Write non-select memory cell sharing a write selection gate line 3-3. Write non-selected memory cells that share a write-selected bit line 3-4. Write-unselected memory cells connected to write-unselected gate lines and write-unselected bit lines <4. Various operations in non-volatile semiconductor storage devices>
<5. Actions and effects>
<6. Second data writing method>
<7. About carrier exclusion operation>
<8. Data batch writing method>

(1) Overall Configuration of Non-Volatile Semiconductor Storage Device FIG. 1 shows the configuration of the non-volatile semiconductor storage device 1 according to the present invention. As an example, memory cells 2a, 2b, 2c, and 2d are arranged in a matrix to provide a memory. The non-volatile semiconductor storage device 1 in which the cell array is configured is shown. The non-volatile semiconductor storage device 1 is one for each memory cell row in which the memory cells 2a, 2c (2b, 2d) are arranged in one direction (for example, the column direction) among these memory cells 2a, 2b, 2c, 2d. A book bit line BL1 (BL2) is shared, and a predetermined bit line voltage can be uniformly applied to each bit line BL1 and BL2 by the bit line voltage application circuit 10. Further, in the non-volatile semiconductor storage device 1, one first selection is made for each memory cell row in which memory cells 2a, 2b (2c, 2d) are arranged in the other direction (in this case, the row direction) intersecting one direction. The gate line DGL1 (DGL2) is shared, and a predetermined first-selection gate voltage can be uniformly applied to each of the first-selection gate lines DGL1 and DGL2 by the first-selection gate voltage application circuit 11.

Further, in the case of this embodiment, in the non-volatile semiconductor storage device 1, one memory gate line MGL, one second selection gate line SGL, and one source line SL are all memory cells 2a. , 2b, 2c, 2d are shared, a predetermined memory gate voltage is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and a predetermined memory gate voltage is applied to the second selection gate line SGL by the second selection gate voltage application circuit 14. The second selection gate voltage of the above is applied, and a predetermined source voltage can be applied to the source line SL by the source voltage application circuit 15.

In this embodiment, one memory gate line MGL, one second selection gate line SGL, and one source line SL are shared by all memory cells 2a, 2b, 2c, and 2d. However, the present invention is not limited to this, and the memory gate line and the second memory gate line and the second memory cell line are provided for each memory cell row in which the memory cells 2a and 2b (2c, 2d) are arranged in other directions (row directions), respectively. The selection gate line and the source line may be shared.

In this non-volatile semiconductor storage device 1, for example, a memory cell array in which memory cells 2a, 2b, 2c, and 2d are arranged in a matrix is arranged in one memory well MPW made of P type, and a substrate voltage application circuit 17 is used. A predetermined substrate voltage can be applied to the memory well MPW. Here, since these memory cells 2a, 2b, 2c, and 2d all have the same configuration, the following description will be given mainly focusing on the memory cells 2a in the first row and first column.

In this case, the memory cell 2a includes a first-select transistor ST1, a second-select transistor ST2, and a memory transistor MT connected in series between the first-select transistor ST1 and the second-select transistor ST2. The bit line BL1 is connected to the drain region at one end of the first selection transistor ST1, and the source line SL is connected to the source region at one end of the second selection transistor ST2. A drain region and a source region are not provided between the first-selection transistor ST1 and the memory transistor MT, or between the second-selection transistor ST2 and the memory transistor MT.

Here, the first selection gate electrode DG is provided in the first selection transistor ST1, and the first selection gate wire DGL1 is connected to the first selection gate electrode DG. The first selection transistor ST1 is turned on by the voltage difference between the bit line voltage applied from the bit line BL1 to the drain region and the first selection gate voltage applied from the first selection gate line DGL1 to the first selection gate electrode DG. -Can operate off. In practice, when the potential difference between the first-select gate voltage and the bit line voltage is larger than the threshold voltage of the first-select transistor ST1, the first-select transistor ST1 is turned on and the potential difference between the first-select gate voltage and the bit line voltage. When is equal to or less than the threshold voltage of the first-selection transistor ST1, the first-selection transistor ST1 is turned off.

When the first-select transistor ST1 is turned on, the drain region and the channel layer on the surface of the memory well MPW where the memory transistor MT is arranged are electrically connected, and the bit line voltage from the bit line BL1 is the memory transistor. It is applied to the channel layer of MT. On the other hand, when the first-select transistor ST1 is turned off, the electrical connection between the drain region and the channel layer of the memory transistor MT is cut off, and the bit line voltage is applied from the bit line BL1 to the channel layer. Be blocked.

The second-selection transistor ST2 is provided with the second-selection gate electrode SG, and the second-selection gate wire SGL is connected to the second-selection gate electrode SG. The second selection transistor ST2 is turned on by the voltage difference between the source voltage applied from the source line SL to the source region and the second selection gate voltage applied from the second selection gate line SGL to the second selection gate electrode SG. Can work off. In practice, when the potential difference between the second selection gate voltage and the source voltage is larger than the threshold voltage of the second selection transistor ST2, the second selection transistor ST2 is turned on and the potential difference between the second selection gate voltage and the source voltage is the second. When the voltage is equal to or lower than the threshold voltage of the 2 selection transistor ST2, the 2nd selection transistor ST2 is turned off.

When the second selection transistor ST2 is turned on, the source region and the channel layer of the memory transistor MT are electrically connected. On the other hand, when the second selection transistor ST2 is turned off, the electrical connection between the source region and the channel layer of the memory transistor MT is cut off, and the application of the source voltage from the source line SL to the channel layer is blocked. Will be done.

The memory transistor MT is provided with a charge storage layer EC sandwiched between the lower gate insulating film and the upper gate insulating film, and a memory gate electrode MG arranged on the upper gate insulating film. The memory gate line MGL is connected to MG. The memory transistor MT is configured so that the voltage difference between the memory gate electrode MG and the memory well MPW causes the charge to be injected into the charge storage layer EC by the quantum tunnel effect, or the charge is extracted from the charge storage layer EC. Has been done.

(2) Detailed Configuration of Memory Cell Here, FIG. 2 is a cross-sectional view showing a side sectional configuration of the memory cell 2a. In practice, as shown in FIG. 2, for example, in the memory cell 2a, a P-type memory well MPW is formed on a silicon substrate 20 via an N-type deep well layer DNW, and a MONOS type memory transistor MT is formed. The memory gate structure 4 to be configured, the first-selection gate structure 5 constituting the first-selection transistor ST1 of the N-type MOS (Metal-Oxide-Semiconductor), and the second-selection transistor ST2 of the N-type MOS are also configured. A second-choice gate structure 6 is formed on the memory well MPW.

On the surface of the memory well MPW, there are a drain region 31 at one end of the first selection gate structure 5 and to which the bit line BL1 is connected, and a source line SL at one end of the second selection gate structure 6. It is formed with a predetermined distance from the connected source area 34. In the case of this embodiment, the concentration of N-type impurities in the drain region 31 and the source region 34 is set to 1.0E21 / cm ³ or more, while the surface region where the channel layer CH of the memory well MPW is formed ( For example, the P-type impurity concentration in the region from the surface to 50 [nm]) is set to 1.0E19 / cm ³ or less, preferably 3.0E 18 / cm ³ or less.

The memory gate structure 4 has a lower gate insulating film 24a made of an insulating material such as silicon oxide (SiO, SiO ₂ ) on the memory well MPW between the drain region 31 and the source region 34, for example, silicon nitride (Si ₃ N _4). ), A charge storage layer EC made of silicon nitride (SiON), alumina (Al ₂ O ₃ ), etc., an upper gate insulating film 24b also made of an insulating material, and a memory gate electrode MG, which are laminated in this order.

In the memory gate structure 4, a wall-shaped side wall spacer 28a made of an insulating material such as silicon oxide (SiO, SiO ₂ ) is formed along one side wall, and the first choice is made through the side wall spacer 28a. A gate structure 5 is provided adjacent to the gate structure 5. The side wall spacer 28a provided between the memory gate structure 4 and the first-choice gate structure 5 has a predetermined film thickness, and the memory gate structure 4 and the first-choice gate structure 5 are formed. It is configured so that the withstand voltage between 5 and 5 can be secured.

The first-select gate structure 5 has a first-select gate insulating film 30 and a first-select gate made of an insulating material such as silicon oxide (SiO, SiO ₂ ) on the memory well MPW between the side wall spacer 28a and the drain region 31. It has a structure in which electrodes DG are laminated in order. The film thickness of the first-select gate insulating film 30 is 9 [nm] or less, preferably 3 [nm] or less.

Here, when the film thickness of the side wall spacer 28a is less than 5 [nm], when a predetermined voltage is applied to the memory gate electrode MG and the first-select gate electrode DG, the side wall spacer 28a may have a withstand voltage defect. On the other hand, when the thickness of the side wall spacer 28a exceeds 40 [nm] and the distance between the memory gate electrode MG and the first selection gate electrode DG exceeds 40 [nm], the memory gate electrode MG and the first selection gate electrode The resistance in the memory well MPW (for example, the region from the surface to 50 [nm] (surface region)) increases between the DGs, and the read current becomes difficult to flow between the memory transistor MT and the first-choice transistor ST1 when reading data. ..

Therefore, in the case of this embodiment, it is desirable that the distance between the memory gate electrode MG and the first-choice gate electrode DG is formed to be 5 [nm] or more and 40 [nm] or less, and the film thickness of the side wall spacer 28a. It is desirable that the film is formed at 5 [nm] or more and 40 [nm] or less.

Further, a side wall spacer 28b made of an insulating material such as silicon oxide (SiO, SiO ₂ ) is also formed on the other side wall of the memory gate structure 4, and the second selection gate structure is formed through the side wall spacer 28b. 6 are provided adjacent to each other. The side wall spacer 28b provided between the memory gate structure 4 and the second selection gate structure 6 is also formed to have the same film thickness as one side wall spacer 28a, and the memory gate structure 4 and the second selection gate are formed. It is configured so that the withstand voltage between the structure 6 and the structure 6 can be ensured.

The second-select gate structure 6 has a second-select gate insulating film 33 and a second-select gate made of an insulating material such as silicon oxide (SiO, SiO ₂ ) on the memory well MPW between the side wall spacer 28b and the source region 34. It has a structure in which electrodes SG are laminated in order. The film thickness of the second-select gate insulating film 33 is 9 [nm] or less, preferably 3 [nm] or less.

Here, also between the memory gate electrode MG and the second selection gate electrode SG, as in the case between the memory gate electrode MG and the first selection gate electrode DG described above, there is a problem of withstand voltage failure of the side wall spacer 28b, and the memory transistor MT and the first selection gate electrode SG. It is desirable that the transistors are formed at a distance of 5 [nm] or more and 40 [nm] or less because there is a risk that the read current will drop between the two selection transistors ST2. Therefore, in the case of this embodiment, it is desirable that the film thickness of the side wall spacer 28b is also formed to be 5 [nm] or more and 40 [nm] or less.

Further, the first-selection gate insulating film 30 and the second-selection gate insulating film 33 are films composed of the same layer, and the side wall spacer 28a and the side wall spacer 28b are films composed of the same layer. Since the first-select gate insulating film 30 and the second-select gate insulating film 33, and the side wall spacer 28a and the side wall spacer 28b are films formed by different manufacturing processes and composed of different layers, the first-select gate insulating film is formed. The film thicknesses of 30 and the second-select gate insulating film 33 are set to the film thickness for obtaining the desired operating speed, and the film thicknesses of the side wall spacer 28a and the side wall spacer 28b are the film thickness for ensuring the desired dielectric strength. Can be set to. Preferably, it is set so as to satisfy the relationship of [the film thickness of the side wall spacer 28a and the side wall spacer 28b> the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33].

The memory cells 2a, 2b, 2c, 2d having such a configuration are formed by a general semiconductor manufacturing process using photolithography technology, film formation technology such as oxidation and CVD, etching technology, ion implantation method, and the like. Since it can be done, the description thereof is omitted here.

(3) First Data Writing Method Next, in the non-volatile semiconductor storage device 1 shown in FIG. 1, a charge is injected into the charge storage layer EC of the memory cell 2a in the first row and the first column, and the memory cell is concerned. The case where data is written only to 2a and data is not written to other memory cells 2b, 2c, 2d will be described below. Table T1 shown in FIG. 1 shows the voltage values applied to each part when data is written to the memory cell 2a in the first row and first column.

In this case, the first row in which the memory cell (hereinafter referred to as write selection memory cell) 2a for writing data is arranged is referred to as a selected row, and the memory cell in which data is not written (hereinafter referred to as write non-selection memory cell). The second line where 2c and 2d are placed is called a non-selected line. Further, the first column in which the write memory cells 2a are arranged is called a selected column, and the second column in which the write non-selected memory cells 2b and 2d are arranged is called a non-selected column.

As shown in FIG. 1, in the non-volatile semiconductor storage device 1, the charge storage gate voltage V _PROG (for example, 12 [V]) is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and the substrate voltage application circuit 17 A substrate voltage (eg, 0 [V]) can be applied to the memory well MPW. As a result, not only the memory cell (also called a write selection memory cell) 2a that injects charge into the charge storage layer EC, but also the memory cell (also called a write non-selection memory cell) 2b, 2c that does not inject charge into the charge storage layer EC. Also in 2d, a high voltage charge storage gate voltage V _{PRO G} can be applied to the memory gate electrode MG. The charge storage gate voltage V _PROG may be various voltage values as long as the charge can be injected into the charge storage layer EC by the quantum tunnel effect in the memory transistor MT of the write selection memory cell 2a.

Further, in the non-volatile semiconductor storage device 1, a gate-off voltage of 0 [V] is applied to the second-selection gate line SGL by the second-selection gate voltage application circuit 14, and the first of all memory cells 2a, 2b, 2c, 2d. 2 The gate-off voltage can be applied to the selective gate electrode. Further, the source voltage application circuit 15 applies a source off voltage of 0 [V] to the source line SL, and the source voltage can be applied to the source regions of all the memory cells 2a, 2b, 2c, and 2d.

Further, the write selection gate voltage Vdd _DG is applied to the first selection gate line (also called the write selection gate line) DGL1 to which the write selection memory cell 2a is connected by the first selection gate voltage application circuit 11, and the write non-selection memory. A write non-selective gate voltage of 0 [V] can be applied to the other first-select gate line (also called write-non-selective gate line) DGL2 to which only cells 2c and 2d are connected. In this case, the write selection gate voltage Vdd _DG is used for CPU (Central Processing Unit), ASIC (Application-Specific Integrated Circuit), logic circuit, input / output circuit, and other peripheral circuits that are mixed with the non-volatile semiconductor storage device 1. The power supply voltage Vdd can be the same as the operating voltage, and can be set to, for example, greater than 0 [V] and 3 [V] or less, preferably 0.5 [V] or more and 1.5 [V] or less.

By the bit line voltage application circuit 10, 0 [V] is applied as the write selection bit line voltage to the bit line (also called the write selection bit line) BL1 to which the write selection memory cell 2a is connected, and the write non-selection memory cell 2b, A write blocking voltage Vdd _BL can be applied to the bit line (also called a write-unselected bit line) BL2 to which only 2d is connected. The write blocking voltage Vdd _BL can be set to, for example, greater than 0 [V] and 3 [V] or less, preferably 0.5 [V] or more and 1.5 [V] or less, similar to the write selection gate voltage Vdd _DG described above.

The write selection gate voltage Vdd _DG and the write blocking voltage Vdd _BL are the write selection gate voltage Vdd _DG so that the first selection gate electrode DG is turned off in the write non-selection memory cell sharing the write selection gate line described later. The potential difference between and the write blocking voltage Vdd _BL is set to a voltage equal to or less than Vth _ST1, which is the threshold voltage of the first-select transistor ST1. That is, it is set so as to satisfy the relationship of Vdd _BL ≥ (Vdd _DG -Vth _ST1 ). Here, Vth _ST1 is set to, for example, 0 [V] to 1.0 [V]. Note that Vth _ST2 , which is the threshold voltage of the second selection transistor ST2 described later, is also set to, for example, 0 [V] to 1.0 [V] like Vth _ST1 .

When the write operation is executed in the non-volatile semiconductor storage device 1, the channel potential at the time when the write operation is started may change depending on the charge accumulation state in the memory cells 2a, 2b, 2c, 2d. There is. Therefore, before the writing operation, the potential of the bit line BL1, BL2 or the source line SL is set to, for example, 0 [V], and the first selection gate line DGL1, DGL2 or the second selection gate electrode SG is set to, for example, 1.5 [V]. With at least one of the 1-selection transistor ST1 and the 2nd-selection transistor ST2 turned on, and the memory gate electrode MG being set to, for example, 1.5 [V], the channel potentials of the memory cells 2a, 2b, 2c, and 2d are set to bit lines BL1, BL2. Alternatively, it is more desirable to add an operation of aligning the potential of the source line SL. In that case, after aligning the channel potentials, the first-selection gate line DGL1, DGL2 or the second-selection gate line SGL may be returned to a voltage of 0 [V] before proceeding to the writing operation.

(3-1) Write Selection Memory Cell An operation in the case of injecting charge into the charge storage layer EC of the write selection memory cell 2a will be described.
A charge storage gate voltage V _PROG (eg 12 [V]) is applied from the memory gate line MGL to the memory gate electrode MG, and a substrate voltage (eg 0 [V]) is applied to the memory well MPW.

A gate-off voltage of 0 [V] is applied from the second-select gate line SGL to the second-select gate electrode SG, and a source-off voltage of 0 [V] is applied from the source line SL to the source region 34. Transistor ST2 is turned off. As a result, a source-side non-conducting region is formed in the memory well MPW directly under the second-select gate structure 6 (FIG. 2), and the source region 34 and the channel layer CH of the memory well MPW directly under the memory gate structure 4 are formed. The electrical connection can be cut off and the voltage application from the source line SL to the channel layer CH can be blocked.

On the other hand, the write selection gate voltage Vdd _DG (for example, 1.5 [V]) is applied from the write selection gate line DGL1 to the first selection gate electrode DG, and 0 [V] is applied from the write selection bit line BL1 to the drain region 31. The write selection bit line voltage is applied, and the first selection transistor ST1 is turned on. As a result, a drain-side conduction region is formed in the memory well MPW directly under the first-select gate structure 5 (FIG. 2), and the drain region 31 and the channel layer CH directly under the memory gate structure 4 are electrically connected. , 0 [V] write selection bit line voltage can be applied to the channel layer CH of the memory transistor MT.

Thus, in the write-selective memory cell 2a, a large voltage difference (for example, 12 [V]) is generated between the memory gate electrode MG and the channel layer CH, and the quantum tunnel effect generated by this causes a charge in the charge storage layer EC. Can be injected and data can be written to the memory transistor MT.

(3-2) Write Non-Selected Memory Cell Sharing a Write Selected Gate Line Next, a write non-selected memory cell 2b of a selected row sharing a write selected memory cell 2a and a write selected gate line DGL1 will be described. The charge storage gate voltage V _PROG is also applied to the memory gate electrode MG from the memory gate line MGL to the write non-selection memory cell 2b, and the substrate voltage is applied to the memory well MPW.

A gate-off voltage of 0 [V] is applied from the second-select gate line SGL to the second-select gate electrode SG, and a source-off voltage of 0 [V] is applied from the source line SL to the source region 34. Transistor ST2 is turned off. As a result, a source-side non-conducting region is formed in the memory well MPW directly under the second-select gate structure 6, and the source region 34 is electrically connected to the channel layer CH of the memory well MPW directly under the memory gate structure 4. Can be blocked and voltage application from the source line SL to the channel layer CH can be blocked.

Further, in the first selection transistor ST1 of the write non-selection memory cell 2b, the write selection gate voltage Vdd _DG (for example, 1.5 [V]) is applied from the write selection gate line DGL1 to the first selection gate electrode DG, and the write is performed. A write blocking voltage Vdd _BL (for example, 1.5 [V]) is applied from the non-selected bit line BL2 to the drain region 31 to turn it off. As a result, a drain-side non-conducting region is formed in the memory well MPW directly under the first-select gate structure 5, and the electrical connection between the drain region 31 and the channel layer CH directly under the memory gate structure 4 is cut off. The voltage application from the write non-selection bit line BL2 to the channel layer CH can be blocked.

In this way, in the write-unselected memory cell 2b of the selected row, both the first-selection transistor ST1 and the second-selection transistor ST2 on both sides of the memory transistor MT are turned off, so that the channel layer formed in the memory transistor MT is formed. The electrical connection between the CH and the source line SL and the bit line BL2 is cut off, and the channel layer CH is in a floating state. Since the charge storage gate voltage V _PROG is applied to the memory gate electrode MG, the depletion layer D is formed in the memory well MPW around the channel layer CH.

The potential of the channel layer CH is an insulating film composed of three layers: the capacitance of the depleted layer D (hereinafter referred to as the depleted layer capacitance) C1, the upper gate insulating film 24b, the charge storage layer EC, and the lower gate insulating film 24a. Capacity (hereinafter referred to as gate insulating film capacity) increases due to capacity coupling with C2.
Thus, in the write-unselected memory cell 2b, the potential difference between the memory gate electrode MG and the channel layer CH can be reduced to prevent charge injection into the charge storage layer EC due to the quantum tunneling effect.

The potential increase of the channel layer CH due to the capacitance coupling between the depletion layer capacitance C1 and the gate insulating film capacitance C2 will be described below. When the depletion layer D is formed in the memory well MPW around the channel layer CH, it can be considered that the gate insulating film capacitance C2 and the depletion layer capacitance C1 are connected in series, and the channel layer CH can be regarded as a configuration. The following equation (1) holds for the channel potential Vch.

Channel potential Vch = (charge storage gate voltage V _PROG − substrate voltage) × {C2 / (C1 + C2)}… (1)

For example, when the gate insulating film capacity C2 is three times the capacity of the depletion layer capacity C1, the substrate voltage of the memory well MPW is 0 [V] and the charge storage gate voltage V _PROG is 12 [in this embodiment. Since it is V], the channel potential Vch is 9 [V] as shown in the following equation (2).

Channel potential Vch = (12 [V] −0 [V]) × {3 ・ C1 / (C1 + 3 ・ C1)} = 9 [V]… (2)

As a result, in the write-unselected memory cell 2b, even if a charge storage gate voltage of 12 [V] is applied to the memory gate electrode MG, the channel potential Vch of the channel layer CH becomes 9 [V], so that the memory gate The voltage difference between the electrode MG and the channel layer CH becomes as small as 3 [V], and as a result, charge injection into the charge storage layer EC can be prevented without causing the quantum tunnel effect.

In addition to this, in the write-unselected memory cell 2b, the area of the memory well MPW between the memory gate structure 4 and the first-select gate structure 5 has an impurity concentration such as a drain area 31 or a source area 34. Since the high impurity diffusion region is not formed, the depletion layer D can be surely formed around the channel layer CH formed around the surface of the memory well MPW, and the depletion layer D is the first selection from the channel layer CH. It can prevent the channel potential Vch from reaching the gate insulating film 30.

As a result, in the first-selection gate structure 5, even if the first-selection gate insulating film 30 is thinly formed in accordance with the low-voltage write-selection gate voltage Vdd _DG and the write-blocking voltage Vdd _BL , the channel potential Since Vch is blocked by the depleted layer D, it is possible to prevent dielectric breakdown of the first-select gate insulating film 30 due to the channel potential Vch.

Further, the memory well MPW region between the memory gate structure 4 and the second-select gate structure 6 is not formed with an impurity diffusion region having a high impurity concentration such as a drain region 31 and a source region 34. Therefore, the depletion layer D can be surely formed around the channel layer CH formed around the surface of the memory well MPW, and the depletion layer D reaches the channel potential Vch from the channel layer CH to the second selection gate insulating film 33. Can be blocked.

As a result, even in the second-selection gate structure 6, even if the thickness of the second-selection gate insulating film 33 is reduced according to the low-voltage gate-off voltage and source-off voltage, the channel potential Vch is blocked by the depletion layer D. Therefore, it is possible to prevent dielectric breakdown of the second-select gate insulating film 33 due to the channel potential Vch.

In the above-described embodiment, the case where the write selection gate voltage Vdd _DG and the write blocking voltage Vdd _BL are both the same voltage as 1.5 [V] has been described, but the write selection gate voltage Vdd _DG and the write blocking voltage have been described. The Vdd _BL may have a different voltage as long as the first-choice transistor ST1 is turned off. Assuming that the threshold voltage of the first-select transistor ST1 is Vth _ST1 , the first-select transistor ST1 is turned off if the condition of Vdd _BL ≥ (Vdd _DG -Vth _ST1 ) is satisfied.

Here, when the write blocking voltage Vdd _BL is made larger than (Vdd _DG -Vth _ST1 ) (Vdd _BL > (Vdd _DG -Vth _ST1 )), the voltage difference between Vdd _BL and (Vdd _DG -Vth _ST1 ). , The apparent threshold voltage of the first-choice transistor ST1 increases, the leakage current between the channel layer CH and the drain region 31 decreases accordingly, and the off operation characteristics can be improved. As a result, the depletion layer D can be stabilized in the write non-selective memory cell 2b, and the disturb resistance can be improved.

Incidentally, Vdd _BL is preferably Vdd _BL ≧ Vdd _DG, more preferably in the range of 3 times the voltage of _{Vdd DG ~Vdd DG (3 · Vdd} DG), Vdd 1.5 times the voltage of _DG (1.5 · Vdd _DG) is Especially preferable. If Vdd _BL exceeds 3 times Vdd _DG , a new disturb may occur due to a junction leak between the memory well MPW directly under the first-select gate electrode DG and the drain region 31. Therefore, it is desirable that Vdd _BL is 3 times or less of Vdd _DG .

(3-3) Write / Non-Selected Memory Cell Sharing Write Selected Bit Line Next, the write / non-selected memory cell 2c of the selected column sharing the write selected memory cell 2a and the write selected bit line BL1 will be described below. The charge storage gate voltage V _PROG is also applied to the memory gate electrode MG from the memory gate line MGL to the write non-selection memory cell 2c, and the substrate voltage is applied to the memory well MPW.

The operation of the second selection transistor ST2 of the write non-selection memory cell 2c is the same as the operation of the second selection transistor ST2 of the write non-selection memory cell 2b described above, the second selection transistor ST2 is turned off, and the source area 34 Then, the electrical connection of the memory well MPW directly under the memory gate structure 4 to the channel layer CH can be cut off, and the voltage application from the source line SL to the channel layer CH can be blocked.

Further, in the first selection transistor ST1 of the write non-selection memory cell 2c, a write non-selection gate voltage of 0 [V] is applied from the write non-selection gate line DGL2 to the first selection gate electrode DG, and a write selection bit line is applied. A write selection bit line voltage of 0 [V] is applied from BL1 to the drain region 31 to turn it off. As a result, a drain-side non-conducting region is formed in the memory well MPW directly under the first-select gate structure 5, and the electrical connection between the drain region 31 and the channel layer CH directly under the memory gate structure 4 is cut off. The voltage application from the write selection bit line BL1 to the channel layer CH can be blocked.

As a result, even in the write non-selective memory cell 2c, both the first-selection transistor ST1 and the second-selection transistor ST2 on both sides of the memory transistor MT are turned off, so that the channel layer CH formed in the memory transistor MT and the source The electrical connection with the line SL and the bit line BL1 is cut off, and the depletion layer D is formed in the memory well MPW around the channel layer CH. Thus, in the write-unselected memory cell 2c, the channel potential Vch of the channel layer CH surrounded by the depletion layer D rises and the voltage difference between the memory gate electrode MG and the channel layer CH becomes smaller, resulting in a quantum tunneling effect. Can be prevented from injecting charge into the charge storage layer EC without generating.

(3-4) Write non-selected memory cells connected to write non-selected gate lines and write non-selected bit lines Next, write non-selected memory cells connected to write non-selected gate lines DGL2 and write non-selected bit lines BL2. 2d will be described below. The charge storage gate voltage V _PROG is also applied from the memory gate line MGL to the memory gate electrode MG to the write non-selection memory cell 2d arranged in the non-selected row and in the non-selected column, and the substrate voltage is applied to the memory well MPW. Is applied.

The operation of the second selection transistor ST2 of the write non-selection memory cell 2d is the same as the operation of the second selection transistor ST2 of the write non-selection memory cells 2b and 2c described above, the second selection transistor ST2 is turned off, and the source The electrical connection between the region 34 and the channel layer CH of the memory well MPW directly under the memory gate structure 4 can be cut off, and the voltage application from the source line SL to the channel layer CH can be blocked.

Further, in the first selection transistor ST1 of the write non-selection memory cell 2d, a write non-selection gate voltage of 0 [V] is applied from the write non-selection gate line DGL2 to the first selection gate electrode DG, and the write non-selection bit is applied. A write blocking voltage Vdd _BL (for example, 1.5 [V]) is applied from the line BL2 to the drain region 31 to turn it off. As a result, a drain-side non-conducting region is formed in the memory well MPW directly under the first-select gate structure 5, and the electrical connection between the drain region 31 and the channel layer CH directly under the memory gate structure 4 is cut off. The voltage application from the write non-selection bit line BL2 to the channel layer CH can be blocked.

As a result, even in the write non-selective memory cell 2d, both the first-selection transistor ST1 and the second-selection transistor ST2 on both sides of the memory transistor MT are turned off, so that the channel layer CH formed in the memory transistor MT and the source The electrical connection with the line SL and the bit line BL2 is cut off, and the depletion layer D is formed in the memory well MPW around the channel layer CH. Thus, in the write-unselected memory cell 2d, the channel potential Vch of the channel layer CH surrounded by the depletion layer D rises and the voltage difference between the memory gate electrode MG and the channel layer CH becomes smaller, resulting in a quantum tunneling effect. Can be prevented from injecting charge into the charge storage layer EC without generating.

(4) Various Operations in the Non-Volatile Semiconductor Storage Device Next, in the non-volatile semiconductor storage device 1 of the present invention, for example, a data reading operation of whether or not a charge is stored in the charge storage layer EC of the memory cell 2a, and The data erasing operation of extracting the charge from the charge storage layer EC of the memory cells 2a, 2b, 2c, and 2d will be described in order.

In the data read operation of the memory cell 2a, the voltage of Vdd _SGREAD (greater than 0 [V] and less than 3 [V], for example, voltage of 1.5 [V], is applied to the second selection gate line SGL by the second selection gate voltage application circuit 14. ) Is applied, and the source voltage application circuit 15 applies a voltage of 0 [V] to the source line SL, so that the second-select transistor ST2 of each memory cell 2a, 2b, 2c, 2d is turned on. , The source line SL and the channel layer CH of the memory transistor MT are electrically connected. Further, 0 [V] is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and 0 [V] is applied to the memory well MPW by the substrate voltage application circuit 17.

Further, the bit line voltage application circuit 10 reads the bit line BL1 connected to the memory cell (hereinafter, also referred to as the read selection memory cell) 2a for reading the data, and the read selection voltage Vdd _READ (3 [V] larger than 0 [V]]. The following voltage (for example, voltage of 1.5 [V]) is precharged, while memory cells that do not read data (hereinafter, also referred to as read-unselected memory cells) 2b, 2d are connected to the bit line BL2 0 [ Apply the read-out non-selective voltage of V]. Further, the voltage of Vdd _DGREAD (greater than 0 [V] and 3 [V] or less, for example, 1.5 [V]] is connected to the first-select gate line DGL1 to which the read-selection memory cell 2a is connected by the first-select gate voltage application circuit 11. Voltage) is applied, and a voltage of 0 [V] is applied to the first-selection gate line DGL2 to which only read-unselected memory cells 2c and 2d are connected.

As a result, when the charge is accumulated in the charge storage layer EC in the read selection memory cell 2a (when data is written), the memory transistor MT is turned off, and the bit line BL1 and the source line SL are connected. The electrical connection is cut off. At this time, in the read non-selection memory cell 2c that shares the bit line BL1 with the read selection memory cell 2a, a gate-off voltage of 0 [V] is applied to the first selection gate line DGL2, and the first selection transistor ST1 is in the off state. Therefore, the charge storage state in the charge storage layer EC of the memory transistor MT does not affect the read selection voltage Vdd _READ of the bit line BL1. As a result, in the non-volatile semiconductor storage device 1, the read selection voltage Vdd _READ of the bit line BL1 to which the read selection memory cell 2a is connected is maintained as it is.

On the other hand, when the charge is not accumulated in the charge storage layer EC in the read selection memory cell 2a (when no data is written), the memory transistor MT is turned on and the bit line is passed through the read selection memory cell 2a. BL1 and the source line SL are electrically connected. As a result, in the non-volatile semiconductor storage device 1, the read selection voltage Vdd _READ of the bit line BL1 connected to the read selection memory cell 2a decreases. Thus, in the non-volatile semiconductor storage device 1, whether or not the charge is accumulated in the charge storage layer EC of the read selection memory cell 2a by detecting whether or not the read selection voltage Vdd _READ of the bit line BL1 has changed. Data read operation can be executed.

Next, the data erasing operation of extracting the charge in the charge storage layer EC of the memory cells 2a, 2b, 2c, 2d in the non-volatile semiconductor storage device 1 will be described. In this case, in the non-volatile semiconductor storage device 1, the erasing gate voltage V _ERASE (for example, -12 [for example, -12 [, for example, -12 [, for example,] V]) is applied, and the substrate voltage of 0 [V] is applied to the memory well MPW by the substrate voltage application circuit 17, so that the charge in the charge storage layer EC is extracted toward the memory well MPW and the data is obtained. Can be erased.

(5) Actions and Effects In the above configuration, in the non-volatile semiconductor storage device 1, bit lines BL1 and BL2 (hereinafter, hereinafter, BL2) are used for each memory cell sequence in which a plurality of memory cells 2a, 2b, 2c, and 2d are arranged in one direction. These are collectively referred to as bit line BL), and the first selection gate line DGL1, DGL2 is provided for each memory cell row arranged in the other direction in which a plurality of memory cells 2a, 2b, 2c, 2d intersect one direction. (Hereinafter, these are simply referred to as the first-select gate line DGL), and it is necessary to inject charge into the charge storage layer EC of a plurality of memory cells 2a, 2b, 2c, 2d by the quantum tunnel effect. The charge storage gate voltage V _PROG is applied by the memory gate line MGL.

The write selection memory cell 2a is selected by the bit line BL in the column direction and by the first selection gate line DGL in the row direction. A write selection bit line voltage 0 [V] is applied to the bit line BL of the selected column, and a write blocking voltage Vdd _BL is applied to the bit line BL of the non-selected string. The write selection gate voltage Vdd _DG is applied to the first selection gate line DGL of the selected line, and the write non-selection gate voltage 0 [V] is applied to the first selection gate line DGL of the non-selection line.

Only in the write selection memory cell 2a, the potential difference between the write selection gate voltage Vdd _DG and the write selection bit line voltage 0 [V] becomes + Vdd _DG , and the first selection transistor ST1 is turned on so that the write selection bit line voltage is turned on. By applying 0 [V] to the channel layer CH of the memory transistor MT, the charge can be injected into the charge storage layer EC by the quantum tunnel effect.

On the other hand, in the write-unselected memory cells 2b, 2c, 2d, the potential difference between the voltage applied to the first-select gate line DGL and the voltage applied to the bit line BL is Vdd _DG −Vdd _BL , 0 [V], It became −Vdd _BL , the first selection transistor ST1 was turned off, and the connection between the memory transistor MT and the bit line BL was cut off. At this time, in the write non-selection memory cells 2b, 2c, 2d, the potential difference between the voltage applied to the second selection gate line SGL and the voltage applied to the source line SL becomes 0 [V], and the second selection The transistor ST2 was turned off, and the connection between the memory transistor MT and the source line SL was cut off.

As a result, in the write-unselected memory cells 2b, 2c, 2d, a depletion layer D is formed in the memory well MPW directly under the memory gate electrode MG of the memory transistor MT, and a quantum tunnel effect is formed between the memory gate electrode MG and the memory well MPW. As a voltage difference that does not occur, charge injection into the charge storage layer EC is prevented.

Therefore, in the non-volatile semiconductor storage device 1, a high write-blocking voltage is applied in order to make the voltage difference between the memory gate electrode MG and the memory well MPW by the poor layer D during the data writing operation so that the quantum tunnel effect does not occur. The voltage applied to the bit line BL, the source line SL, the first selection gate line DGL and the second selection gate line SGL without being constrained by the charge storage gate voltage V _PROG is applied to the first selection transistor ST1 and The voltage value at which the second-choice transistor ST2 can operate on and off can be reduced. The film thickness of the first-selection gate insulating film 30 of the first-selection transistor ST1 and the second-selection gate insulating film 33 of the second-selection transistor ST2 can be reduced by that amount, and the film thickness is reduced as much as before. Can also achieve high speed operation.

(6) Second Data Writing Method Next, the second data writing method will be described below. FIG. 3, which is shown by assigning the same reference numerals to the parts corresponding to those in FIG. 1, shows the voltage in each part in the second data writing method with respect to the circuit configuration of the non-volatile semiconductor storage device 1 shown in FIG. , Table T2 which summarizes the voltage of each part of the second data writing method is shown. The second data writing method is different from the above-described embodiment in that the voltage applied to the source line SL during the data writing operation is the source side power supply voltage Vdd _SL, and other non-volatile semiconductors. Since the configuration of the storage device 1, the data reading operation, and the data erasing operation are the same as those in the above-described embodiment, the description thereof will be omitted. Here, the data writing operation will be focused on and described below.

Here, the source side power supply voltage Vdd _SL applied to the source line SL during the data writing operation is 0 [V] which is the gate-off voltage of the second-selection gate line SGL so that the second-selection transistor ST2 is turned off. ] And the source side power supply voltage Vdd _SL are set to a voltage equal to or less than Vth _ST2, which is the threshold voltage of the second selection transistor ST2. That is, it is set so as to satisfy the relationship of (Vdd _SL ≧ -Vth _ST2 ). The source side power supply voltage Vdd _SL is preferably equal to or higher than the voltage value applied to the second selection gate line SGL, and more preferably larger than the voltage value applied to the second selection gate line SGL.

The power supply voltage Vdd _SL on the source side can be, for example, the same power supply voltage Vdd as the operating voltage of various peripheral circuits such as a CPU, ASIC, logic circuit, input / output circuit, etc., which are mixed with the non-volatile semiconductor storage device 1. It can be set to be larger than 0 [V] and 3 [V] or less, preferably 0.5 [V] or more and 1.5 [V] or less. Further, the source side power supply voltage Vdd _SL may be the same voltage as the write selection gate voltage Vdd _DG or the write blocking voltage Vdd _BL , or may be a different voltage.

For example, the source-side power supply voltage Vdd _SL is tailored to Vdd _BL in the embodiment described above, preferably Vdd _SL ≧ Vdd _DG, 3 times the voltage (3 · Vdd _DG) is more preferably from Vdd _DG ~Vdd _DG, Vdd A voltage 1.5 times that of _DG (1.5 Vdd _DG ) is particularly preferable. If Vdd _SL exceeds 3 times Vdd _DG , a new disturb may occur due to a junction leak between the memory well MPW directly under the 2nd selection gate electrode SG and the source region 34. Therefore, it is desirable that Vdd _SL is 3 times or less of Vdd _DG .

In the above configuration, even under the voltage conditions shown in Table T2 shown in FIG. 3, the charge can be injected into the charge storage layer EC in the write selection memory cell 2a, and the charge can be injected in the write non-selection memory cells 2b, 2c, 2d. It is possible to prevent the injection of electric charge into the storage layer EC. In the write-unselected memory cells 2c (2b, 2d), the first-select transistor ST1 is turned off by the voltage applied to the bit line BL1 (BL2) and the first-select gate line DGL2 (DGL1, DGL2), and the memory transistors MT and bits The connection with the line BL1 (BL2) is cut off, and the voltage applied to the source line SL and the second selection gate line SGL also turns off the second selection transistor ST2, cutting off the connection between the memory transistor MT and the source line SL. Will be done.

As a result, in the non-volatile semiconductor storage device 1, in the write non-selective memory cell 2c (2b, 2d), a depletion layer D is formed in the memory well MPW directly below the memory gate electrode MG of the memory transistor MT, and the memory gate electrode MG and the memory gate electrode MG Charge injection into the charge storage layer EC is blocked as a voltage difference between the memory well MPWs where the quantum tunnel effect does not occur.

In the non-volatile semiconductor storage device 1, it is necessary to apply a high write blocking voltage in order to create a voltage difference between the memory gate electrode MG and the memory well MPW due to the poor layer D during the data writing operation so that the quantum tunnel effect does not occur. The voltage applied to the bit line BL, the source line SL, the first selection gate line DGL and the second selection gate line SGL, without being constrained by the charge storage gate voltage V _PROG , is applied to the first selection transistors ST1 and second. The voltage value at which the selected transistor ST2 can operate on and off can be reduced. The film thickness of the first-selection gate insulating film 30 of the first-selection transistor ST1 and the second-selection gate insulating film 33 of the second-selection transistor ST2 can be reduced by that amount, and the film thickness is reduced as much as before. Can also achieve high speed operation.

At this time, in the second data writing method, the voltage applied to the source line SL is set to the source side power supply voltage Vdd _SL, which is larger than the value obtained by subtracting Vth _ST2 from the gate-off voltage applied to the second selection gate electrode SG. By doing so (by setting Vdd _SL > -Vth _ST2 ), the voltage difference between Vdd _SL and -Vth _ST2 and the apparent threshold voltage of the second-select transistor ST2 become higher, and the channel layer CH and source area 34 by that amount. Leakage current between and is reduced, and off-operation characteristics can be improved. As a result, the depletion layer D can be stabilized in the write non-selective memory cells 2b, 2c, 2d, and the disturb resistance can be improved.

In particular, in the second data writing method, when the voltage difference between the gate-off voltage applied to the second selection gate electrode SG and the source side power supply voltage Vdd _SL becomes large, the memory transistors in the write non-selection memory cells 2b, 2c, 2d The depletion layer D formed in the memory well MPW of MT can be further stabilized, and the disturb resistance can be improved.

(7) Carrier Elimination Operation In the non-volatile semiconductor storage device 1 according to the present invention, each data writing operation is executed in the first data writing method, the second data writing method, and the third data writing method described above. The carrier exclusion operation described later may be executed.

In this case, as a carrier exclusion operation, in the non-volatile semiconductor storage device 1 of the present invention, in each memory cell 2a, 2b, 2c, 2d, a carrier forming a channel layer is present in the memory well MPW facing the memory gate electrode MG. The carrier is excluded from the region (hereinafter referred to as the channel layer forming carrier region), and the memory well MPW directly under the memory gate electrode MG does not form the channel layer in the write non-selected memory cells 2b, 2c, 2d. It is designed so that the depletion layer D can be formed.

In the non-volatile semiconductor storage device 1, when the carrier exclusion operation is executed, the first selection gate lines DGL1 and DGL2 have a gate carrier exclusion voltage Vdd _DGELIM (voltage greater than 0 [V] and 3 [V] or less, for example, 1.5 [V]. ] Voltage) is applied, and 0 [V] bit line carrier exclusion voltage is applied to the bit lines BL1 and BL2. As a result, the first-selection transistors ST1 of each memory cell 2a, 2b, 2c, and 2d are turned on, and a drain-side conduction region is formed on the surface of the memory well MPW directly below the first-selection gate electrode DG. In each memory cell 2a, 2b, 2c, 2d, the drain region 31 to which the bit lines BL1 and BL2 are connected and the channel layer forming carrier region of the memory well MPW directly under the memory gate electrode MG are electrically connected.

Further, in the case of this embodiment, in the non-volatile semiconductor storage device 1, the second selection gate line SGL also has a gate carrier exclusion voltage Vdd _SGELIM (0 [V] and a voltage of 3 [V] or less, for example, 1.5 [V]. ] Voltage) is applied, and 0 [V] source carrier exclusion voltage is applied to the source line SL. As a result, the second selection transistor ST2 of each memory cell 2a, 2b, 2c, 2d is turned on, and a source-side conduction region is formed on the surface of the memory well MPW directly below the second selection gate electrode SG. In each memory cell 2a, 2b, 2c, 2d, the source region 34 to which the source line SL is connected and the channel layer forming carrier region of the memory well MPW directly under the memory gate electrode MG are electrically connected.

In addition to this, in the non-volatile semiconductor storage device 1, a substrate carrier exclusion voltage of 0 [V], which is the same as the bit line carrier exclusion voltage and the source carrier exclusion voltage, is applied to the memory well MPW and the memory gate line MGL is stored. A gate carrier exclusion voltage Vdd _ELIM (eg -2 [V]) is applied. Here, the memory gate carrier exclusion voltage Vdd _ELIM applied to the memory gate electrode MG is defined based on the threshold voltage (Vth) at which the channel layer is formed in the memory well MPW directly under the memory gate electrode MG, and the data. A voltage value outside the threshold voltage (Vth) range that is displaced between the writing state and the data erasing state, and the channel layer is not formed when applied to the memory gate electrode MG. Has been selected for.

As a result, in each memory cell 2a, 2b, 2c, 2d, the carriers (electrons in this case) induced in the channel layer forming carrier region are transferred to the channel by the memory gate carrier exclusion voltage applied to the memory gate electrode MG. The layering carrier region can lead to the drain region 31 and / or the source region 34 and expel carriers from the channel layering carrier region.

In the case of this embodiment, the memory gate structure 4 in each memory cell 2a, 2b, 2c, 2d is formed on the P-type memory well MPW to form an N-type MOS transistor structure. Therefore, in each memory cell 2a, 2b, 2c, 2d, the threshold voltage (Vth) in the data writing state is set to, for example, 2.0 [V], and the threshold voltage (Vth) in the data erasing state is set. For example, it can be set to -1.5 [V]. In this case, the carrier exclusion voltage for expelling carriers from the channel layer forming carrier region may be selected, for example, to -2.0 [V] or less. As a result, in each memory cell 2a, 2b, 2c, 2d, the threshold voltage in the memory transistor MT is applied to the memory gate electrode MG regardless of whether or not the data is written or erased. The memory gate carrier exclusion voltage guides the carriers in the channel layer forming carrier region to the drain region 31 and the source region 34 conductively connected to the channel layer forming carrier region, and expels the carriers from the channel layer forming carrier region. The channel layer can be left unformed.

As described above, the threshold voltage in the memory transistor MT is when electrons (charges) are accumulated in the charge storage layer EC (when data is written) and when electrons are not accumulated in the charge storage layer EC (or It is different from when (the holes are accumulated) (when the data is erased). That is, the threshold voltage when electrons are accumulated in the charge storage layer EC is higher (deeper) than the threshold voltage when electrons are not accumulated (or holes are accumulated) in the charge storage layer EC. Become. Therefore, the memory gate carrier exclusion voltage is higher than the threshold voltage based on the lower (shallow) threshold voltage when electrons are not accumulated (or holes are accumulated) in the charge storage layer EC. It is selected with a low (shallow) voltage value so that carriers can be expelled from the channel layer forming carrier region to the drain region 31 and the source region 34 regardless of whether or not the charge is stored in the charge storage layer EC. ..

Thus, in each memory cell 2a, 2b, 2c, 2d, each memory cell 2a, 2b, 2c, 2d is in a depleted state by applying the memory gate carrier exclusion voltage set as described above to the memory gate electrode MG. Even if it is, the carriers induced in the channel layer forming carrier region of the memory well MPW directly under the memory gate electrode MG are excluded from the channel layer forming carrier region, and the channel layer is not formed and the empty layer D is removed. Can be in a formed state.

In the above-described embodiment, the case where both the first selection transistor ST1 and the second selection transistor ST2 are turned on during the carrier exclusion operation has been described, but the present invention is not limited to this, and the first selection is not limited to this. Only one of the transistor ST1 and the second-choice transistor ST2 may be turned on. In this case, when either the first selection transistor ST1 or the second selection transistor ST2 is turned on, either the drain region 31 or the source region 34 and the channel layer forming carrier region are electrically connected. The carriers in the channel layer forming carrier region can be sent to the drain region 31 or the source region 34, and the carriers can be excluded from the channel layer forming carrier region.

In the case of this embodiment, after the non-volatile semiconductor storage device 1 executes such a carrier exclusion operation, the above-mentioned "(3) first data writing method" and "(6) second data writing method" are described above. Or "(7) Third data writing method" to execute the data writing operation. For example, in the write non-selective memory cells 2b, 2c, 2d, the first-select transistor ST1 and the second-select transistor ST2 are turned off during the data write operation, as in each of the above-described embodiments, and the memory gate of the memory transistor MT is turned off. A depletion layer D is formed in the memory well MPW directly under the electrode MG, and charge injection into the charge storage layer EC is prevented as a voltage difference between the memory gate electrode MG and the memory well MPW where the quantum tunnel effect does not occur.

Here, the voltage difference Vono between the memory gate electrode MG and the memory well MPW surface in the write-unselected memory cells 2b, 2c, 2d can be obtained from the following equation. Note that q is the elementary charge, Na is the acceptor concentration of the memory well MPW, and Cono is the capacitance of the upper gate insulating film 24b, the charge storage layer EC, and the lower gate insulating film 24a (hereinafter, also referred to as the memory gate capacitance). Call). Further, ε ₁ is the relative permittivity of the material (silicon in this embodiment) forming the memory well MPW, ε ₀ is the permittivity of the vacuum, Vfb is the flat band voltage, and V g is the charge storage gate voltage V _{PRO G.}

In the case of this embodiment, the voltage difference Vono on the surface of the memory gate electrode MG and the memory well MPW in the write non-selective memory cells 2b, 2c, 2d has Vfd of 0 [V], Vg of 12 [V], and Na. 2.0E17 [cm ^-3 ], the thickness of the upper gate insulating film 24b is 2 [nm], the thickness of the charge storage layer EC is 12 [nm], and the thickness of the lower gate insulating film 24a is 3.5 [nm]. In the case, it becomes about 2 [V].

As a result, in the memory transistor MT in each write non-selective memory cell 2b, 2c, 2d, even if a charge storage gate voltage of 12 [V] is applied to the memory gate electrode MG, the surface of the memory gate electrode MG and the memory well MPW The voltage difference Vono becomes about 2 [V], and the large voltage difference required for the quantum tunnel effect to occur between the memory gate electrode MG and the memory well MPW surface does not occur, preventing charge injection into the charge storage layer EC. obtain.

Therefore, even when such a carrier exclusion operation is executed, the quantum tunnel effect is generated between the memory gate electrode MG and the memory well MPW by the vacancy layer D during the data writing operation, as in the above-described embodiment. Since the voltage difference does not occur, it is not necessary to apply a high write blocking voltage, and the bit line BL, source line SL, first-choice gate line DGL and second are not constrained by the charge storage gate voltage V _PROG . The voltage applied to the selection gate line SGL can be reduced to a voltage value at which the first selection transistor ST1 and the second selection transistor ST2 can operate on and off. The film thickness of the first-selection gate insulating film 30 of the first-selection transistor ST1 and the second-selection gate insulating film 33 of the second-selection transistor ST2 can be reduced by that amount, and the film thickness is reduced as much as before. Can also achieve high speed operation.

(8) Data batch writing method Next, a data batch writing method for batch writing data to each memory cell 2a, 2b, 2c, 2d in the non-volatile semiconductor storage device 1 will be described below. FIG. 4, which is shown by assigning the same reference numerals to the parts corresponding to those in FIG. 1, shows the voltage in each part in the data batch writing method for the circuit configuration of the non-volatile semiconductor storage device 1 shown in FIG. Table T4 which summarizes the voltage of each part of the batch writing method is shown. In this data batch writing method, data is written to memory cells 2a, 2b, 2c, 2d in a batch by using the source line SL and the second selection gate line SGL common to the memory cell array (memory mat). Can be done.

In this case, in this case, in the non-volatile semiconductor storage device 1, as shown in FIG. 4, the charge storage gate voltage V _PROG is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and the memory is stored by the substrate voltage application circuit 17. A substrate voltage of 0 [V] is applied to the well MPW. Further, the write selection source voltage of 0 [V] is applied to the source line SL shared by the write selection memory cells 2a, 2b, 2c, and 2d by the source voltage application circuit 15, and the write selection is performed by the second selection gate voltage application circuit 14. 2nd selection gate line shared by memory cells 2a, 2b, 2c, 2d SGL to 2nd selection gate side power supply voltage Vdd _SG (voltage larger than 0 [V] and less than 3 [V], for example, voltage of 1.5 [V] ) Is applied.

As a result, in the non-volatile semiconductor storage device 1, the second selection transistors ST2 of the write selection memory cells 2a, 2b, 2c, and 2d are collectively turned on by the voltage applied to the source line SL and the second selection gate line SGL. Then, the memory transistor MT and the source line SL are electrically connected. As a result, in each write selection memory cell 2a, 2b, 2c, 2d, a source-side conduction region is formed in the memory well MPW directly under the second selection gate electrode SG, and the source region 34 and the memory well directly under the memory gate electrode MG are formed. The MPW is electrically connected, and a write selection source voltage of 0 [V] is applied to the channel layer CH of the memory transistor MT.

Thus, in the write-selective memory cells 2a, 2b, 2c, 2d, a large voltage difference (eg, 12 [V]) occurs between the memory gate electrode MG and the channel layer CH, and the resulting quantum tunnel effect charges the charge. Charges may be injected into the storage layer EC, and data may be written to the memory transistor MT.

At this time, in the non-volatile semiconductor storage device 1, a gate-off voltage of 0 [V] is applied to each of the first-select gate lines DGL1 and DGL2 by the first-selection gate voltage application circuit 11, and each bit is applied by the bit-line voltage application circuit 10. 0 [V] or write blocking voltage Vdd _BL ((voltage greater than 0 [V] and less than 3 [V], for example, voltage 1.5 [V])) is applied to the lines BL1 and BL2. As a result, in each write selection memory cell 2a, 2b, 2c, 2d, the first selection transistor ST1 is turned off, and the electrical connection between the memory transistor MT and the bit lines BL1 and BL2 is cut off.

In the above-described embodiment, as shown in FIG. 4, 0 [V] is applied to the first selection gate lines DGL1 and DGL2 by the first selection gate voltage application circuit 11 in the data batch writing. Then, 0 [V] or write blocking voltage Vdd _BL is applied to both bit lines BL1 and BL2 by the bit line voltage application circuit 10, or 0 [V] is applied to one of the bit lines BL1 and BL2 and the other is written. Even if the blocking voltage Vdd _BL is applied and 0 [V] and the write blocking voltage Vdd _BL are mixed, the first selection transistor ST1 can be turned off, and the bit line by the bit line voltage application circuit 10 The voltage control of BL1 and BL2 can be eliminated.

However, the present invention is not limited to this, and by applying 0 [V] to each bit line BL1 and BL2 by the bit line voltage application circuit 10, each of the first selection gate lines DGL1 from the first selection gate voltage application circuit 11 Apply 0 [V] or write selection gate voltage Vdd _DG to both, DGL2, or apply 0 [V] to one of the first selection gate lines DGL1 and DGL2 and apply write selection gate voltage Vdd _DG to the other. 0 [V] and the write selection gate voltage Vdd _DG may be mixed. When the write selection gate voltage Vdd _DG is applied to the first selection gate lines DGL1 and DGL2, the write selection source voltage of 0 [V] is applied to the channel layer CH of the memory transistor MT and 0 [V]. The voltage of is applied from each bit line BL1 and BL2 to the channel layer CH of the memory transistor MT, and the charge is injected into the charge storage layer EC by the quantum tunnel effect. When 0 [V] is applied to the 1st selection gate lines DGL1 and DGL2, the 1st selection transistor ST1 can be turned off, and the write selection source voltage of 0 [V] is the channel of the memory transistor MT. When applied to the layer CH, the charge is injected into the charge storage layer EC by the quantum tunneling effect. Therefore, if 0 [V] is applied to each bit line BL1 and BL2, the voltage control of the first-selection gate lines DGL1 and DGL2 by the first-selection gate voltage application circuit 11 can be eliminated.

In the non-volatile semiconductor storage device 1, the data batch write operation can be executed as a series of data erasure operations before the data erasure operation. As a result, in the non-volatile semiconductor storage device 1, even if the data erasing operation is repeatedly executed, the data is written to all the memory cells 2a, 2b, 2c, 2d before the data erasing operation, so that each memory cell 2a, 2b The threshold voltages of, 2c and 2d can be made uniform, and the threshold voltage after data erasure can be prevented from being unnecessarily lowered. Therefore, in the write non-selected memory cells 2b, 2c, 2d during the data write operation performed after the data erase operation, the depleted layer D formed in the memory well MPW of each memory transistor MT is the memory cells 2a, 2b. It is formed evenly and stably without variation between 2, 2c and 2d, and the disturb resistance can be improved in the entire memory mat.

1 Non-volatile semiconductor storage device
2a, 2b, 2c, 2d memory cells
30 First-choice gate insulating film
31 Drain area
33 Second choice gate insulating film
34 Source area
BL1, BL2 bit line
D depletion layer
DG 1st choice gate electrode
DGL1, DGL2 1st selection gate line
EC charge storage layer
MGL memory gate line
MPW memory well
MG memory gate electrode
MT memory transistor
SG 2nd choice gate electrode
SGL 2nd choice gate line
SL source line
ST1 1st choice transistor
ST2 2nd choice transistor

Claims (5)

A plurality of memory cells connected in series in the order of a first-select transistor, a memory transistor having a charge storage layer, and a second-select transistor and arranged in a matrix.
A bit line shared by a memory cell sequence and connected to the drain region of the first-select transistor,
A first-selection gate line shared by the memory cell row and connected to the first-selection gate electrode of the first-selection transistor,
The second selection gate wire connected to the second selection gate electrode of the second selection transistor and
The source line connected to the source region of the second selection transistor and
A data writing method for a non-volatile semiconductor storage device including a memory gate wire connected to a memory gate electrode of the memory transistor.
The charge storage gate voltage required to inject charge into the charge storage layer by the quantum tunnel effect is applied from the memory gate line to the memory gate electrode .
Write-unselected memory cells in the same row and different columns as the write-selected memory cells that inject charge into the charge storage layer, write-non-selected memory cells in the same column and different rows as the write-selected memory cells, and the write In a write-unselected memory cell that is in a different row and column than the selected memory cell
The voltage applied to the bit line to which only the write-unselected memory cell is connected is set to be equal to or higher than the voltage value applied to the first-select gate line connected to the write-selective memory cell.
The voltage applied to the first-select gate line to which only the write-unselected memory cell is connected is set to 0 [V].
By setting the voltage applied to the source line to which the write-unselected memory cell is connected to be equal to or higher than the voltage value applied to the second-select gate line.
Thereby disconnects the previous SL first selection transistor the memory transistor by the OFF state and the bit line, the pre-Symbol second select transistor is in an OFF state in the memory transistor connected between said source line By blocking, a depleted layer is formed in the memory well immediately below the memory gate electrode, and the charge is injected into the charge storage layer as a voltage difference between the memory gate electrode and the memory well so that the quantum tunnel effect does not occur. A method of writing data in a non-volatile semiconductor storage device, which is characterized by blocking the data. The data writing method for a non-volatile semiconductor storage device according to claim 1 , wherein 0 [V] is applied to the source line and the second selection gate line. A source side power supply voltage Vdd _SL larger than 0 [V] is applied to the source line.
The data writing method for a non-volatile semiconductor storage device according to claim 1 , wherein 0 [V] is applied to the second selection gate line. A voltage of Vdd or less and 3 [V] or less is applied to the bit line, the first selection gate line, the source line, and the second selection gate line in the non-volatile semiconductor storage device. The data writing method of the non-volatile semiconductor storage device according to any one of claims 1 to 3 , wherein the data is written. Before injecting charge into the charge storage layer of the write-selection memory cell,
While the first selection transistor and / or the second selection transistor of the memory cell is turned on, the carrier exclusion voltage defined with reference to the threshold voltage for forming the channel layer in the memory well directly under the memory gate electrode is set. By being applied to the memory gate electrode, carriers in the memory well directly under the memory gate electrode are sent out to the drain region and / or the source region, and the memory well directly under the memory gate electrode is used. The data writing method for a non-volatile semiconductor storage device according to any one of claims 1 to 4 , wherein carriers are eliminated.

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