JP2006310564A - Nonvolatile semiconductor memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique which can improve the read-out characteristic of a memory cell, while controlling the drive capability deterioration of a gate electrode (word line), and to provide a technique which can improve the read-out characteristic of a memory cell, by reducing the leak current of the space region between word lines. <P>SOLUTION: Two or more floating gate electrodes 13 and gate electrodes 14 are formed on a semiconductor substrate 1. Further, a shield electrode 18 is formed in a space region between the word lines between floating gate electrodes 13. 0 V or negative voltage is applied to this shield electrode 18. An interface of shield insulation film 16 and semiconductor substrate 1 is made lower than an interface of a gate insulation film 8 and the semiconductor substrate 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing technique thereof, and more particularly to a technique effective when applied to reading of a memory cell.

  2. Description of the Related Art In recent years, a flash memory, which is one of nonvolatile semiconductor memory devices, is excellent in portability and impact property, and can be erased collectively in an electrical manner. Therefore, in recent years, a memory device for small portable information devices such as portable personal computers and cellular phones. As demand grows rapidly. Bit cost reduction is an important factor for the expansion of the market, and in addition to miniaturization of memory cells, this bit cost reduction is being promoted by a multi-value storage technology that stores two or more bits in one cell.

  However, as the miniaturization progresses, the interval between the floating gate electrode of the memory cell to be read and the adjacent floating gate electrode becomes narrow, and the capacitive coupling ratio between the two cannot be ignored. As a result, the threshold value of the memory cell to be read is (read cell threshold value change) = (change in write state of adjacent cell) × (adjacent floating state) in accordance with the write state or erase state of the adjacent floating gate electrode. The problem of changing only by the capacitive coupling ratio between the gate electrodes becomes obvious.

  This threshold value change may cause the memory cell to be read erroneously. In particular, this is an important problem for a multi-value memory in which the threshold distribution is narrowed and each threshold distribution is narrowly set.

For example, as described in Japanese Patent Application Laid-Open No. 2003-188287 (Patent Document 1), a technique for the change in the threshold value is, for example, polysilicon having an impurity added between floating gate electrodes of a memory cell transistor. For example, a conductive material is embedded and fixed to the potential of the source region or the drain region.
JP 2003-188287 A

  However, in the memory cell described in Patent Document 1 described above, the following problems become apparent as the memory cell becomes finer.

  For example, in Patent Document 1, when the height of the shield gate electrode in the word line space region is higher than the height of the floating gate electrode and further covers the gate electrode (word line), the word line and the shield The capacitance between the gate electrode is increased. For this reason, there is a problem that the driving performance of the word line is deteriorated and the reading performance of the memory cell is deteriorated. That is, by forming the shield gate electrode around the word line, the parasitic capacitance around the word line is increased, so that the time constant (voltage rise time) of the word line is increased and the driving capability is lowered.

  As the memory cell is miniaturized, an increase in leakage current in the word line space region can be cited as a factor that degrades read characteristics. The leakage current needs to be sufficiently lower than the read determination current, and when it exceeds the determination current, the memory cell cannot be read. In an AND type memory cell in which the memory cell array is connected in parallel, since the space between the source / drain diffusion layers becomes narrower as the size of the memory cell advances and the floating gate electrode width becomes narrower, leakage current in the word line space region becomes apparent. There is a possibility of becoming.

  Regarding the leakage current in the word line space region, even if a high concentration impurity region is formed in the same region, the spread of the drain depletion layer cannot be ignored as the memory cell is miniaturized, and the leakage current flows and the memory cell is read. Characteristics deteriorate.

  An object of the present invention is to provide a technique capable of improving the read characteristics of a memory cell while suppressing a decrease in driving capability of a gate electrode (word line).

  Another object of the present invention is to provide a technique capable of reducing the leakage current in the word line space region and improving the read characteristics of the memory cell.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A nonvolatile semiconductor memory device according to the present invention is a nonvolatile semiconductor memory device having a plurality of memory cells on a semiconductor substrate, the memory cell comprising: (a) a source region and a drain region formed on the semiconductor substrate; (B) a gate insulating film formed on the semiconductor substrate; (c) a floating gate electrode formed on the gate insulating film; and (d) an insulating film formed on the floating gate electrode; (E) a gate electrode formed on the insulating film, and a shield electrode adjacent to the floating gate electrode is formed between the memory cells via a sidewall insulating film, and the shield electrode The height of is lower than the height of the gate electrode.

  A method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device in which a plurality of memory cells are formed on a semiconductor substrate, and (a) an auxiliary gate insulating film is formed on the semiconductor substrate. (B) forming a conductive film on the auxiliary gate insulating film, (c) forming a first insulating film on the conductive film, and (d) patterning the conductive film. Forming an auxiliary gate electrode; (e) forming a first sidewall insulating film on the sidewall of the auxiliary gate electrode; and (f) forming a gate insulating film on the exposed semiconductor substrate. (G) forming a first conductive film on the gate insulating film; (h) forming an insulating film on the first conductive film and the first insulating film; and (i) the insulating film. Forming a second conductive film thereon; (j) before Forming a second insulating film on the second conductive film; (k) patterning the second conductive film to form a gate electrode; and (l) patterning the first conductive film to form a floating gate. Forming an electrode; (m) forming a second sidewall insulating film on side surfaces of the gate electrode and the floating gate electrode; and (n) forming a shield insulating film on the exposed semiconductor substrate; (O) forming a third conductive film on the shield insulating film and the second insulating film; and (p) patterning the third conductive film to form a shield electrode adjacent to the floating gate electrode. A step of forming the shield electrode with a height lower than that of the gate electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the height of the shield electrode is made lower than the height of the gate electrode, it is possible to improve the read characteristics of the memory cell while suppressing a decrease in the driving capability of the gate electrode.

  In addition, since the interface between the shield insulating film formed under the shield electrode and the semiconductor substrate is lower than the interface between the gate insulating film formed under the floating gate electrode and the semiconductor substrate, the open between the memory cells is formed. Leakage current in the field can be reduced. For this reason, the read characteristics of the memory cell can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In order to make the drawing easier to see, even a plan view may be hatched.

(Embodiment 1)
FIG. 1 is a partial top view showing an example of the nonvolatile semiconductor memory device according to the first embodiment. FIGS. 2 to 5 are AA line, BB line, and C line in FIG. 1, respectively. It is sectional drawing cut | disconnected by the -C line | wire and DD line | wire.

  1, the nonvolatile semiconductor memory device according to the first embodiment has a plurality of auxiliary gate electrodes 6 extending in the Y-axis direction. By applying, for example, a positive voltage to the auxiliary gate electrode 6, a channel is formed in the semiconductor region immediately below the auxiliary gate electrode 6. The channel region is formed along the auxiliary gate electrode 6 and connected to the diffusion layer 19 serving as a source region or a drain region. Therefore, the channel region under the auxiliary gate electrode 6 becomes a source region or a drain region. That is, the auxiliary gate electrode 6 is provided in order to form a source region and a drain region composed of a channel region extending in the Y-axis direction.

  A plurality of gate electrodes (word lines) 14 are formed in a direction crossing the auxiliary gate electrode 6, that is, a direction extending in the X-axis direction. Then, under the gate electrode 14 between the auxiliary gate electrodes 6, nonvolatile memory cells C1 and C2 are formed. That is, the nonvolatile memory cells C1 and C2 are formed so as to be connected in parallel between the same source region and drain region (AND type memory cell). Information can be stored in each of the nonvolatile memory cells C1 and C2. A shield electrode 18 is formed between the plurality of gate electrodes 14 (word line space region, open field) so as to be parallel to the gate electrodes 14.

  Next, in FIG. 2 (a cross-sectional view taken along the line AA in FIG. 1), a p-type well 2 is formed on the semiconductor substrate 1, and an auxiliary gate insulating film 3 is formed on the p-type well 2. An auxiliary gate electrode 6 is formed therethrough. A channel region (not shown) is formed under the auxiliary gate electrode 6 during driving, and this channel region becomes a source region or a drain region. A floating gate electrode 13 is formed between the auxiliary gate electrodes 6 via a gate insulating film 8. The floating gate electrode 13 and the auxiliary gate electrode 6 are insulated from each other by a side wall insulating film (first side wall insulating film) 7 formed on the side wall of the auxiliary gate electrode 6. An insulating film 5 is formed on the auxiliary gate electrode 6, and an insulating film 10 is formed on the insulating film 5 and the floating gate electrode 13. A gate electrode 14 is formed on the insulating film 10.

  The floating gate electrode 13 functions as a charge storage film that stores charges. That is, when electrons are accumulated in the floating gate electrode 13, the threshold value (voltage) at which a channel is formed increases. For this reason, when a read voltage is applied to the gate electrode 14, a channel is not formed under the floating gate electrode 13, and the source region and the drain region formed between the auxiliary gate electrodes 6 are not conductive and no current flows. . On the other hand, if electrons are not accumulated in the floating gate electrode 13, the threshold value for forming a channel is lowered. Therefore, when a read voltage is applied to the gate electrode 14, a channel is formed under the floating gate electrode, and a current flows between the source region and the drain region. Thus, information can be stored in the nonvolatile memory cell in accordance with the presence / absence of charge accumulated in the floating gate electrode 13.

  In FIG. 3 (a cross-sectional view taken along the line BB in FIG. 1), a floating gate electrode 13 and a gate electrode 14 corresponding to a plurality of nonvolatile memory cells are formed on the semiconductor substrate 1. A shield electrode 18 is formed between the adjacent floating gate electrodes 13. The floating gate electrode 13 and the shield electrode 18 are insulated by a side wall insulating film (side wall insulating film, second side wall insulating film) 15. The shield electrode 18 is insulated from the semiconductor substrate 1 (p-type well 2) by the shield insulating film 16.

  The function of the shield electrode 18 will be described below. As the non-volatile memory cells are highly integrated, the distance between adjacent floating gate electrodes 13 is becoming narrower. When the distance between the floating gate electrodes 13 becomes narrow, a phenomenon called so-called Vth blur occurs. That is, the charge is accumulated in the floating gate electrode 13, but the threshold value of the nonvolatile memory cell to be read changes depending on the charge accumulation state of the adjacent floating gate electrode 13. It happens. The change of the threshold value to be read changes by (change of write state of adjacent cell) × (capacitive coupling ratio between adjacent floating gate electrodes). When the threshold value is affected by the adjacent floating gate electrode 13 as described above, for example, when a read voltage is applied to the gate electrode 14 of the nonvolatile memory cell to be read, a current flows between the source region and the drain region. Although the current should not flow, the threshold value drops and a current flows. Or, conversely, there is a problem that the current rises between the source region and the drain region, but the threshold value rises and no current flows. As a result, the information of the nonvolatile memory cell to be read cannot be normally read, and the reliability of the read characteristics of the nonvolatile semiconductor memory device is lowered.

  Therefore, the shield electrode 18 is provided between the adjacent floating gate electrodes 13. The shield electrode 18 is made of a conductive material, and the shield effect is obtained by setting the shield electrode 18 to 0 V (ground). In other words, the shield effect of the shield electrode 18 can reduce the influence from the adjacent floating gate electrode 13, so that so-called Vth blur can be reduced.

  However, the shield electrode 18 is usually formed to be higher than the floating gate electrode 13 and to cover the gate electrode 14. Therefore, there arises a new problem that the parasitic capacitance around the gate electrode 14 is increased. When the parasitic capacitance is increased, the time constant (parasitic capacitance × resistance) of the gate electrode 14, that is, the word line is increased, and the driving capability is deteriorated.

  For this reason, in the first embodiment, as shown in FIG. 3, the shield electrode 18 is formed between the adjacent floating gate electrodes 13, and the height of the shield electrode 18 is lower than the height of the floating gate electrode 13. is doing. Then, 0 V or a negative voltage is applied to the shield electrode 18. By forming the shield electrode 18 in this way, the drive capability of the gate electrode (word line) 14 can be maintained while suppressing so-called Vth blur. That is, since the shield electrode 18 is not formed so as to cover the periphery of the gate electrode 14, an increase in parasitic capacitance can be suppressed. The effect of reducing the parasitic capacitance can be obtained by making the height of the shield electrode 18 lower than the height of the gate electrode 14, but further, the floating gate formed below the gate electrode 14 has the height of the shield electrode 18. It is desirable to make it lower than the height of the electrode 13 from the viewpoint of reducing the parasitic capacitance. Although not shown in FIG. 3, all the shield electrodes 18 formed between the gate electrodes 14 are electrically connected at the end portions. That is, 0 V or a negative voltage is simultaneously applied to all the shield electrodes 18.

  Next, in FIG. 4 (cross-sectional view taken along the line CC in FIG. 1), an auxiliary gate electrode 6 extending in the lateral direction (Y direction) is formed on the semiconductor substrate 1, and an insulating film An insulating film 10 and a gate electrode 14 are formed on the auxiliary gate electrode 6 via 5. The gate electrode 14 extends in a direction (X direction) perpendicular to the paper surface.

  FIG. 5 (a cross-sectional view taken along the line DD in FIG. 1) shows a cross section in an open field in which a nonvolatile memory cell is not formed. In FIG. 5, a shield electrode 18 is formed between the pair of auxiliary gate electrodes 6 via a shield insulating film 16. A source region and a drain region are formed under the pair of auxiliary gate electrodes 6 by a channel. In an open field, it is desirable that no leakage current flows between the source region and the drain region.

  However, with the high integration of nonvolatile memory cells, the distance between the source region and the drain region in the open field has become shorter. For this reason, the problem that leakage current increases occurs.

  Therefore, in the first embodiment, the interface between the semiconductor substrate 1 (p-type well 2) and the shield insulating film 16 is set lower than the interface between the semiconductor substrate 1 (p-type well 2) and the gate insulating film 8. (See FIG. 3). Thereby, in an open field in which a nonvolatile memory cell is not formed, a substantial distance between the source region and the drain region can be increased, and a leakage current can be reduced. That is, since the shield insulating film 16 bites into the semiconductor substrate 1, the leakage current path is formed so as to avoid the shield insulating film 16. In other words, the leakage current path becomes longer than the linear distance between the source region and the drain region by the amount that avoids the shield insulating film 16, so that the leakage current can be reduced.

  Next, a write operation, an erase operation, and a read operation of the nonvolatile memory cell in the first embodiment will be described with reference to FIGS.

  The writing operation of the nonvolatile memory cell is performed by applying a predetermined voltage to the semiconductor region serving as the source region / drain region, the gate electrode, and the auxiliary gate electrode.

  Specifically, as shown in FIG. 6, the semiconductor region 20a is 5V, the semiconductor region 20b is open, the semiconductor region 20c is 0V, the gate electrode 14a of the write selection memory cell is 15V, the auxiliary gate electrode 6a is 8V, and the auxiliary gate. 1V is applied to the electrode 6b, and 5V is applied to the auxiliary gate electrode 6c.

  Under this voltage condition, the region under the auxiliary gate electrode 6a and the region under the selected memory cell is strongly inverted to form a channel, so that the potential of the semiconductor region 20a serving as the drain region reaches below the selected memory cell.

  Further, the potential of the source region (the potential of the semiconductor region 20c) also reaches below the auxiliary gate electrode 6b through the channel below the strongly inverted auxiliary gate electrode 6c and the channel below the weakly inverted auxiliary gate electrode 6b.

  At this time, a strong electric field is generated in the channel under the insulating film between the write selection memory cell and the auxiliary gate electrode 6b adjacent to the cell, and hot electrons are generated. The generated hot electrons are injected into the floating gate electrode of the write selection memory cell, and the threshold value of the write selection memory cell rises (source side hot electron injection write method). In this way, a write operation can be performed on the write selected memory cell.

  At this time, in order to suppress the leakage current in the space region (open field) between the write unselected memory cells and between the word lines (gate electrodes), and to increase the channel current of the write selected memory cells to improve the write efficiency, -2V and 0V are applied to the gate electrode 14b and the shield electrode 18 of the non-programmed memory cell, respectively.

  Further, element isolation between memory cells on the selected word line is performed by applying −2 V to the auxiliary gate electrode 6d.

  When erasing the selected memory cell, as shown in FIG. 7, the semiconductor region 20a is 0V, the semiconductor region 20b is 0V, the semiconductor region 20c is 0V, the selected word line (gate electrode 14a) is −18V, and the auxiliary gate electrode 0V is applied to 6a, 0V is applied to the auxiliary gate electrode 6b, and 0V is applied to the auxiliary gate electrode 6c.

  Further, −2V, 0V, and 0V are applied to the gate electrode 14b, the shield electrode 18, and the auxiliary gate electrode 6d of the non-selected memory cell, respectively.

  As a result, electrons are emitted from the floating gate electrode of the selected memory cell to the semiconductor substrate, and the threshold value is lowered. In this way, the erase operation can be performed on the selected memory cell.

  When the read operation of the selected memory cell is performed, as shown in FIG. 8, the semiconductor region 20a is 0V, the semiconductor region 20b is 1V, the semiconductor region 20c is 0V, the auxiliary gate electrode 6a is 4V, and the auxiliary gate electrode 6b is 4V. Then, −2 V is applied to the auxiliary gate electrode 6c. At this time, element isolation is performed by applying −2 V to the two systems of auxiliary gate electrodes 6c and 6d.

  Further, −2 V and 0 V are applied to the gate electrode 14 b and the shield electrode 18 of the non-selected memory cell, respectively. As described above, during the read operation of the selected memory cell, 0 V is applied to the shield electrode 18 to shield the periphery of the selected memory cell, thereby suppressing Vth blur caused by the write state of the unselected memory cell. be able to.

  Here, in the first embodiment, the voltage applied to the shield electrode 18 is always 0 V, but a negative voltage may be applied from the viewpoint of enhancing the leakage current suppressing effect.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 9 to 16, the cross section parallel to the X-axis direction shown in FIG. 1 (corresponding to the AA cross section in FIG. 1) and the cross section parallel to the Y axis direction (corresponding to the BB cross section in FIG. 1). Is described.

  First, after forming a first conductivity type (for example, p-type) semiconductor region (p-type well) 2 on a semiconductor substrate 1, an auxiliary gate insulating film 3 for insulating the auxiliary gate electrode and the semiconductor substrate 1 by thermal oxidation. (FIG. 9).

  Next, a polysilicon film (conductive film) 4 as an auxiliary gate electrode and a silicon nitride film / silicon oxide film (first insulating film) 5 as an insulating film are sequentially deposited by, for example, a CVD (Chemical Vapor Deposition) method ( FIG. 9). Then, the auxiliary gate electrode 6 is formed by patterning using a photolithography technique and a dry etching technique (FIG. 10).

  Subsequently, a silicon oxide film for insulating the auxiliary gate electrode and the floating gate electrode is deposited by the CVD method, and a sidewall insulating film (side wall, first sidewall oxide film) 7 is formed on the side surface of the auxiliary gate electrode 6 by an etching technique. Form (FIG. 11).

  Next, a gate insulating film 8 that insulates the floating gate electrode from the semiconductor substrate 1 is formed by a thermal oxidation method, and then a polysilicon film (first conductive film) 9 to be a floating gate electrode is deposited. Then, a part of the deposited polysilicon film 9 is etched back to make the height of the polysilicon film 9 to be a floating gate electrode lower than that of the silicon nitride film / silicon oxide film 5 (FIG. 12).

  Next, the silicon oxide film formed on the silicon nitride film / silicon oxide film 5 is etched, and thereafter, the silicon oxide film / silicon nitride film / silicon oxide film is formed to insulate the floating gate electrode from the gate electrode. An insulating film (insulating film) 10 is deposited. Further, a polysilicon film (second conductive film) 11 and a silicon oxide film (second insulating film) 12 to be gate electrodes are deposited (FIG. 13).

  Then, the gate electrode 14 is formed by patterning the polysilicon film 11 using a photolithography technique. Then, the floating gate electrode 13 is formed by patterning using the gate electrode 14 as a mask (FIG. 14).

  Subsequently, a side wall insulating film (second side wall insulating film) 15 is formed on the side surfaces of the floating gate electrode 13 and the gate electrode 14 by depositing and etching a silicon oxide film.

  At this time, in order to form the interface between the shield insulating film 16 and the semiconductor substrate 1 at a position lower than the interface between the gate insulating film 8 and the semiconductor substrate 1, the exposed surface of the semiconductor substrate 1 is etched. Here, the semiconductor substrate 1 is the semiconductor substrate 1 including the semiconductor region 2.

  Subsequently, a shield insulating film 16 of the shield electrode is formed by a thermal oxidation method, and a polysilicon film (third conductive film) 17 to be a shield electrode (a shield electrode in the word space portion, a shield electrode on the open field) is deposited. (FIG. 15).

  Thereafter, a part of the polysilicon film 17 is etched back to form a shield electrode 18, and the height of the shield electrode 18 is made lower than the height of the floating gate electrode 13 (FIG. 16). At this time, the height of the shield electrode 18 is set higher than the remaining silicon nitride film of the silicon nitride film / silicon oxide film 5 in order to apply a voltage to the shield electrode 18 at once.

  Subsequently, although not shown in the drawing, after forming an interlayer insulating film between the memory cell, the peripheral circuit and the wiring, the gate electrode 14, the auxiliary gate electrode 6, a diffusion layer to be the source region / drain region, and the peripheral circuit A contact hole is formed for electrical connection. Then, after depositing a metal film, wiring is formed by patterning. In this way, a nonvolatile semiconductor memory device can be formed.

FIG. 17 is a schematic plan view of the nonvolatile semiconductor memory device according to the first embodiment. In FIG. 17, gate electrodes 30 are formed at regular intervals so as to extend in the Y direction.
The gate electrode 30 is connected to the wiring 32 through the contact hole 31.

  A shield electrode 33 is formed in the region between the gate electrodes 30. The shield electrode 33 is bundled on the outer periphery of the gate electrode 30 and can be fed collectively. By arranging a plurality of contact holes 34 at both ends of the shield electrode 33, the resistance of the shield electrode 33 is lowered and the driving capability is increased. The shield electrode 33 is connected to the wiring 35 through the contact hole 34. The voltage is applied to the shield electrode 33 from the dummy gate electrode 30a formed at the end. The dummy gate electrode 30 a is formed on the outermost periphery of the gate electrode 30 and does not function as the gate electrode 30.

  The shield electrode 33 is connected to the dummy gate electrode 30a via a contact hole. By applying 0V or a negative voltage to the dummy gate electrode 30a, 0V or a negative voltage is applied to the shield electrode 33. It has become.

  In FIG. 17, an auxiliary gate electrode 36 is formed in a direction crossing the gate electrode 30, that is, in a direction extending in the X-axis direction. The auxiliary gate electrode 36 is connected to an upper layer wiring through a contact hole 37 so that a predetermined voltage is applied. When a predetermined voltage is applied to the auxiliary gate electrode 36 and turned on, a channel is formed in the semiconductor region under the auxiliary gate electrode 36. This channel is connected to the diffusion layer 38, and the channel functions as a source region or a drain region. That is, the channel potential is the same as the voltage applied to the diffusion layer 38 via the contact hole 39.

  The effect of suppressing the leakage current of the nonvolatile semiconductor memory device manufactured through the above-described steps will be described in comparison with the structure studied by the present inventors.

FIG. 18 shows the structure of the nonvolatile semiconductor memory device in the first embodiment and the structure of the nonvolatile semiconductor memory device examined by the present inventors. 18A shows a structure in which no shield electrode is provided, and FIG. 18B shows a structure in which a high concentration impurity region 21 is formed in a space region between the gate electrodes 14. The high concentration impurity diffusion region 21 is formed, for example, under the conditions of ion species: BF ₂ , implantation energy: 50 keV, and dose amount: 1 × 10 ¹³ (cm ⁻² ). FIG. 18C shows a structure in which a shield electrode 18 is provided in the space region between the gate electrodes 14, and FIG. 18D shows the shield insulating film 16 rather than the interface between the gate insulating film 8 and the semiconductor substrate 1. 2 shows a structure in which the interface between the semiconductor substrate 1 and the semiconductor substrate 1 is lowered.

  The relationship between the gate voltage and the channel current is shown for the four structures shown in FIG. FIG. 19 is a graph showing the relationship between the gate voltage and the channel current for the four structures. In FIG. 19, the horizontal axis represents the gate voltage (V), and the vertical axis represents the channel current (A). The curves (a) to (d) in FIG. 19 correspond to the structures (a) to (d) in FIG. 18, respectively.

  For example, looking at the curve (a) in FIG. 19, a constant channel current flows when the gate voltage is equal to or higher than a predetermined value (ON state), but when the gate voltage becomes equal to or lower than a predetermined value (OFF), Decrease. However, the channel current does not become zero but settles to a constant value. This current that has settled to a certain value indicates a leak current that flows even in the off state. 19A to 19D, it can be seen that the leakage current decreases in the order of (a) to (d). That is, FIG. 19 shows that the effect of suppressing the leakage current increases in the order of (a) <(b) <(c) <(d). Therefore, as shown in FIG. 18D, the leakage current is provided by providing the shield electrode 18 and lowering the interface between the shield insulating film 16 and the semiconductor substrate 1 than the interface between the gate insulating film 8 and the semiconductor substrate 1. Can be greatly reduced. This is because the surface of the semiconductor substrate in the space region between the gate electrodes 14 is separated from the auxiliary gate electrode, so that the electric field from the auxiliary gate electrode is relaxed. Another reason is that the leakage current path can be substantially bypassed and lengthened by causing the shield insulating film 16 to penetrate into the semiconductor substrate 1. Further, since the effect of suppressing the leakage current becomes more pronounced as the shield insulating film 16 is thinner, it is desirable to form the shield insulating film 16 thinner than the gate insulating film 8. As shown in (c) of FIG. 19, the provision of a shield electrode can also provide an effect of reducing the leakage current as compared with (a) and (b) of FIG.

  Next, the effect of suppressing the threshold change of the read selected memory cell by the shield electrode will be described. Here, as an example, the structure of the memory cell is such that the height from the semiconductor substrate 1 to the floating gate electrode 13 is twice the height from the semiconductor substrate 1 to the insulating film 5, the gate width of the gate electrode is 90 nm, and the side wall. The film thickness of the insulating film 15 is 30 nm, and the width of the shield electrode 18 is 30 nm (see FIGS. 2 and 3). The shield electrode 18 is always applied with 0 V or a constant negative voltage (negative bias), and shields the potential change of the floating gate electrode 13 of the read selected memory cell due to the change of the threshold value of the adjacent memory cell. Consider the case.

  FIG. 20 shows the relationship between the ratio of the height of the shield electrode 18 to the height of the floating gate electrode 13 (the height of the shield electrode / the height of the floating gate electrode) and the threshold change due to capacitive coupling of the read selected memory cell. FIG. 3 is a diagram showing a case where a memory cell is a multi-value memory and a binary memory. A multi-level memory can store information of 2 bits or more in one memory cell, and a binary memory can store 2-bit information in one memory cell. FIG. 21 is a diagram showing an example of threshold windows of the multi-level memory and the binary memory.

  As shown in FIG. 21, in the case of a multi-level memory as compared to a binary memory, the threshold value window is wide, and the threshold value distribution is narrowed so that the interval between the threshold value distributions is set narrower. You can see that

  As described above, the threshold value change of the read selected memory cell is represented by (threshold value change of adjacent memory cell) × (capacitive coupling ratio between adjacent floating gate electrodes). For this reason, in the multi-value memory having a large threshold window, the threshold value change of the read selected memory cell accompanying the change in the threshold value of the adjacent cell becomes larger. For example, as shown in FIG. 21, in the binary memory, the threshold change width is 3 V at the maximum, whereas in the multi-value memory, the threshold change width is 5 V at the maximum. Therefore, the first embodiment is particularly effective when applied to a multilevel memory.

  As shown in FIG. 20, when the height of the shield electrode / the height of the floating gate electrode is increased in both the multilevel memory and the binary memory, the threshold value change of the read selected memory cell is reduced. This is because the shield effect can be improved as the height of the shield electrode is increased. However, when the height of the shield electrode is increased, the parasitic capacitance of the gate electrode (word line) is increased and the driving capability is lowered, so that the height of the shield electrode is excessively increased in view of the driving capability of the gate electrode. Not desirable. Here, for example, in a multi-level memory, if a threshold value change of 0.1 V of a read selected memory cell is allowed with respect to a threshold value change (change of 5 V) of an adjacent memory cell, (height of shield electrode / floating It can be seen that the height of the gate electrode should be 0.7.

  Next, the effect of the structure in which the height of the shield electrode is lower than that of the floating gate electrode on the time constant of the gate electrode (word line) will be described. The time constant is expressed by (resistance of the gate electrode) × (total sum of capacitance around the gate electrode). When the time constant increases, the rising time of the applied voltage at the gate electrode becomes longer, so that the driving ability of the gate electrode is deteriorated and the reading characteristics are deteriorated.

  FIG. 22 shows the relationship between (height of the shield electrode / height of the floating gate electrode) and the sum of the surrounding capacitances with respect to the gate electrode (parasitic capacitance). In FIG. 22, the horizontal axis indicates the height of the shield electrode / the height of the floating gate electrode, and the vertical axis indicates the total sum of the surrounding capacitance with respect to the gate electrode. The parasitic capacitance when the shield electrode is not formed is 1. As can be seen from FIG. 22, by increasing the height of the shield electrode below the height of the floating gate electrode, it is possible to suppress an increase in the total capacitance around the gate electrode.

  For example, when (the height of the shield electrode / the height of the floating gate electrode) is 0.7, the total capacity around the gate electrode can be reduced to four times that in the case where the shield electrode is not formed. . At this time, it can be seen that if the resistance is lowered to 0.25 times the current level by, for example, polymetalizing the gate electrode, it is possible to prevent a reduction in the driving capability of the gate electrode. That is, if the shield electrode is formed so as to cover the gate electrode beyond the height of the floating gate electrode, the parasitic capacitance with respect to the gate electrode increases so as not to be covered by the low resistance. However, according to the structure according to the first embodiment, the increase in the parasitic capacitance due to the formation of the shield electrode is in a range that can be covered by the low resistance of the gate electrode. A decrease in driving capability can be suppressed. For example, the resistance of the gate electrode can be reduced by replacing the tungsten silicide (WSi) film, which is a constituent material of the gate electrode, with a tungsten (W) film.

  In addition, when the shield electrode is formed, the parasitic capacitance of the gate electrode is increased, so that the capacitive coupling ratio (coupling ratio) between the gate electrode and the floating gate electrode is lowered, and the writing speed and the erasing speed are deteriorated. In this case, the capacitive coupling ratio can be secured by increasing the height of the floating gate electrode to increase the coupling area between the gate electrode and the floating gate electrode.

  As described above, the memory cell of interest accompanying writing / erasing of the adjacent floating gate is provided by providing a shield electrode between the gate electrodes of the memory cell constituting the nonvolatile semiconductor memory device and constantly applying 0 V or a negative voltage to the shield electrode. Can be suppressed.

  Further, by making the height of the shield electrode lower than that of the floating gate electrode, it is possible to suppress deterioration of the time constant of the gate electrode.

  Furthermore, the leakage current in the space region between the gate electrodes can be suppressed by forming the shield electrode. The effect of suppressing the leakage current becomes remarkable when the shield insulating film is formed at a lower position than the gate insulating film, and the read characteristics of the memory cell can be improved.

(Embodiment 2)
The difference between the second embodiment and the first embodiment is that the arrangement of the memory cells constituting the nonvolatile semiconductor memory device is parallel connection in the first embodiment, whereas the second embodiment is different in the second embodiment. It is a series connection. That is, while the first embodiment has an AND type structure, the second embodiment has a NAND type structure.

  FIG. 23 is a partial top view showing an example of the nonvolatile semiconductor memory device in the second embodiment. In FIG. 23, a plurality of gate electrodes (word lines) 50 extend in the X-axis direction, and a shield electrode 54 extending in the X-axis direction is formed between the gate electrodes 50. A diffusion layer 52 is formed in the direction intersecting the gate electrode 50, that is, in the Y-axis direction. This diffusion layer 52 becomes a source region / drain region. In the first embodiment, the source region and the drain region are formed by the channel formed under the auxiliary gate electrode. On the other hand, in the second embodiment, the diffusion layer 52 is used. Memory cells C1 to C4 are formed in regions where the gate electrode 50 and the diffusion layer 52 intersect. The memory cell C1 and the memory cell C2 are connected in series to one diffusion layer 52. An element isolation region 45 is formed between the diffusion layers 52.

  In the first embodiment, one of the two channels formed under the two auxiliary gate electrodes is a source region and the other is a drain region. A plurality of memory cells are connected in parallel between the source region and the drain region. With this structure, there arises a problem that a leak current flows between the source region and the drain region in an open field in which no memory cell is formed.

  On the other hand, in the second embodiment, one diffusion layer 52 has one end as a source region and the other end as a drain region. Then, a nonvolatile memory cell is arranged in series with the diffusion layer 52 and operated. Since the diffusion layers 52 are separated from each other by the element isolation region 45, there is no problem that a leakage current occurs. However, the second embodiment is also similar to the first embodiment in that so-called Vth blur occurs in which the threshold value of the memory cell of interest changes due to writing / erasing of adjacent memory cells. Therefore, the second embodiment can prevent Vth blur by adopting the structure described below.

  24 to 26 are cross-sectional views taken along lines AA, BB, and CC in FIG. 23, respectively.

  24, the memory cell includes a well 41 formed on the semiconductor substrate 40, a gate insulating film 42, an element isolation region 45, an insulating film (insulating film) 46, an insulating film (second insulating film) 48, a floating gate electrode 49, A gate electrode (control gate) 50 is provided.

  The well 41 and the floating gate electrode 49 are insulated by a gate insulating film 42 (tunnel insulating film), and the floating gate electrode 49 and the gate electrode 50 are insulated by an insulating film 46. The well 41 is isolated by an element isolation region 45 in which a silicon oxide film is embedded in an element isolation trench.

  In FIG. 25, side wall insulating films (side wall insulating films) 51 are formed on the side walls of the floating gate electrode 49 and the gate electrode 50. A shield electrode 54 is formed between the floating gate electrodes 49 via a sidewall insulating film 51, and a shield insulating film 53 is formed below the shield electrode 54. A diffusion layer 52 is formed in the semiconductor substrate 40 below the shield insulating film 53. This diffusion layer 52 is formed from, for example, an n-type impurity diffusion region. Thus, also in the second embodiment, the shield electrode 54 is provided in the same manner as in the first embodiment, and by applying 0V or a negative voltage to the shield electrode 54, the charge accumulation state of the adjacent memory cell is changed. This can suppress fluctuations in the threshold value of the memory cell of interest. As in the first embodiment, the parasitic capacitance around the gate electrode 50 is reduced by making the height of the shield electrode 54 lower than the height of the gate electrode 50, more desirably, the height of the floating gate electrode 49. can do. That is, according to the second embodiment, by providing the shield electrode 54, so-called Vth blur can be reduced, and the height of the shield electrode 54 is made lower than the height of the floating gate electrode 49, thereby making the gate electrode parasitic. Capacitance can be reduced and a reduction in gate electrode driving capability can be suppressed. Although not shown in the drawings, all the shield electrodes 54 formed between the gate electrodes 50 are electrically bound at the end portions.

  In FIG. 26, a well 41 and a diffusion layer 52 are formed in a semiconductor substrate 40, and an element isolation region 45 is formed. Although not shown in FIG. 26, memory cells are connected in series on the individual diffusion layers 52 separated by the element isolation region 45. A shield insulating film 53 is formed on the diffusion layer 52, and a shield electrode 54 is formed on the shield insulating film 53.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to the drawings.

  27 to 32 are cross-sectional views showing a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 33 is a schematic plan view of the nonvolatile semiconductor memory device according to the second embodiment. . 27 to 32, a cross section parallel to the X axis direction shown in FIG. 23 (corresponding to the AA cross section in FIG. 23) and a cross section parallel to the Y axis direction (corresponding to the BB cross section in FIG. 23). ) Is described.

  First, after a well 41 is formed on the semiconductor substrate 40 by ion implantation, a gate insulating film 42 made of, for example, a silicon oxide film is formed by thermal oxidation. Thereafter, a polysilicon film (first conductive film) 43 and a silicon oxide film 44 to be a floating gate electrode are sequentially deposited by a chemical vapor deposition (CVD) method (FIG. 27).

  Next, the polysilicon film 43 is patterned by a photolithography technique and a dry etching technique (FIG. 28).

  Subsequently, an element isolation groove is formed by etching the semiconductor substrate 40 using the silicon oxide film 44 on the patterned polysilicon film 43 as a mask, and then a silicon oxide film is deposited so as to be embedded in the formed element isolation groove. Then, an element isolation region 45 called, for example, STI (Shallow Trench Isolation) is formed by etching back (FIG. 29).

  Next, after an insulating film (insulating film) 46 made of silicon oxide film / silicon nitride film / silicon oxide film is sequentially deposited, a polysilicon film (second conductive film) 47 to be a gate electrode, for example, a silicon oxide film is used. An insulating film (second insulating film) 48 to be formed is deposited (FIG. 30) and patterned by photolithography technique and dry etching technique to form the gate electrode 50 and the floating gate electrode 49 (FIG. 31).

  Subsequently, a silicon oxide film is deposited and etched to form a sidewall insulating film on the side surfaces of the gate electrode 50 and the floating gate electrode 49, and then become a source region / drain region of a memory cell in the exposed semiconductor substrate 1. The diffusion layer 52 is formed by ion implantation.

  Thereafter, a shield insulating film 53 is formed by a thermal oxidation method, and a polysilicon film (third conductive film) to be a shield electrode (electrode formed in a space region between word lines) is deposited and a part thereof is etched back. Thereby, the shield electrode 54 is formed, and the height of the shield electrode 54 is made lower than the height of the floating gate electrode 49 (FIG. 32).

  Subsequently, although not shown in the drawing, after the formation of an interlayer insulating film between the memory cell and the peripheral circuit and the wiring, the gate electrode 50, the diffusion layer serving as the source region / drain region, and the peripheral circuit are made conductive. The contact hole is formed. Then, after depositing a metal film, wiring is formed by patterning. In this way, a nonvolatile semiconductor memory device can be formed.

FIG. 33 is a schematic plan view of the nonvolatile semiconductor memory device according to the second embodiment. In FIG. 33, gate electrodes 60 are formed at regular intervals so as to extend in the Y direction.
The gate electrode 60 is connected to the wiring 62 through the contact hole 61.

  A shield electrode 63 is formed in a region between the gate electrodes 60. The shield electrode 63 is bound on the outer periphery of the gate electrode 60 and can be fed in a batch. By arranging a plurality of contact holes 64 at both ends of the shield electrode 63, the resistance of the shield electrode 63 is lowered and the driving capability is increased. The shield electrode 63 is connected to the wiring 65 through the contact hole 64. The voltage is applied to the shield electrode 63 from the dummy gate electrode 60a formed at the end. The dummy gate electrode 60 a is formed on the outermost periphery of the gate electrode 60 and does not function as the gate electrode 60.

  The shield electrode 63 is connected to the dummy gate electrode 60a via a contact hole. By applying 0V or a negative voltage to the dummy gate electrode 60a, 0V or a negative voltage is applied to the shield electrode 63. It has become.

  Also in the second embodiment, as in the first embodiment, a shield electrode is formed in the inter-word space region of the memory cell, and 0V or a negative voltage is always applied to the shield electrode, so that the adjacent floating gate electrode Changes in the threshold value of the memory cell of interest accompanying writing / erasing can be suppressed.

  In addition, by making the height of the shield electrode lower than that of the floating gate electrode, it is possible to suppress the deterioration of the time constant of the gate electrode (word line), so that it is possible to suppress a decrease in the driving capability of the gate electrode.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The effects of the first embodiment and the second embodiment will be described as follows.

  In a flash memory, by forming a shield electrode in a space region between word lines, it is possible to suppress a change in threshold value of a memory cell of interest due to interference between adjacent floating gate electrodes.

  Further, by making the height of the shield electrode lower than that of the floating gate electrode, it is possible to suppress deterioration of the time constant of the gate electrode.

  Further, since the shield electrode is formed, the leakage current in the space region between the word lines can be suppressed. The effect of suppressing the leakage current is significant when the shield insulating film is formed at a lower position than the gate insulating film formed under the floating gate electrode.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1 is a partial top view showing a nonvolatile semiconductor memory device in a first embodiment of the present invention. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. It is sectional drawing cut | disconnected by CC line of FIG. It is sectional drawing cut | disconnected by the DD line | wire of FIG. It is a figure explaining write-in operation of a nonvolatile semiconductor memory device. It is a diagram illustrating an erasing operation of the nonvolatile semiconductor memory device. It is a figure explaining read-out operation of a nonvolatile semiconductor memory device. FIG. 6 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in the first embodiment. FIG. 10 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 9. FIG. 11 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 10. FIG. 12 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 11. FIG. 13 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 12. FIG. 14 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 13. FIG. 15 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device following FIG. 15. 1 is a schematic plan view showing a nonvolatile semiconductor memory device in a first embodiment. (A), (b) is sectional drawing which showed the structure of the non-volatile semiconductor memory device which the present inventors examined, (c), (d) is the structure of the non-volatile semiconductor memory device in Embodiment 1. It is sectional drawing which showed. It is the graph which showed the relationship between a gate voltage and a channel current. 5 is a graph showing the relationship between (height of shield electrode / height of floating gate electrode) and threshold change due to capacitive coupling. It is the figure which showed the threshold value distribution of a multi-value memory, and the threshold value distribution of a binary memory. It is the graph which showed the relationship between the sum total of the surrounding capacity | capacitance with respect to a gate electrode, and (height of a shield electrode / height of a floating gate electrode). FIG. 6 is a partial top view showing the nonvolatile semiconductor memory device in the second embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. It is sectional drawing cut | disconnected by CC line of FIG. 11 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in the second embodiment. FIG. FIG. 28 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 28. FIG. 30 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device subsequent to FIG. 29. FIG. 31 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 30. FIG. 32 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device following FIG. 31. FIG. 6 is a schematic plan view showing a nonvolatile semiconductor memory device in a second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor region 3 Auxiliary gate insulating film 4 Polysilicon film 5 Silicon nitride film / silicon oxide film 6 Auxiliary gate electrode 7 Side wall insulating film 8 Gate insulating film 9 Polysilicon film 10 Insulating film 11 Polysilicon film 12 Silicon oxide film DESCRIPTION OF SYMBOLS 13 Floating gate electrode 14 Gate electrode 15 Side wall insulating film 16 Shield insulating film 17 Polysilicon film 18 Shield electrode 19 Diffusion layer 30 Gate electrode 30a Dummy gate electrode 31 Contact hole 32 Wiring 33 Shield electrode 34 Contact hole 35 Wiring 36 Auxiliary gate electrode 37 Contact hole 38 Diffusion layer 39 Contact hole 40 Semiconductor substrate 41 Well 42 Gate insulating film 43 Polysilicon film 44 Silicon oxide film 45 Element isolation region 46 Insulating film 47 Polysilicon film 48 Insulating film 49 Floating gate electrode 5 The gate electrode 51 side wall insulating film 52 diffusion layer 53 shielding insulating film 54 shield electrode 60 gate electrode 60a dummy gate electrode
61 Contact hole 62 Wiring 63 Shield electrode 64 Contact hole 65 Wiring

Claims (20)

A nonvolatile semiconductor memory device having a plurality of memory cells on a semiconductor substrate,
The memory cell is
(A) a source region and a drain region formed in the semiconductor substrate;
(B) a gate insulating film formed on the semiconductor substrate;
(C) a floating gate electrode formed on the gate insulating film;
(D) an insulating film formed on the floating gate electrode;
(E) a gate electrode formed on the insulating film,
Further, a shield electrode adjacent to the floating gate electrode is formed between the plurality of memory cells via a sidewall insulating film,
A non-volatile semiconductor memory device, wherein the height of the shield electrode is lower than the height of the gate electrode.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the height of the shield electrode is lower than the height of the floating gate electrode. A shield insulating film is formed between the shield electrode and the semiconductor substrate,
2. The nonvolatile semiconductor memory device according to claim 1, wherein an interface between the shield insulating film and the semiconductor substrate is formed at a position lower than an interface between the gate insulating film and the semiconductor substrate.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the thickness of the shield insulating film is smaller than the thickness of the gate insulating film.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell stores information of 2 bits or more.   The nonvolatile semiconductor memory device according to claim 1, wherein 0 V or a negative voltage is applied to the shield electrode.   The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cells sharing the source region and the drain region are connected in parallel.   2. The nonvolatile semiconductor memory according to claim 1, wherein the source region and the drain region are channel regions formed under an auxiliary gate electrode formed on the semiconductor substrate via an auxiliary gate insulating film. apparatus.   The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cells sharing the source region and the drain region are connected in series.   The nonvolatile semiconductor memory device according to claim 1, wherein the gate electrode is made of a tungsten film. A method for manufacturing a nonvolatile semiconductor memory device, wherein a plurality of memory cells are formed on a semiconductor substrate,
(A) forming an auxiliary gate insulating film on the semiconductor substrate;
(B) forming a conductive film on the auxiliary gate insulating film;
(C) forming a first insulating film on the conductive film;
(D) patterning the conductive film to form an auxiliary gate electrode;
(E) forming a first sidewall insulating film on the sidewall of the auxiliary gate electrode;
(F) forming a gate insulating film on the exposed semiconductor substrate;
(G) forming a first conductive film on the gate insulating film;
(H) forming an insulating film on the first conductive film and the first insulating film;
(I) forming a second conductive film on the insulating film;
(J) forming a second insulating film on the second conductive film;
(K) patterning the second conductive film to form a gate electrode;
(L) patterning the first conductive film to form a floating gate electrode;
(M) forming a second sidewall insulating film on side surfaces of the gate electrode and the floating gate electrode;
(N) forming a shield insulating film on the exposed semiconductor substrate;
(O) forming a third conductive film on the shield insulating film and the second insulating film;
(P) patterning the third conductive film to form a shield electrode adjacent to the floating gate electrode,
A method for manufacturing a nonvolatile semiconductor memory device, wherein the height of the shield electrode is lower than the height of the gate electrode.   12. The method of manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the height of the shield electrode is lower than the height of the floating gate electrode.   In the step (n), the shield insulating film formation region of the semiconductor substrate is etched by a predetermined thickness, and then the shield insulating film is formed, whereby the interface between the semiconductor substrate and the shield insulating film is formed on the semiconductor substrate. 12. The method for manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the method is lower than an interface between the gate insulating film and the gate insulating film.   14. The method of manufacturing a nonvolatile semiconductor memory device according to claim 13, wherein the shield insulating film is formed thinner than the gate insulating film.   12. The method of manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the memory cell stores information of 2 bits or more.   12. The method for manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the shield electrode is formed of a polysilicon film. A method for manufacturing a nonvolatile semiconductor memory device, wherein a plurality of memory cells are formed on a semiconductor substrate,
(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a first conductive film on the gate insulating film;
(C) patterning the first conductive film;
(D) forming an element isolation region between the first conductive films;
(E) forming an insulating film on the first conductive film and the element isolation region;
(F) forming a second conductive film on the insulating film;
(G) forming a second insulating film on the second conductive film;
(H) patterning the second conductive film to form a gate electrode;
(I) patterning the first conductive film to form a floating gate electrode;
(J) forming a sidewall insulating film on a side surface of the floating gate electrode and the gate electrode;
(K) forming a source region and a drain region by forming an impurity diffusion region in alignment with the gate electrode;
(L) forming a shield insulating film on the exposed semiconductor substrate;
(M) forming a third conductive film on the shield insulating film and the second insulating film;
(N) patterning the third conductive film to form a shield electrode adjacent to the floating gate electrode,
A method of manufacturing a nonvolatile semiconductor memory device, wherein the height of the shield electrode is lower than the height of the gate electrode.   18. The method of manufacturing a nonvolatile semiconductor memory device according to claim 17, wherein the height of the shield electrode is lower than the height of the floating gate electrode.   The method of manufacturing a nonvolatile semiconductor memory device according to claim 17, wherein the memory cell stores information of 2 bits or more.   18. The method of manufacturing a nonvolatile semiconductor memory device according to claim 17, wherein the shield electrode is formed of a polysilicon film.