JP2008205187A - Nonvolatile semiconductor memory device and manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device such as a NOR type flash memory and the like which can suppress a depletion of a control gate electrode between floating gate electrodes drastically and contains a multi-value type in which a read error is difficult to occur, and its manufacturing method. <P>SOLUTION: A plurality of memory cells 4 are disposed so as to space in a one direction mutually. A portion 24 overlapped in the one direction is formed of polycrystalline silicon having a doped impurity on a side face of an ONO film 22 of a control gate electrode 2. In the portion 24 overlapped in the one direction in the control gate electrode 2, an impurity concentration of the polycrystalline silicon is set to 10<SP>20</SP>/cm<SP>3</SP>to 10<SP>21</SP>/cm<SP>3</SP>, whereby it is possible to suppress a depletion of the control gate electrode 2 between floating gate electrodes 10 drastically, to radically reduce a threshold value change caused by a capacitance coupling between the floating gate electrodes 10 of adjacent cells, and not to suffer an interference of a threshold value of the adjacent cells. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof. The present invention particularly relates to a nonvolatile semiconductor memory device having a floating gate electrode and capable of electrically rewriting data, and a method for manufacturing the same.

  Conventionally, as a nonvolatile semiconductor memory device, there is a flash memory in which a floating gate electrode and a control gate electrode have a laminated structure and data can be electrically rewritten.

  The flash memory stores the write / erase state by changing the threshold value of the memory cell transistor by injecting / emitting electrons into the floating gate electrode. Since the floating gate electrode is insulated, the electrons accumulated in the floating gate electrode can maintain the state, and information is stored.

  There are many types of flash memory such as NOR type, NAND type, and DINOR type. The point that the threshold value is controlled by the amount of charge in the floating gate electrode is basically the same in any flash memory.

  Here, the structure and operation of a memory cell will be described with respect to a NOR type flash memory as a conventional technique.

  FIG. 10 is a plan view schematically showing a conventional NOR type flash memory cell array. In FIG. 10, reference numeral 103 denotes a drain contact, and 104 denotes a memory cell.

  As shown in FIG. 10, in the memory cell array, active regions are arranged in a stripe shape, and control gate electrodes 102 of a plurality of memory cells are arranged in an orthogonal manner on the active region 101. Under the control gate electrode 102 on the active region 101, a floating gate electrode is disposed independently for each bit, and the source / drain is formed in a self-aligned manner with respect to the control gate electrode 102.

  FIG. 11A is a cross-sectional view taken along the line AA ′ of FIG. 10, and is a schematic cross-sectional view of the flash memory cell array. FIG. 11B is a cross-sectional view taken along the line BB ′ of FIG. 10 and is a schematic cross-sectional view of the flash memory cell array.

  A trench 108 is formed on the silicon substrate 105, and the active region 101 is appropriately separated by embedding an oxide film 109 in the trench 108. A tunnel oxide film 110 is formed on the active region 101, and a floating gate electrode 111 is formed so as to cover the tunnel oxide film 110. The upper surface and side surfaces of the floating gate electrode 111 are covered with the ONO film 112, and the control gate electrode 102 is formed on the ONO layer 112.

  As shown in FIG. 11B, the source 114 and the drain 115 are made of an N + diffusion layer formed in a self-aligned manner with respect to the control gate electrode 102. The source 114 and the drain 115 are connected to a bit line 117 via a drain contact 103 provided on the drain side, while the control gate electrode 102 is connected to a word line.

  Reading (reading) of the memory cell 104 is performed, for example, by setting the potential of the bit line 117 to 1V, the potential of the control gate electrode 102 to 5V, and the potential of the source 114 to 0V. In addition, when writing to the memory cell 104, for example, the potential of the bit line 117 is 4V, the potential of the control gate electrode 102 is 9V, the potential of the source 114 is 0V, and electrons are transferred to the floating gate electrode 111 by channel hot electron injection. By injecting into

  Further, erasure of information written in the memory cell 104 flows from the floating gate electrode 111 toward the silicon substrate 105 by setting the potential of the silicon substrate 105 to 7V and the potential of the control gate electrode 102 to −8V, for example. This is done by emitting electrons with an FN current.

  FIG. 12A is a diagram illustrating an example of a threshold distribution of memory cells in a write / erase state.

  Reading (reading) is performed by comparing the currents of the reference cell and each memory cell 104. While the current flowing through the memory cell 104 in the erased state is larger than that of the reference cell, the current flowing through the memory cell 104 in the written state is smaller than that of the reference cell. If this is utilized, two states can be distinguished.

  In recent years, a memory cell having a large capacity by storing multi-value data in one memory cell has been developed.

  FIG. 12B is a diagram showing an example of a threshold distribution of a flash memory capable of recording multiple values, more precisely, an example of a threshold distribution of memory cells storing four values.

  In the case of a four-value writable memory cell, for example, the four values are detected by comparing the current of the memory cell with three different threshold level reference cells. In this case, the difference between each threshold value and the threshold value of the reference cell is smaller than in the case of binary values.

  However, when the memory cell is miniaturized, there is a problem that the threshold value fluctuates due to the influence of the threshold value of the adjacent cell. This phenomenon occurs due to capacitive coupling between floating gates of adjacent cells. For example, consider a case where three adjacent memory cells are in the erased state and have the same threshold value. In this state, when the left and right cells are set in the write state, electrons are injected into the adjacent floating gate, and the potential of the floating gate rises. If the capacitance between the floating gates is large at this time, the threshold value of the memory cell increases because the potential of the floating gate rises due to the influence of the potential of the adjacent floating gate. Due to such a threshold increase due to capacitive coupling between floating gates with adjacent cells, the current difference from the reference cell changes and a read error occurs. In particular, since the threshold difference between the reference level and the erased state is small in multi-level flash, the influence of the threshold increase due to capacitive coupling between floating gates is large.

For example, JP-T-2005-530362, JP-A-2003-188287, and JP-A-2002-57228 disclose a method for improving the problem by shielding adjacent floating gates with a conductive layer. The patent describes an improvement method for NAND flash memory, but measures can be similarly applied to NOR flash memory cells. That is, a control gate may be embedded between the floating gates to shield the floating gates.
JP 2005-530362 A JP 2003-188287 A JP 2002-57228 A

  The present inventor has found that the above-described conventional technique has the following problems.

  That is, in the prior art, as shown in 13B which is a partially enlarged view of FIGS. 13A and 13A, the depletion layer 130 is generated in the portion of the control gate electrode sandwiched between the adjacent second insulating films, and the control gate It has been found that there is a problem that the capacitance Cfg between the floating gate electrodes increases due to the depletion layer 130 in the electrode portion.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a non-volatile semiconductor memory device that can greatly suppress depletion of a portion of a control gate electrode located between floating gate electrodes and is less prone to read errors, and a method of manufacturing the same. .

In order to solve the above problems, a nonvolatile semiconductor device of the present invention is
Comprising a plurality of memory cells arranged in one direction and spaced from each other;
Each of the above memory cells
A first insulating film formed on the semiconductor substrate;
A floating gate electrode formed on the first insulating film;
A second insulating film formed on a top surface and a side surface of the floating gate electrode in a cross section including the one direction and a direction perpendicular to the top surface of the semiconductor substrate;
The plurality of memory cells include
In the cross section, a common control gate electrode is provided on the upper surface and the side surface of each second insulating film,
The portion of the control gate electrode formed between the portions of the second insulating film formed on the side surface of the floating gate electrode of the memory cell adjacent in the one direction and facing each other in the one direction is an impurity. Is formed of doped polycrystalline silicon.

  According to the present invention, the portion of the control gate electrode located between the portions of the second insulating film facing each other in the one direction is formed of polycrystalline silicon doped with impurities. Depletion of the control gate electrode located between the floating gate electrodes can be significantly suppressed, and the possibility of information misread can be reduced.

In one embodiment, the impurity concentration of the portion of the control gate electrode is not less than 10 ²⁰ / cm ^{3 and not} more than 10 ²¹ / cm ³ .

According to the above embodiment, since the impurity concentration of the polycrystalline silicon is 10 ²⁰ / cm ³ or more and 10 ²¹ / cm ³ or less, the control gate electrode between the floating gate electrodes can be formed in a miniaturized memory cell size. The depletion of can be remarkably suppressed. A memory cell that does not affect the threshold value of the adjacent cell can be provided, and a flash memory suitable for miniaturization without a read error can be provided.

  In one embodiment, the floating gate electrode contains phosphorus or arsenic.

  According to the above embodiment, read errors can be suppressed.

In addition, a method for manufacturing a nonvolatile semiconductor device of the present invention includes
On the semiconductor substrate, a plurality of active regions separated from each other in one direction are formed, and a first insulating film is formed on each active region,
After forming the floating gate electrode on the first insulating film, a second insulating film is formed on the upper surface and the side surface of the floating gate,
After depositing a polycrystalline silicon film on the upper surface and side surfaces of the second insulating film, impurities are implanted into a region between the adjacent second insulating films in the one direction, and then heat treatment is performed. It is characterized by.

  According to the present invention, the depletion of the control gate electrode positioned between the floating gate electrodes can be greatly suppressed, and the possibility of information misread can be reduced.

In one embodiment, the volume concentration of the impurity implanted into the region between the adjacent second insulating films is 10 ²⁰ / cm ³ or more and 10 ²¹ / cm ³ or less.

  According to the above embodiment, depletion of the control gate electrode between the floating gate electrodes can be remarkably suppressed in a miniaturized memory cell size. A memory cell that does not affect the threshold value of the adjacent cell can be provided, and a flash memory suitable for miniaturization without a read error can be provided.

  In one embodiment, the floating gate electrode is a polycrystalline silicon film doped with phosphorus or arsenic.

  According to the above embodiment, read errors can be suppressed.

  According to the nonvolatile semiconductor device of the present invention, since the portion of the control gate electrode that overlaps the side surface of the second insulating film in one direction is formed of polycrystalline silicon doped with impurities, the control between the floating gate electrodes is performed. Depletion of the gate electrode can be greatly suppressed, and reading can be performed accurately.

Further, according to the nonvolatile semiconductor device of one embodiment, since the impurity concentration of the control gate electrode buried between the floating gate electrodes is 10 ²⁰ / cm ³ , the depletion layer width W spreading in the control gate electrode is reduced. , (2ε _Si ε ₀ (2Φ _F ) / qN _A ) ^1/2 , and the capacitance coupling ratio Cfg / Ctot between the floating gate electrodes is about 0.0025. It can be rapidly reduced to 1/10 or less. Therefore, the increase in threshold due to capacitive coupling between the floating gate electrodes can be rapidly reduced to 1/10 or less of the conventional value.

  Therefore, by making the memory cell structure the same as that of the conventional one, the threshold fluctuation due to capacitive coupling between floating gate electrodes of adjacent cells can be drastically reduced without significantly changing the layout and manufacturing process. Thus, a memory cell transistor that does not receive the interference can be realized. In particular, in a miniaturized large-capacity flash memory, the performance of the multi-value flash memory can be remarkably improved.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a plan view of a NOR flash memory cell array in which a plurality of NOR flash memories which are nonvolatile semiconductor memory devices according to an embodiment of the present invention are arranged.

  This flash memory cell array has a plurality of active regions 1 and control gate electrodes 2 of a plurality of memory cells. The active regions 1 are arranged in stripes, and the control gate electrodes 2 are arranged so as to be orthogonal to the active regions 1. An independent floating gate electrode is arranged for each bit on the active region 1 and below the control gate electrode 2, and the source / drain is formed in a self-aligned manner with respect to the control gate electrode 2. In FIG. 1, reference numeral 4 is a memory cell, and reference numeral 5 is a drain contact. The plurality of memory cells 4 included in the flash memory cell array are arranged so as to be spaced apart from each other in one direction that is the extending direction of the control gate electrode 2.

  2A and 2B are schematic cross-sectional views of the flash memory cell array. Specifically, FIG. 2A is a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB ′ in FIG. 1. In FIG. 2A and FIG. 2B, reference numeral 15 indicates a bit line. In FIG. 2A, the arrow A indicates the one direction.

  As shown in FIG. 2A, a trench 8 is formed on the upper surface of a silicon substrate 7 as an example of a semiconductor substrate, and an element isolation region 9 is formed by embedding an oxide film in the trench 8. . The element isolation region 9 isolates the active region 1.

  Each memory cell 4 has a tunnel oxide film 19 as a first insulating film, a floating gate electrode 10, and an ONO film 22 as a second insulating film, and the plurality of memory cells 4 arranged in one direction are Have a common control gate electrode 2.

  The tunnel oxide film 19 is formed on the active region 1, and the floating gate electrode 10 is formed so as to cover the tunnel oxide film 19. Further, the ONO film 22 has the cross section shown in FIG. 2A, that is, the cross section including the one direction and the direction perpendicular to the upper surface of the silicon substrate 7 (the cross section including the one direction and the stacking direction of the nonvolatile semiconductor memory device). The floating gate electrode 10 is formed on the upper surface and side surfaces thereof so as to be along the upper surface and side surfaces of the floating gate electrode 10. The control gate electrode 2 is formed on the upper surface and side surfaces of each ONO film 22 so as to cover the ONO film 22 in the cross section shown in FIG. 2A.

  An interlayer film 27 is located on the control gate electrode 2, and a bit line 15 that is a metal wiring is located on the interlayer film 27. Further, the source indicated by 11 in FIG. 2B and the drain indicated by 13 in FIG. 2B are composed of an N + diffusion layer formed in a self-aligned manner with respect to the control gate electrode 12. The source 11 and the drain 13 are connected to the bit line 15 via the drain contact 5 provided on the drain 13 side. The control gate electrode 12 is connected to a word line (not shown).

  Referring to FIG. 2A, a control gate electrode formed on the side surface of floating gate electrode 10 of memory cell 4 adjacent in one direction and positioned between portions 25 of ONO film 22 facing each other in the one direction. The second portion 24 is made of polycrystalline silicon doped with impurities. In other words, the portion 24 that overlaps in one direction with the side surface of the ONO layer 11 of the control gate electrode 2 is formed of polycrystalline silicon doped with impurities.

In the portion 24 of the control gate electrode 2, the impurity concentration of polycrystalline silicon is 10 ²⁰ / cm ³ or more and 10 ²¹ / cm ³ or less. The floating gate electrode 10 contains phosphorus or arsenic.

  3A to 7B are diagrams illustrating a method for manufacturing a nonvolatile semiconductor device according to an embodiment of the present invention. Hereinafter, an embodiment of a method for manufacturing a nonvolatile semiconductor device of the present invention will be described with reference to FIGS. 3A to 7B. 3A to 7B, AA ′ indicates that the figure corresponds to the sectional view taken along the line AA ′ in FIG. 1, and BB ′ is the figure equivalent to the sectional view taken along the line BB ′ in FIG. It shows that there is.

  First, as shown in FIG. 3A, an active region 1 and an element isolation region 9 are formed on a P-type silicon substrate 7. For example, an oxide film 30 having a thickness of about 15 nm and a SiN film 31 having a thickness of about 150 nm are sequentially deposited on the silicon substrate 1, and the photoresist is left in a stripe shape by photolithography, so that the SiN film 31 and the oxide film 30 are formed. Then, the photoresist is used as a mask to sequentially etch by dry etching, and the silicon substrate 1 is further etched to form a shallow trench 8 having a depth of about 200 nm.

  Next, an HDP film is deposited (for example, 500 nm), and the HDP film is polished by CMP or the like using the SiN film 31 as a stopper. Thereafter, the SiN film 31 is removed with, for example, phosphoric acid to form the active region 1 and the element isolation region 9. In this way, the active region 1 having a width of about 200 nm and the element isolation region 9 having a width of about 150 nm and a thickness of about 350 nm are formed. At this point, FIG. 3B shows a state in which the oxide film 30 and the SiN film 31 are sequentially formed.

Next, in order to increase the P-type concentration immediately below the element isolation region 9 and on the surface of the silicon substrate 1, 5E12 / cm ² of boron (B) having an energy of 30 keV is implanted and boron (B) having an energy of 100 keV is 5E12 / Inject cm ² and drive with heat treatment. Thereafter, the oxide film 30 remaining on the silicon substrate 7 is removed by wet etching or the like, and a thermal oxide film 40 of about 10 nm serving as a tunnel oxide film is formed on the active region 1 as shown in FIG. 4A. Further, a polycrystalline silicon film 41 (for example, film thickness: 150 nm) doped with phosphorus or the like to be a floating gate electrode is deposited thereon. Thereafter, polycrystalline silicon is embedded between the element isolations by CMP or the like. Here, for example, the width of the floating gate electrode is set to about 250 nm, and the space between the floating gate electrodes is set to about 100 nm. At this point, FIG. 4B shows a state in which the thermal oxide film 40 and the polycrystalline silicon film 41 are sequentially formed.

  Subsequently, as shown in FIG. 5A, the ONO film 22 is formed after the oxide film buried between the polycrystalline silicon is etched using a wet etching method or the like. The purpose of etching the oxide film is to increase the gate capacitance ratio as much as possible. In addition, another purpose of etching the oxide film is that the portion between the control gate electrodes is formed in the portion of the groove formed between the adjacent floating gate electrodes by etching between the polycrystalline silicon. This is because a portion for embedding is formed. For this reason, the wet etching amount needs to be performed so that the side surface of the floating gate electrode 41 is exposed as much as possible. At this time, FIG. 5B shows a state in which the polycrystalline silicon film 41 and the ONO film 22 are sequentially formed.

  In this embodiment, the removal amount of the oxide film is 150 nm in the direction perpendicular to the substrate. The ONO film is a film formed by stacking an oxide film, a SiN film, and an oxide film in this order, and the film thickness of each film is, for example, 6 nm / 5 nm / 7 nm. As a method for generating an ONO film, for example, there is a method in which after the surface of polycrystalline silicon is thermally oxidized, a SiN film is deposited by a CVD method or the like, and then an HTO film is deposited.

Next, a polycrystalline silicon film (for example, 200 nm) to be a control gate electrode is deposited on the ONO film 22. By this step, a part of the polycrystalline silicon film 61 that becomes the control gate electrode is buried between the floating gate electrodes 41. Thereafter, impurities such as phosphorus (P) or arsenic (As) are implanted and heat treatment is performed. Here, the impurity implantation amount is set so that the volume concentration of the polycrystalline silicon serving as the control gate electrode buried between the floating gate electrodes is 10 ²⁰ to 10 ²¹ / cm ³ . In this example, P was implanted at ²⁰ KeV, 3.5E15 / cm2.

The polycrystalline silicon 61 serving as the control gate electrode buried between the floating gate electrodes 41 has a thickness of 350 nm and a volume concentration of 10 ²⁰ / cm ³ . Thereafter, heat treatment is performed. The heat treatment is performed so that the implanted impurities are sufficiently diffused to the bottom of the polycrystalline silicon that becomes the control gate electrode buried between the floating gate electrodes. In this embodiment, the heat treatment was continuously performed at 900 ° C. for 30 minutes.

As another method, polycrystalline silicon may be formed by depositing doped silicon into which impurities such as phosphorus (P) or arsenic (As) are introduced. In this case, for example, an LPCVD furnace is used, and monosilane (SiH ₄ ) and phosphine (PH ₃ ) are mainly used as source gases, the film formation temperature is set to about 600 ° C., and the phosphorus concentration in the film is 10 ^20. Set to / cm ³ to produce doped silicon with a thickness of 200 nm (not shown).

  After that, the photoresist is left in stripes by photolithography in the vertical direction with the active region 1, and the polysilicon, the ONO film, and the floating gate electrode are continuously etched by dry etching or the like using the photoresist as a mask. The control gate electrode 12 shown in FIGS. 7A and 7B is formed.

At this time, the floating gate electrode 10 is formed separately for each memory cell under the control gate electrode 12. Then, arsenic (As) was injected (e.g., 15 KeV, 1E15 / cm ^2), heat treatment such as RTA (e.g. 950 ° C., 10 sec) by the applied drain, a source. Thereafter, a sidewall 70 (see FIG. 7B) is formed by depositing and etching back an HTO film or the like, and Co salicide is formed on the source 11 / drain 13 and the control gate electrode 12. Next, after depositing an interlayer film 27 and planarizing it with CMP or the like, a contact plug is formed on the drain. Thereafter, the metal wiring is patterned in a direction perpendicular to the control gate electrode to form a metal wiring that becomes the bit line 15. In this manner, the nonvolatile semiconductor device shown in FIGS. 7A and 7B is formed.

  As in the above-described embodiment, a part of the control gate electrode 2 is buried between adjacent floating gate electrodes 10, and a part of the control gate electrode 2 (the ONO layer 22 in the control gate electrode 2 is the same as the above-described one). If the portion overlapping in the direction) is made of polycrystalline silicon doped with impurities, depletion of the control gate electrode between the floating gate electrodes, which is a problem in the prior art, can be greatly suppressed.

In particular, if the impurity concentration of a part of the control gate electrode 2 is set to 10 ²⁰ / cm ³ to 10 ²¹ / cm ³ , depletion of the control gate electrode between the floating gate electrodes, which is a problem in the prior art, is caused. The suppression effect can be greatly increased.

  Hereinafter, this will be described in detail based on the phenomenon found by the present inventors.

  The floating gate electrode is capacitively coupled to the control gate electrode, the substrate, the source / drain, and the floating gate electrode of the adjacent cell.

  FIG. 8 shows the capacitive coupling using an equivalent circuit.

  The potential of the floating gate electrode includes the capacitance Cono between the floating gate electrode and the control gate electrode, the capacitance Cch between the substrates, the capacitance Cs between the sources, the capacitance Cd between the drains, the capacitance Cfg with the floating gate electrode of the adjacent cell, and the control gate. It is determined by the potential Vg of the electrode, the potential Vsub of the substrate, the potential Vs of the source, the potential Vd of the drain, and the potentials Vfg ′ and Vfg ″ of the floating gate electrode of the adjacent memory cell.

  Specifically, Vfg = (Cono / Ctot) · Vg + (Cch / Ctot) Vsub + (Cd / Ctot) · Vd + (Cs / Ctot) · Vs + (Cfg / Ctot) · Vfg '+ (Cfg / Cot) · Vfg '' + Qfg / Ctot.

  Here, Ctot = Cono + Cch + Cd + Cs + 2 · Cfg, and Qfg is the amount of charge in the floating gate electrode.

  As the memory cell is miniaturized, the capacitance Cfg between the floating gate electrodes increases. When the capacitance between the floating gate electrodes becomes large, the threshold value of the adjacent cell fluctuates due to the influence of capacitive coupling.

  For example, consider a case where three adjacent memory cells are in the erased state and have the same threshold value. In this state, when the left and right two cells are set in the write state, electrons are injected into the adjacent floating gate electrode, and the potential of the floating gate electrode rises. At this time, if the capacitance Cfg between the floating gate electrodes is large, Vfg rises due to the influence of the potential of the adjacent floating gate electrode. That is, the threshold value of the memory cell increases.

  Due to such an increase in threshold due to capacitive coupling between the floating gate electrodes with adjacent cells, the current difference from the reference cell changes, causing a read error. In particular, in a multi-level flash memory, since the threshold difference between the reference level and the erased state is small, the influence of the threshold increase due to capacitive coupling between the floating gate electrodes becomes large.

  This will be described in detail. When polycrystalline silicon is used as the material for the control gate electrode, impurity doping into the polycrystalline silicon is performed simultaneously with the impurity implantation into the source / drain, and when the impurities are activated by the subsequent heat treatment, the memory cell is miniaturized. In this case, it is necessary to form the source / drain Xj shallowly in order to suppress the short channel effect of the cell transistor.

  That is, it is necessary to perform impurity doping with a low dose and low energy, and to perform thermal treatment to suppress the thermal diffusion of impurities by using RTA or the like. For this reason, the dose amount of the impurity introduced into the control gate electrode is small, and it is necessary to reduce the thermal diffusion of the impurity implanted into the polycrystalline silicon.

  Further, since the bottom of the control gate electrode portion buried between the floating gate electrodes has a high aspect, the impurity concentration at the bottom of the control gate electrode buried between the floating gate electrodes is lowered.

  Therefore, even if an attempt is made to shield the potential between the floating gate electrodes by embedding the gap between the control gate electrodes between the floating gate electrodes, the lower part of the control gate electrode buried between the floating gate electrodes has a low impurity concentration. A depletion layer is generated in the crystalline silicon, and the depletion layer in the polycrystalline silicon increases the capacitance Cfg between the floating gate electrodes.

In order to explain this easily, in the case of a 0.13 μm rule NOR-type memory cell, when the impurity concentration at the bottom of the control gate electrode embedded between the floating gate electrodes is 10 ¹⁸ / cm ³ , the adjacent cell The threshold fluctuation due to the capacitive coupling between the floating gate electrodes will be specifically described using numerical values.

  Referring to FIG. 8, various capacitances are values near the actual set value, specifically, capacitance Cono between floating gate electrode control gate electrodes is about 0.18 fF and capacitance Cd between floating gate electrode drains. , About 0.008 fF, the capacitance Cs between the floating gate electrode sources is about 0.008 fF, and the capacitance Cch between the floating gate electrode substrates is 0.08 fF.

In this case, the depletion layer width W spreading in the control gate electrode having an impurity concentration NA of 10 ¹⁸ / cm ³ is about 33 nm due to (2ε _Si ε ₀ (2Φ _F ) / qN _A ) ^1/2 , and this depletion layer The capacitance Cfg between the floating gate electrodes is about 0.007 fF. Therefore, since the capacitive coupling ratio Cfg / Ctot between the floating gate electrodes is about 0.025, the threshold value of the memory cell in the erased state is set to 3V, and the threshold value of the two memory cells adjacent to the left and right from this state is set to 3V. Considering the case where the voltage is raised to 6V, the threshold value increase ΔVth is a very large value of ΔVth = (6-3) × 0.025 × 2 = 0.15V.

  Therefore, although the read error is improved as compared with the conventional case, there is still a possibility that the read error occurs.

The reason why a non-volatile semiconductor device with a very low possibility of read error can be constructed if the impurity concentration is 10 ²⁰ / cm ³ or more can be explained as follows.

  FIG. 9 shows the impurity concentration of polycrystalline silicon as a part of the control gate electrode and the increase (ΔVth) of the threshold value of the memory cell when the threshold values of two memory cells adjacent to the left and right are increased from 3V to 6V. The relationship is shown.

In FIG. 9, ΔVth is 0.18 fF for the capacitance Cono, 0.008 fF for the capacitance Cd between the floating gate electrode drains, and 0.008 fF for the capacitance Cs between the floating gate electrode sources. The capacitance Cch between the electrode substrates was calculated as 0.08 fF using (2ε _Si ε ₀ (2Φ _F ) / qN _A ) ^1/2 .

As shown in FIG. 9, when the impurity concentration is 10 ²⁰ / cm ³ or more, ΔVth can be 0.015 V or less, compared with a device having an impurity concentration of about 10 ¹⁸ / cm ³ . ΔVth can be rapidly reduced to 1/10 or less.

Therefore, as in this embodiment, the impurity concentration of a part of the control gate electrode 2 (the part of the control gate electrode 2 that overlaps the ONO layer 22 in the one direction) is 10 ²⁰ / cm ³ to 10 ²¹ / cm ^3. By doing so, it is possible to construct a memory cell that hardly affects the threshold value of the adjacent cell, and it is possible to construct a nonvolatile semiconductor device (for example, flash memory) suitable for miniaturization with a very low possibility of read error. It can be done.

  In the above embodiment, the nonvolatile semiconductor device is a NOR type flash memory. However, in the present invention, the nonvolatile semiconductor device is not a NOR type flash memory, such as a NAND type flash memory or a DINOR type flash memory. The non-volatile semiconductor device may be used.

Further, in the above embodiment, the impurity implantation amount is set so that the volume concentration of polycrystalline silicon in the control gate electrode 2 embedded between the floating gate electrodes 10 is 10 ²⁰ to 10 ²¹ / cm ³ . However, in this invention, the impurity implantation amount may be such that the volume concentration of polycrystalline silicon in the portion of the control gate electrode buried between the floating gate electrodes is smaller than 10 ²⁰ / cm ³ , It may be a value larger than 10 ²¹ / cm ³ .

  In the above embodiment, phosphorus (P) is implanted into the control gate electrode 2 embedded between the floating gate electrodes 10, but arsenic (As) may be implanted instead of phosphorus.

1 is a plan view of a NOR flash memory cell array in which a plurality of NOR flash memories that are nonvolatile semiconductor memory devices according to an embodiment of the present invention are arranged. FIG. It is a schematic cross section of a flash memory cell array. It is a schematic cross section of a flash memory cell array. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. It is a figure explaining the manufacturing method of the non-volatile semiconductor device of one Embodiment of this invention. The state of capacitive coupling is shown by an equivalent circuit. The relationship between the impurity concentration of a part of polycrystalline silicon of the control gate electrode and the increase in the threshold value (ΔVth) of the memory cell when the threshold values of two memory cells adjacent to the left and right are increased from 3V to 6V is shown. It is a top view which shows typically the conventional NOR type flash memory cell array. FIG. 11 is a cross-sectional view taken along line AA ′ of FIG. 10, and is a schematic cross-sectional view of a flash memory cell array. FIG. 11 is a cross-sectional view taken along the line BB ′ of FIG. 10 and a schematic cross-sectional view of a flash memory cell array. It is a figure which shows an example of the threshold value distribution of the memory cell of a writing / erasing state. It is a figure which shows an example of the threshold value distribution of the flash memory which can record a multi-value, and exactly an example of the threshold value distribution of the memory cell which stores 4 values. It is a figure explaining generation | occurrence | production of the depletion layer in a polycrystalline silicon. It is a figure explaining generation | occurrence | production of the depletion layer in a polycrystalline silicon.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active region 2 Control gate electrode 4 Memory cell 5 Drain contact 7 Silicon substrate 8 Trench 9 Element isolation region 10 Floating gate electrode 11 Source 13 Drain 15 Bit line 19 Tunnel oxide film 22 ONO film

Claims (6)

Comprising a plurality of memory cells arranged in one direction and spaced from each other;
Each of the above memory cells
A first insulating film formed on the semiconductor substrate;
A floating gate electrode formed on the first insulating film;
A second insulating film formed on a top surface and a side surface of the floating gate electrode in a cross section including the one direction and a direction perpendicular to the top surface of the semiconductor substrate;
The plurality of memory cells include
In the cross section, a common control gate electrode is provided on the upper surface and the side surface of each second insulating film,
The portion of the control gate electrode formed between the portions of the second insulating film formed on the side surface of the floating gate electrode of the memory cell adjacent in the one direction and facing each other in the one direction is an impurity. A non-volatile semiconductor memory device, characterized by being made of polycrystalline silicon doped with. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein an impurity concentration in the portion of the control electrode is 10 ²⁰ / cm ³ or more and 10 ²¹ / cm ³ or less. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the floating gate electrode contains phosphorus or arsenic. On the semiconductor substrate, a plurality of active regions separated from each other in one direction are formed, and a first insulating film is formed on each active region,
After forming the floating gate electrode on the first insulating film, a second insulating film is formed on the upper surface and the side surface of the floating gate,
After depositing a polycrystalline silicon film on the upper surface and side surfaces of the second insulating film, impurities are implanted into a region between the adjacent second insulating films in the one direction, and then heat treatment is performed. A method for manufacturing a nonvolatile semiconductor memory device. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4,
A method for manufacturing a nonvolatile semiconductor memory device, wherein the volume concentration of impurities implanted into the region between the adjacent second insulating films is 10 ²⁰ / cm ³ or more and 10 ²¹ / cm ³ or less. . The method for manufacturing a nonvolatile semiconductor memory device according to claim 4,
The method for manufacturing a nonvolatile semiconductor memory device, wherein the floating gate electrode is a polycrystalline silicon film doped with phosphorus or arsenic.

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