JP2001094077A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device, which is constituted so as to be capable of enhancing its yield and its reliability by a method, where an irregularity in an operating characteristic caused by an STI step in an STI- structure semiconductor memory device is prevented and the operating characteristic is made uniform, and to provide its manufacturing method. SOLUTION: In this semiconductor memory device and its manufacturing method, a floating gate is formed into a thickness of an extent such that irregularities on the surface of the floating gate caused by an STI step as the positional relationship of a height between the surface of a semiconductor substrate and the surface of an STO-structure element isolation region are embedded, in other words, in thickness to such an extent that the area on the surface of the floating gate becomes nearly constant, irrespective of the height of the STI step, more correctly, in thickness of 1/2 or larger of the distance between STI-structure element isolation regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a memory cell of a nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 29 shows an STI (Shallow Trench Isolation).
FIG. 4 is a plan view of a memory cell portion of the structure nonvolatile semiconductor memory device. The memory cell portion of the STI structure nonvolatile semiconductor memory device is configured by stacking a silicon oxide film 105 serving as an STI structure element isolation region, a polysilicon film 107 serving as a floating gate, a polysilicon film 110, and the like. I have.

FIG. 30 is a cross-sectional view showing a cross-sectional structure of a memory cell portion of a conventional non-volatile semiconductor memory device having an STI structure along line AA 'in FIG.

The memory cell portion of the conventional nonvolatile semiconductor memory device having an STI structure shown in FIG.
An STI structure element isolation region 105 made of a silicon oxide film formed by filling a groove formed in a surface layer portion and a portion on the groove, and a tunnel oxide film 106 made of a silicon oxide film formed on the surface of the silicon substrate 100; Between STI structure element isolation regions 105 and STI structure element isolation regions 1
A floating gate 107 made of a polycrystalline silicon film formed on
7 and an STI structure element isolation region 105, an inter-poly insulating film 109 made of an ONO (Oxide-Nitride-Oxide) film, a polycrystalline silicon film 110 and a tungsten film sequentially formed on the inter-poly insulating film 109. It comprises a control gate made of a silicide film 111 and a silicon nitride film 112 formed on the tungsten silicide film 111.

FIG. 31 is a sectional view showing a sectional structure of a memory cell portion of the conventional STI structure nonvolatile semiconductor memory device taken along line BB 'in FIG.

The memory cell portion of the conventional STI structure nonvolatile semiconductor memory device shown in FIG.
A tunnel oxide film 106, a floating gate 107, an interpoly insulating film 109, a control gate (a polycrystalline silicon film 110 and a tungsten silicide film 111) and a silicon nitride film 112 are formed in this order, and the STI is formed in the horizontal direction. The trench is formed above the tunnel oxide film 106 in a direction orthogonal to the structural element isolation region 105, and is separated for each cell by the STI structural element isolation region 105.

FIG. 32 is a circuit diagram showing an equivalent circuit of a memory cell of the nonvolatile semiconductor memory device.

The potential of the control gate is Vcg, the potential of the floating gate is Vfg, and the capacitance of the ONO film is C
ono, the capacitance of the tunnel oxide film is Cox, ST
The memory cell of the I-structure nonvolatile semiconductor memory device has a potential V
The capacitance Cono and the capacitance Cox between cg and the ground potential
Are connected in series, and a potential Vfg is applied to a connection node between the capacitance Cono and the capacitance Cox.

Therefore, the writing, erasing and reading operations of the memory cell are performed by changing the voltage applied to the control gate and controlling the potential of the floating gate which is capacitively coupled.

Hereinafter, a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure will be described with reference to the drawings.

FIGS. 33 to 53 are sectional views showing a sectional structure of a memory cell portion in one step of a method of manufacturing a conventional nonvolatile semiconductor memory device having an STI structure. FIGS. 33 to 48 are cross-sectional views of a portion corresponding to line AA 'in FIG. 29, and FIGS. 49 to 53 are cross-sectional views of a portion corresponding to line BB' in FIG.

First, as shown in FIG. 33, a silicon oxide film 101 having a thickness of 10 nm is formed on a silicon substrate 100 by a dry oxidation technique, and is further formed on the silicon oxide film 101 by an LP-CVD method. A silicon nitride film 102 having a thickness of 400 nm is deposited. Silicon nitride film 10
2 is a mask used for trench processing of the silicon substrate 100 in a later step, and a CMP (Chemical Mec).
Functions as a stopper during hanical polishing.

After forming the silicon nitride film 102, as shown in FIG. 34, a photoresist 103 is coated on the entire surface of the silicon nitride film 102 to a thickness of 600 nm, and the photoresist 103 is processed into a predetermined element isolation pattern by a lithography technique. .

After the processing of the photoresist 103, as shown in FIG.
IE, silicon nitride film 102 and silicon oxide film 1
01 is processed into a predetermined pattern.

After processing the silicon nitride film 102 and the silicon oxide film 101, the photoresist 103 is removed by the asher technique as shown in FIG.

After removing the photoresist 103, as shown in FIG. 37, the silicon nitride film 102 is
The silicon substrate 100 is trenched by IE,
A trench 104 having a depth of 400 nm to be an I-structure element isolation region is formed.

After forming the groove 104, as shown in FIG.
1 μm thick silicon oxide film 10 by LP-CVD
5 is buried and the trench 104 is buried.

After depositing the silicon oxide film 105, as shown in FIG. 39, the silicon oxide film 105 is shaved by CMP, and the upper surface of the silicon oxide film 105 is flattened. On this occasion,
As described above, the silicon nitride film 102 functions as a stopper.

After planarizing the upper surface of the silicon oxide film 105, the silicon nitride film 102 is removed by wet etching as shown in FIG.

After removing the silicon nitride film 102, the silicon oxide film 101 is removed by wet etching as shown in FIG. At this point, the silicon oxide film 105
Means that it is processed into the STI structure element isolation region.

After removing the silicon oxide film 101, as shown in FIG. 42, a 10-nm-thick silicon oxide film 106 functioning as a tunnel oxide film of the memory cell is formed by a dry oxidation technique.

After the formation of the silicon oxide film 106, as shown in FIG.
A polycrystalline silicon film 107 of nm is deposited by the LP-CVD method. This polycrystalline silicon film 107 is a film that will later become a floating gate.

After depositing the polycrystalline silicon film 107, FIG.
As shown in FIG.
Then, the photoresist 108 is processed into a predetermined floating gate pattern by a lithography technique.

After processing the photoresist 108, the polycrystalline silicon film 107 is processed into a floating gate by RIE as shown in FIG.

After processing the polycrystalline silicon film 107, FIG.
As shown in FIG.
08 is removed.

After the photoresist 108 has been removed, as shown in FIG.
An NO film 109 is deposited. The ONO film is an insulating film composed of three layers of a silicon oxide film / silicon nitride film / silicon oxide film, and is called an inter-poly (Inter-Poly) insulating film.

After depositing the ONO film 109, as shown in FIG. 48, a 150 nm-thick polycrystalline silicon film 110 in which phosphorus is implanted as an impurity is deposited by LP-CVD, and then a 50 nm-thick polycrystalline silicon film 110 is sputtered. A tungsten silicide film 111 is deposited. The polycrystalline silicon film 110 and the tungsten silicide film 111
Is a film to be a control gate. After depositing the tungsten silicide film 111, a silicon nitride film 112 having a thickness of 300 nm is deposited by the LP-CDV method.

FIG. 49 is a sectional view of a portion corresponding to line BB 'in FIG. 29 at the time when the silicon nitride film 112 is deposited. Hereinafter, the remaining steps will be described with reference to FIGS. 50 to 53 which are cross-sectional views of a portion corresponding to line BB ′ in FIG.

After depositing the silicon nitride film 112, as shown in FIG. 50, a photoresist 113 is applied to a thickness of 600 nm, and
Is processed into a predetermined control gate pattern.

After processing the photoresist 113, as shown in FIG.
The silicon nitride film 112 is processed by IE.

After processing the silicon nitride film 112, as shown in FIG.
3 is removed.

After removing the photoresist 113, as shown in FIG. 53, using the silicon nitride film 112 as a mask,
When the tungsten silicide film 111, the polycrystalline silicon film 110, the ONO film 109, and the polycrystalline silicon film 107 are processed by the IE, the polycrystalline silicon film 110 and the tungsten silicide film 111 become control gates, and are shown in FIGS. 29 to 31. The structure of the memory cell portion of the STI structure nonvolatile semiconductor memory device can be obtained.

[0033]

However, the conventional STI structure nonvolatile semiconductor memory device and the method of manufacturing the same as described above have the following problems.

FIGS. 54 and 55 are cross-sectional views of the memory cell portion showing the problems of the conventional STI structure nonvolatile semiconductor memory device and its manufacturing method. 54 and 55.
30 is a sectional view of a portion corresponding to line AA ′ in FIG. 29.

In the manufacturing process shown in FIG. 39, that is, in the process of flattening the upper surface of the silicon oxide film 105 by CMP, the uniformity of the load on the wafer surface during CMP, the uniformity of the polishing liquid (slurry), etc. Influence of process controllability, C
Due to variations in the thickness of the silicon nitride film 102 serving as an MP stopper, differences in the density of the formed patterns, and the like, the thickness of the remaining film of the silicon nitride film 102 is not constant, and a certain range of the thickness variation occurs. Would. This silicon nitride film 10
2 will be described later.
Surface and STI structure element isolation region (silicon oxide film) 10
5 is reflected in the variation of the STI step, which is the positional relationship of the height with the upper surface.

For example, FIG. 54 shows a case in which the STI step varies in a direction of decreasing, and FIG. 55 shows a case in which the STI step varies in a direction of increasing. FIG.
As can be seen from FIG. 55 and FIG. 55, when the STI step of the memory cell varies, the shape of the floating gate 107, particularly the shape of the upper surface, becomes different, and the surface area of the ONO film 109 covering the floating gate 107 also becomes different.

Since the memory cell is represented by the equivalent circuit shown in FIG. 32, if the ONO film 109 has a different surface area and the ONO film 109 has a different capacitance, a predetermined floating gate Since the potential Vfg cannot be obtained, problems such as a decrease in the writing speed and the erasing speed of the memory cell and an increase in variation in the threshold value occur.

The present invention has been made in view of the above problems, and has as its object to solve the problem of the STI structure semiconductor memory device.
An object of the present invention is to provide a semiconductor memory device having a configuration capable of preventing variation in operation characteristics due to a TI step and achieving uniformity, and improving yield and reliability, and a method of manufacturing the same.

[0039]

According to the semiconductor memory device and the method of manufacturing the same according to the present invention, the surface of the semiconductor substrate and the ST are removed.
ST, which is the positional relationship of the height with the upper surface of the I-structure element isolation region
A thickness such that irregularities on the upper surface of the floating gate caused by the I step are almost buried, in other words, a thickness such that the area of the upper surface of the floating gate is substantially constant regardless of the height of the STI step, more specifically Is characterized in that the floating gate is formed to have a thickness equal to or more than half the distance between the STI structure element isolation regions.
Since the area of the upper surface of the floating gate does not depend on the STI step, the surface area of the interpoly insulating film formed over the floating gate can be made uniform, and the capacitance of the interpoly insulating film can be made uniform. It is possible to prevent variations in operating characteristics and achieve uniformity, thereby improving yield and reliability.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

A semiconductor memory device and a method of manufacturing the same according to the present invention are intended to prevent variations in operating characteristics caused by variations in STI steps, which are the positional relationship between the height of the silicon substrate surface and the upper surface of the STI structure element isolation region. The thickness of the floating gate is increased to such an extent that variation in the area of the upper surface of the floating gate due to variation in the STI step is eliminated. That is, the floating gate has a thickness such that the irregularities on the upper surface of the floating gate due to the STI step are substantially buried, in other words, the thickness of the floating gate is substantially constant regardless of the height of the STI step. Is formed. More specifically, the relationship between the thickness T of the floating gate and the channel width W of the memory cell is such that the inequality W ≦ 2T, and therefore (W / 2) ≦ T, that is, the thickness T is equal to the channel width W
To satisfy the condition of 1/2 or more. Accordingly, the area of the upper surface of the floating gate does not depend on the STI step, the surface area of the interpoly insulating film formed over the floating gate is made uniform, and the capacitance of the interpoly insulating film is made uniform. Therefore, it is possible to prevent variations in the operating characteristics and achieve uniformity, thereby improving the yield and reliability.

FIG. 1 is a sectional view showing a sectional structure of a memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention, and is a sectional view of a portion corresponding to line AA 'in FIG. The plan view of the memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention is similar to the plan view of FIG.

The memory cell portion of the nonvolatile semiconductor memory device having the STI structure according to the present invention shown in FIG.
The STI structure element isolation region 205 made of a silicon oxide film formed by burying a groove formed in the surface layer portion and a portion on the groove, and a tunnel oxide film 206 made of a silicon oxide film formed on the surface of the silicon substrate 200 , ST
A floating gate 207 made of a polycrystalline silicon film formed between the I-structure element isolation regions 205 and on the ends of the STI structure element isolation regions 205 to a thickness such that the irregularities on the upper surface caused by the STI step are almost buried; Floating gate 207 and STI structure element isolation region 205
An inter-poly insulating film 209 made of an ONO film formed covering the inter-gate insulating film, a control gate made of a polycrystalline silicon film 210 and a tungsten silicide film 211 formed sequentially on the inter-poly insulating film 209, and a tungsten silicide film 211 Silicon nitride film 2 formed
12.

As described above, the thickness T of the floating gate 207 in the memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention is different from that of the surface of the silicon substrate 200 by S
The extent to which the variation in the area of the upper surface of the floating gate caused by the STI step variation, which is the positional relationship of the height with the upper surface of the TI structure element isolation region 205, is eliminated, ie, ST
The height of the floating gate is set so that the irregularities on the upper surface of the floating gate caused by the I step are almost buried, in other words, the area of the upper surface of the floating gate is substantially constant regardless of the height of the STI step. More specifically, the relationship between the thickness T of the floating gate and the channel width W of the memory cell satisfies the condition of inequality W ≦ 2T, and therefore (W / 2) ≦ T. The condition to be 以上 or more is satisfied. By setting the thickness T of the floating gate 207 in this manner, the area of the upper surface of the floating gate does not depend on the STI step, the surface area of the interpoly insulating film formed over the floating gate is made uniform, and Since the capacitance of the poly-insulating film can be made uniform, it is possible to prevent variations in operating characteristics and make the characteristics uniform, thereby improving yield and reliability.

FIG. 2 is a sectional view showing a sectional structure of a memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention, and is a sectional view of a portion corresponding to line BB 'in FIG.

The memory cell section of the STI structure nonvolatile semiconductor memory device according to the present invention shown in FIG.
Tunnel oxide film 206, floating gate 207 having the above thickness, interpoly insulating film 209, control gate (polycrystalline silicon film 210)
And a tungsten silicide film 211) and a silicon nitride film 212.
The trench is formed above the tunnel oxide film 206 in a direction perpendicular to the I-structure element isolation region 205, and is separated for each cell by the STI-structure element isolation region 205.

Hereinafter, a method for manufacturing an STI structure nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

FIGS. 3 to 23 are cross-sectional views showing the cross-sectional structure of the memory cell portion in one step of the method of manufacturing the STI structure nonvolatile semiconductor memory device according to the present invention. 3 to 18 are cross-sectional views of a portion corresponding to line AA ′ in FIG. 29, and FIGS. 19 to 23 are cross-sectional views of a portion corresponding to line BB ′ in FIG.

First, as shown in FIG. 3, a silicon oxide film 201 having a thickness of 10 nm is formed on a silicon substrate 200 by a dry oxidation technique, and is further formed on the silicon oxide film 201 by an LP-CVD method. A silicon nitride film 202 having a thickness of 400 nm is deposited. Silicon nitride film 202
Functions as a mask used for trench processing of the silicon substrate 200 and a stopper at the time of CMP in a later step.

After forming the silicon nitride film 202, as shown in FIG. 4, a photoresist 203 is applied to a thickness of 600 nm on the entire surface of the silicon nitride film 202, and the photoresist 203 is processed into a predetermined element isolation pattern by lithography. .

After processing the photoresist 203, as shown in FIG.
E, the silicon nitride film 202 and the silicon oxide film 20
1 is processed into a predetermined pattern.

After processing the silicon nitride film 202 and the silicon oxide film 201, the photoresist 203 is removed by the asher technique as shown in FIG.

After the photoresist 203 is removed, as shown in FIG.
E to form a trench in the silicon substrate 200,
A trench 204 having a depth of 400 nm to be a structural element isolation region is formed.

After forming the groove 204, as shown in FIG.
1 μm thick silicon oxide film 205 by P-CVD
Is deposited to fill the groove 204.

After depositing the silicon oxide film 205, as shown in FIG.
The upper surface of the silicon oxide film 205 is flattened. At this time, as described above, the silicon nitride film 202 functions as a stopper.

After flattening the upper surface of the silicon oxide film 205, as shown in FIG. 10, the silicon nitride film 202 is removed by wet etching.

After removing the silicon nitride film 202, as shown in FIG. 11, the silicon oxide film 201 is removed by wet etching. At this point, the silicon oxide film 205
Means that it is processed into the STI structure element isolation region.

After removing the silicon oxide film 201, as shown in FIG. 12, a 10-nm-thick silicon oxide film 206 functioning as a tunnel oxide film of the memory cell is formed by a dry oxidation technique.

After the silicon oxide film 206 is formed, as shown in FIG.
A polycrystalline silicon film 207 of nm is deposited by the LP-CVD method. This polycrystalline silicon film 207 is a film that will later become a floating gate.

The polycrystalline silicon film 107 in the conventional semiconductor memory device and the method for manufacturing the same was formed to have a thickness of 150 nm, whereas the polycrystalline silicon film 207 in the semiconductor memory device according to the present invention and the method for manufacturing the same was thicker. 3
It is formed at 00 nm. This polycrystalline silicon film 20
The thickness of the floating gate 7 is such that the variation in the area of the upper surface of the floating gate caused by the STI step difference is eliminated, that is, the unevenness of the upper surface of the floating gate caused by the STI step is almost buried.
The area is set so that the area of the upper surface of the floating gate becomes substantially constant regardless of the height of the I step.

More specifically, assuming that the thickness of the polycrystalline silicon film 207 serving as a floating gate is T, and the distance between the STI structure element isolation regions (silicon oxide films) 205 which is the channel width of the memory cell is W, The relationship between the thickness T of the floating gate and the channel width W of the memory cell is
The condition of the inequality W ≦ 2T, and therefore (W / 2) ≦ T, ie,
If the condition that the film thickness T is １ ／ or more of the channel width W is satisfied, the irregularities on the upper surface of the floating gate due to the STI step are almost buried, and the area of the upper surface of the floating gate is almost constant regardless of the height of the STI step. Has been found from the results of simulations and the like described later.

By setting the thickness T of the floating gate 207 in this manner, the area of the upper surface of the floating gate does not depend on the STI step, and the surface area of the interpoly insulating film formed over the floating gate is made uniform. Since the capacitance of the interpoly insulating film can be made uniform, it is possible to prevent variations in operation characteristics and to make the characteristics uniform, thereby improving the yield and reliability.

After depositing the polycrystalline silicon film 207, FIG.
As shown in FIG.
Then, the photoresist 208 is processed into a predetermined floating gate pattern by a lithography technique.

After processing the photoresist 208, as shown in FIG. 15, the polycrystalline silicon film 207 is processed into a floating gate by RIE.

After processing the polycrystalline silicon film 207, FIG.
As shown in FIG.
08 is removed.

After removing the photoresist 208, as shown in FIG. 17, an O-layer having a thickness of about 20 nm is formed by LP-CVD.
An NO film 209 is deposited. As described above, the ONO film is an insulating film composed of three layers of a silicon oxide film / silicon nitride film / silicon oxide film, and is called an interpoly insulating film.

After the ONO film 209 is deposited, as shown in FIG. 18, a 150 nm-thick polycrystalline silicon film 210 in which phosphorus is implanted as an impurity is deposited by LP-CVD, and then a 50 nm-thick polycrystalline silicon film 210 is sputtered. A tungsten silicide film 211 is deposited. The polycrystalline silicon film 210 and the tungsten silicide film 211
Is a film to be a control gate. After depositing the tungsten silicide film 211, a silicon nitride film 212 having a thickness of 300 nm is deposited by the LP-CDV method.

FIG. 19 is a sectional view of a portion corresponding to line BB ′ in FIG. 29 at the time when the silicon nitride film 212 is deposited. Hereinafter, the remaining steps will be described with reference to FIGS. 20 to 23 which are cross-sectional views of a portion corresponding to line BB ′ in FIG.

After depositing the silicon nitride film 212, a photoresist 213 is applied to a thickness of 600 nm as shown in FIG.
Is processed into a predetermined control gate pattern.

After processing the photoresist 213, as shown in FIG.
The silicon nitride film 212 is processed by IE.

After processing the silicon nitride film 212, as shown in FIG.
3 is removed.

After removing the photoresist 213, as shown in FIG. 23, the silicon nitride film 212 is
When the tungsten silicide film 211, the polycrystalline silicon film 210, the ONO film 209, and the polycrystalline silicon film 207 are processed by the IE, the polycrystalline silicon film 210 and the tungsten silicide film 211 become control gates, and are shown in FIGS. The structure of the memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention can be obtained.

FIGS. 24 and 25 show the STI according to the present invention.
FIG. 4 is a cross-sectional view of a memory cell portion showing the effect of the structure nonvolatile semiconductor memory device and the method of manufacturing the same. FIGS. 24 and 25 are cross-sectional views of a portion corresponding to line AA ′ in FIG.

As described above, the manufacturing process shown in FIG.
That is, in the step of flattening the upper surface of the silicon oxide film 205 by CMP, the silicon nitride film 20
2 causes a variation in the thickness of the remaining film, and as a result, a variation in the STI step, which is a positional relationship between the surface of the silicon substrate 200 and the upper surface of the STI structure element isolation region (silicon oxide film) 205, occurs.

For example, FIG. 24 shows a case in which the STI step varies in a direction of decreasing, and FIG. 25 shows a case in which the STI step varies in a direction of increasing.

However, in the nonvolatile semiconductor memory device having the STI structure and the method of manufacturing the same according to the present invention, the thickness of the floating gate 207 is set to such a degree that the variation in the area of the upper surface of the floating gate caused by the variation in the STI step is eliminated. In other words, the surface of the floating gate is set to such a degree that the unevenness of the upper surface of the floating gate due to the STI step is almost buried and the area of the upper surface of the floating gate becomes substantially constant regardless of the height of the STI step.

By setting the thickness T of the floating gate 207 in this manner, as can be seen from FIGS. 24 and 25, even if the STI step of the memory cell varies,
The shape of the floating gate 207, particularly the shape of the upper surface, is substantially the same, and the surface area of the ONO film 209 covering the floating gate 207 is also substantially the same.

As a result, the area of the upper surface of the floating gate does not depend on the STI step, the surface area of the interpoly insulating film formed over the floating gate is made uniform, and the capacitance of the interpoly insulating film is made uniform. Therefore, it is possible to prevent variations in operating characteristics and to achieve uniformity, thereby improving yield and reliability.

Further, the results of a simulation performed on the effects of the STI structure nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention will be described.

FIG. 26 is a schematic sectional view of a floating gate portion in a memory cell of a conventional STI structure nonvolatile semiconductor memory device. FIG. 27 is a floating gate portion in a memory cell of the STI structure nonvolatile semiconductor memory device according to the present invention. FIG.

In FIGS. 26 and 27, the channel width of the memory cell is denoted by reference numeral 301, the thickness of the floating gate is denoted by reference numeral 302, the STI step is denoted by reference numeral 303, the floating gate wing width is denoted by reference numeral 304, and the floating gate surface area is as shown in FIGS. This is indicated by a bold line. The surface area of the floating gate is equal to the surface area of the ONO film (interpoly insulating film).

The simulation calculates by calculation how the capacitance of the ONO film (interpoly insulating film) changes when the STI step 303 changes due to process variation or the like in these memory cell structures. It was done.

FIG. 28 shows ST calculated by simulation for the memory cell structures of the STI semiconductor memory device according to the present invention and the conventional STI semiconductor memory device.
5 is a graph showing the relationship between the I step ratio and the ONO film capacitance ratio.

As design values in this simulation, the memory cell channel width 301 was 450 nm, the memory cell channel length (not shown) was 400 nm, and the floating gate wing width 304 was 150 nm.
Further, the floating gate film thickness 302 in the memory cell of the conventional STI structure semiconductor memory device is 150 nm,
The floating gate film thickness 302 in the memory cell of the STI structure semiconductor memory device according to the present invention was 300 nm.

Then, for any of the memory cells,
The design reference value of the STI step 303 is 150 nm, and the STI step ratio on the horizontal axis of the graph represents the ratio of the value of the STI step 303 to the design reference value. The ONO film capacitance ratio on the vertical axis of the graph represents the ratio of the ONO film capacitance value to the design reference value of the ONO film capacitance calculated from each of the design values.

As is clear from this graph, the conventional S
In a memory cell structure of a TI structure semiconductor memory device, S
While the ONO film capacitance ratio changes in proportion to the change in the TI step ratio, the ONO film static ratio changes in the memory cell structure of the STI structure semiconductor memory device according to the present invention regardless of the change in the STI step ratio. It can be seen that the capacitance ratio can always maintain a constant value.

In order to obtain the effects of the present invention,
It is necessary to eliminate the plane portion 305 on the upper surface of the floating gate in the memory cell structure of the conventional STI structure semiconductor memory device shown in FIG. 26, and specific conditions for that are as described above.

Although the floating gate 207 is formed of a polycrystalline silicon film in this embodiment, it may be formed of an amorphous silicon film. Although phosphorus is used as an impurity to be implanted into the floating gate 207, arsenic may be used. The impurity implantation method may be any of a gas phase diffusion method, a solid phase diffusion method, and an ion implantation method. Furthermore, each film thickness is not limited to the specific numerical values described in the present embodiment.

[0089]

According to the semiconductor memory device and the method of manufacturing the same of the present invention, the unevenness of the upper surface of the floating gate caused by the STI step, which is the positional relationship between the surface of the semiconductor substrate and the upper surface of the STI structure element isolation region, is reduced. The thickness is such that it is almost buried, in other words, the thickness is such that the area of the upper surface of the floating gate is substantially constant regardless of the height of the STI step, and more specifically, the distance between the STI structure element isolation regions. Since the floating gate is formed to have a thickness of 1/2 or more, the area of the upper surface of the floating gate does not depend on the STI step, and the surface area of the interpoly insulating film formed over the floating gate is made uniform. , The capacitance of the interpoly insulating film can be made uniform, and the variation in the operating characteristics can be prevented, and the uniformity can be achieved. It is possible to improve the fine reliability.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a cross-sectional structure of a memory cell section of an STI structure nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view showing a cross-sectional structure of a memory cell portion of the STI structure nonvolatile semiconductor memory device according to the present invention.

FIG. 3 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI structure nonvolatile semiconductor memory device according to the present invention.

FIG. 4 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 5 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 6 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 7 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 8 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 9 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 10 is a sectional view showing a sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 11 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing an STI structure nonvolatile semiconductor memory device according to the present invention.

FIG. 12 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 13 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 14 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 15 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 16 is a sectional view showing a sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 17 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 18 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 19 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 20 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 21 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 22 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 23 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing an STI-structure nonvolatile semiconductor memory device according to the present invention.

FIG. 24 is a cross-sectional view of a memory cell portion showing the effects of the STI structure nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention.

FIG. 25 is a cross-sectional view of a memory cell part showing the effects of the STI structure nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention.

FIG. 26 is a schematic cross-sectional view of a floating gate part in a memory cell of a conventional STI structure nonvolatile semiconductor memory device.

FIG. 27 is a schematic sectional view of a floating gate portion in a memory cell of the STI structure nonvolatile semiconductor memory device according to the present invention.

FIG. 28 shows an STI step ratio and O calculated by simulation for the memory cell structures of the STI semiconductor memory device according to the present invention and the conventional STI semiconductor memory device.
4 is a graph showing a relationship with an NO film capacitance ratio.

FIG. 29 is a plan view of a memory cell portion of the STI structure nonvolatile semiconductor memory device.

30 is a cross-sectional view showing a cross-sectional structure of a memory cell portion of the conventional non-volatile semiconductor memory device having an STI structure along line AA ′ in FIG. 29;

FIG. 31 is a cross-sectional view showing a cross-sectional structure of a memory cell portion of the conventional non-volatile semiconductor memory device having an STI structure along line BB ′ in FIG. 29;

FIG. 32 is a circuit diagram showing an equivalent circuit of a memory cell of the STI structure nonvolatile semiconductor memory device.

FIG. 33 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional STI-structure nonvolatile semiconductor memory device.

FIG. 34 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional STI structure nonvolatile semiconductor memory device.

FIG. 35 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional STI-structure nonvolatile semiconductor memory device.

FIG. 36 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional STI structure nonvolatile semiconductor memory device.

FIG. 37 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 38 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 39 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 40 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 41 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 42 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional STI-structure nonvolatile semiconductor memory device.

FIG. 43 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional STI structure nonvolatile semiconductor memory device.

FIG. 44 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 45 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 46 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 47 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional STI-structure nonvolatile semiconductor memory device.

FIG. 48 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional STI-structure nonvolatile semiconductor memory device.

FIG. 49 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 50 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 51 is a cross-sectional view showing a cross-sectional structure of a memory cell part in one step of a method for manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 52 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method for manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 53 is a cross-sectional view showing a cross-sectional structure of a memory cell portion in one step of a method of manufacturing a conventional non-volatile semiconductor memory device having an STI structure.

FIG. 54 is a cross-sectional view of a memory cell portion showing a problem of a conventional STI structure nonvolatile semiconductor memory device and a method of manufacturing the same.

FIG. 55 is a cross-sectional view of a memory cell portion showing a problem of a conventional nonvolatile semiconductor memory device having an STI structure and a method of manufacturing the same.

[Explanation of symbols]

100, 200 Silicon substrate 101, 201 Silicon oxide film 102, 202 Silicon nitride film 103, 108, 113, 203, 208, 213 Photoresist 104, 204 Groove 105, 205 STI structure element isolation region (silicon oxide film) 106, 206 Tunnel oxide film (silicon oxide film) 107, 207 Floating gate (polycrystalline silicon film) 109, 209 Interpoly insulating film (ONO film) 110, 210 Polycrystalline silicon film 111, 211 Tungsten silicide film 112, 212 Silicon nitride film 301 Channel width of memory cell 302 Floating gate thickness 303 STI step 304 Floating gate wing width 305 Planar part of floating gate upper surface T Floating gate thickness W Memory cell Channel width Vcg Control gate potential Vfg Floating gate potential Cono ONO film capacitance Cox Tunnel oxide film capacitance

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA25 AA43 AA63 AB08 AD60 AF05 AG07 AG22 5F083 EP23 EP42 EP55 EP56 EP57 GA30 JA04 JA32 JA53 NA01 PR03 PR05 PR21 PR22 PR29 PR36 PR40 5F101 BA07 BA28 BA36 BB05 BD35 BF01 BH04 BH19

Claims (4)

[Claims] An STI (Shallow Tr) formed by burying a groove formed in a surface layer portion of a semiconductor substrate and a portion on the groove.
and a tunnel oxide film formed on the surface of the semiconductor substrate; between the STI structure element isolation regions and on an end of the STI structure element isolation region; A floating gate formed to a thickness such that the area of the upper surface of the floating gate is substantially constant irrespective of the height of the STI step, which is the height positional relationship with the upper surface of the element isolation region; and the floating gate and the STI structure A semiconductor memory device comprising: an interpoly insulating film formed to cover an element isolation region; and a control gate formed on the interpoly insulating film. 2. An STI structure element isolation region formed by burying a groove formed in a surface layer portion of a semiconductor substrate and a portion on the groove, a tunnel oxide film formed on a surface of the semiconductor substrate, and the STI structure element. A floating gate formed between the isolation regions and on an end of the STI structure element isolation region so as to have a thickness of １ ／ or more of a distance between the STI structure element isolation regions; and the floating gate and the STI structure element isolation region. And a control gate formed on the interpoly insulating film. 3. A first step of forming a groove in a surface layer portion of a semiconductor substrate and forming an STI structure element isolation region by filling the groove and a portion on the groove, and forming a tunnel oxide film on a surface of the semiconductor substrate. Second
Between the STI structure element isolation regions and on the ends of the STI structure element isolation regions, the height of the STI step, which is the positional relationship between the height of the semiconductor substrate surface and the upper surface of the STI structure element isolation regions, A third step of forming the floating gate to a thickness such that the area of the upper surface of the floating gate is substantially constant, and a fourth step of forming an interpoly insulating film covering the floating gate and the STI structure element isolation region. And a fifth step of forming a control gate on the interpoly insulating film. 4. A first step of forming a groove in a surface layer portion of a semiconductor substrate, filling the groove and a portion on the groove to form an STI structure element isolation region, and forming a tunnel oxide film on a surface of the semiconductor substrate. Second
And a third step of forming a floating gate between the STI structure element isolation regions and on the end of the STI structure element isolation region to a thickness of at least half the distance between the STI structure element isolation regions. A fourth step of forming an interpoly insulating film covering the floating gate and the STI structure element isolation region; and a fifth step of forming a control gate on the interpoly insulating film. A method for manufacturing a semiconductor memory device, comprising: