JP2001077333A - Nonvolatile semiconductor memory and its manufacturing method - Google Patents

Nonvolatile semiconductor memory and its manufacturing method

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Publication number
JP2001077333A
JP2001077333A JP24620699A JP24620699A JP2001077333A JP 2001077333 A JP2001077333 A JP 2001077333A JP 24620699 A JP24620699 A JP 24620699A JP 24620699 A JP24620699 A JP 24620699A JP 2001077333 A JP2001077333 A JP 2001077333A
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Japan
Prior art keywords
insulating film
gate
element isolation
film
isolation insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24620699A
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Japanese (ja)
Inventor
Kazuhiro Shimizu
Yuji Takeuchi
和裕 清水
祐司 竹内
Original Assignee
Toshiba Corp
株式会社東芝
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Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP24620699A priority Critical patent/JP2001077333A/en
Priority claimed from TW89117513A external-priority patent/TW484228B/en
Priority claimed from KR1020000051025A external-priority patent/KR100349279B1/en
Publication of JP2001077333A publication Critical patent/JP2001077333A/en
Pending legal-status Critical Current

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Abstract

(57) [Abstract] (with correction) [PROBLEMS] To reduce the variation in capacitance coupling of a stacked gate and to make a memory cell finer without causing short-circuit failure between gates and deterioration of element isolation performance. Provided is a nonvolatile semiconductor memory device. SOLUTION: An element formation region 2 partitioned by an element isolation insulating film 2 is formed on a silicon substrate 1. On this substrate, a charge storage layer 5 is formed via a tunnel insulating film 4, and a control gate 8 is formed via a gate insulating film 7 thereon, thereby forming a memory cell. The charge storage layer 5 of the memory cell is patterned so as to partially overlap the element formation region 3 and the element isolation insulating film 2, and the charge storage layer 5 of the adjacent memory cell facing the element isolation insulating film 2.
A protective insulating film 11 that protects the surface of the element isolation insulating film 2 is disposed between the end portions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory device having a memory cell having a stacked gate structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art As an electrically rewritable nonvolatile semiconductor memory (EEPROM), there is known a memory using a MOS transistor structure having a stacked structure of a charge storage layer and a control gate. FIG. 15 is a plan view of a NOR type EEPROM using such a memory cell, and FIGS. 16 (a) and 16 (b) respectively show A of FIG.
It is sectional drawing of -A 'and BB'.

An element isolation insulating film 102 is buried in a memory cell array region of a silicon substrate 101, and an element forming region 103 continuous in the y direction is partitioned at a predetermined interval in the x direction. A charge storage layer 105 is formed on the substrate separated in this manner via a tunnel insulating film 104, and a control gate 108 is formed on the charge storage layer 105 via an inter-gate insulating film 107 to form a memory cell Is configured. The charge storage layer 105 is an element isolation insulating film 102
It is divided above and becomes independent for each memory cell. The control gate 108 is formed continuously in the x direction, and serves as a common word line for a plurality of memory cells. The control gate 108 and the charge storage layer 105 are patterned in a self-aligned manner so that their side edges are aligned in the y direction. And this control gate 108
An n-type diffusion layer 6 is formed in a self-aligned manner. The memory cell is covered with an interlayer insulating film 109, on which a bit line 110 running in the y direction is provided.

[0004] The data rewriting of this EEPROM is
This is performed by applying a high electric field between the substrate and the charge storage layer and causing a tunnel current to flow between the charge storage layer and the substrate, thereby modulating the amount of charge stored in the charge storage layer. The threshold value of the memory cell increases as the amount of negative charges in the charge storage layer increases, and decreases as the amount of positive charges increases. Therefore, when electrons are injected into the charge storage layer, the state becomes a high threshold state (this is, for example, a write state), and when electrons are extracted from the charge storage layer, a state becomes low (for example, a data erase state).

The most important parameter for rewriting data in such a memory cell is the ratio C1 / C1 between the capacitance C1 between the charge storage layer 105 and the substrate 101 and the capacitance C2 between the control gate 108 and the charge storage layer 105. C2. When the voltage Vcg is applied to the control gate 108 with the substrate at 0 potential, the voltage Vfg of the charge storage layer 105 becomes Vfg = C
2 · Vcg / (C1 + C2). Therefore, the coupling ratio K = C2 / (C1 + C2) = 1 / {1+ (C1 /
C2)} determines the voltage applied to the tunnel insulating film 104.

In order to generate a tunnel current, it is necessary to apply a high electric field of more than ten MV / cm to the tunnel insulating film. For this purpose, V is applied between the charge storage layer and the substrate.
A high voltage of about fg = 10 V needs to be applied. Since the charge storage layer and the control gate are capacitively coupled, a high voltage of about 20 V is required as the voltage Vcg = K · Vfg applied to the control gate. Even if the same voltage is applied to the control gate, if the coupling ratio K is different, the voltage applied to the tunnel insulating film is different, and the threshold value of the memory cell is different. This is a problem because the threshold distribution in the written state of the memory cell is widened. Therefore, it is important to make the coupling ratio K uniform.

FIG. 1 shows the dimensions of each part of the conventional memory cell structure.
7, and using this to determine the capacitance ratio C2 / C1,
It becomes like the following formula.

[0008]

## EQU1 ## C2 / C1 = {Wa + 2 (d + Tsti + Win)
g)} Tox / Wa · Tono Wing = (Wsti-SL) / 2

The capacitance C2 is determined by the area of the charge storage layer 105 and the control gate 108 facing each other. Accordingly, variations in the thickness of the charge storage layer and variations in the length (so-called wing length) Wing of the charge storage layer 105 protruding into the element isolation region cause variations in the capacitance C2. In addition, when the element formation region and the element isolation region have different heights, the thickness of the charge storage layer 105 is likely to be non-uniform as shown in FIG. The non-uniformity of the thickness of the charge storage layer causes a variation in the effective surface area of the charge storage layer. This also causes the variation of the capacitance C2.

The wing length Wing is equal to the element separation width Ws.
It is determined by ti and the cutting width (so-called slit width) SL of the charge storage layer. When the cell size is reduced to increase the capacity and reduce the cost of the EEPROM, the element separation width Wsti and the slit width SL often become the minimum dimensions at the time of manufacturing a memory cell. In the memory cell described above, the charge storage layer 105
Is narrower than the element separation width Wsti, and this is the minimum dimension. However, since the element isolation width determines the bit line pitch together with the element formation region, it is desirable to reduce the element isolation width Wsti as much as possible in order to reduce the memory cell array area.

As a method of realizing a smaller slit width in the range of a small element isolation width, a method using a technique of leaving a side wall has already been proposed by the present inventors (K. Shimizu et. Al. ' 97 IED
M). In this method, after a mask material for slit processing is patterned on the charge storage layer, an additional mask material is deposited to leave a side wall, thereby obtaining a narrow slit width. FIG.
8 and 19 show such a memory cell manufacturing process.

As shown in FIG. 18A, a gate material film 10 is formed on a silicon substrate 101 with a gate insulating film 104 interposed therebetween.
5a is deposited, a mask material 201 is formed thereon, and a pattern is formed so that the gate material film 105a is left in the element formation region. Then, as shown in FIG.
The substrate 101 is etched using 01 to form an element isolation groove, and an element isolation insulating film 102 is buried therein. Next, as shown in FIG. 18C, the gate material film 105a is formed.
Is deposited again, and a mask material 202 for slit processing is formed on the element isolation insulating film 102 by patterning.

Further, as shown in FIG. 19A, a thin mask material 203 is again deposited and etched by anisotropic dry etching to leave the mask material 203 only on the side walls of the mask material 202. Thereby, a slit processing window smaller than the minimum processing dimension is formed. Then, the mask material 20
By etching the gate material film 105b by using the gate insulating films 2 and 203, the charge storage layer 105 having a stacked structure of the gate material films 105a and 105b is formed.
2 and are separated and patterned. After this, FIG.
As shown in (b), a control gate 108 is formed with an inter-gate insulating film 107 interposed. As described above, the control gate 108 is separated from the charge storage layer 105 in the bit line direction.

However, in the above method, after the gate material film 105b is etched in the step of FIG.
In the step of etching and removing 2,203, the surface of the element isolation insulating film 102 is etched, and a narrow groove 204 is formed in the slit separation portion of the charge storage layer 105 as shown in FIG. The groove 204 on the surface of the element isolation insulating film 102 is continuously formed not only in the cross section of FIG. 19 where the control gate 108 is provided but also in the bit line direction (y direction of FIG. 15). When the material of the inter-gate insulating film 107 and the control gate 108 is deposited so as to fill the groove 204, etching residue is generated along the groove 204 in a step of patterning the material due to the narrowness. In addition, since the thickness of the element isolation insulating film 102 immediately below the control gate 108 is reduced, when the thickness of the element isolation insulating film 102 is reduced, the element isolation function is deteriorated. Bring.

[0015]

As described above, in an EEPROM having a memory cell having a laminated structure of a charge storage layer and a control gate, as the element becomes finer, the thickness of the charge storage layer becomes uneven and the charge is not increased. There has been a problem that variation in capacitance coupling caused by variation in slit processing width for separating the storage layer deteriorates data rewriting performance. Also, if a slit narrower than the device isolation width is formed on the device isolation insulating film to separate the charge storage layer, the film of the device isolation insulating film will be reduced, and the device isolation performance will be degraded and a gate short circuit will occur due to gate residues. There is also a problem that occurs.

The present invention has been made in consideration of the above circumstances, and has been made to exhibit excellent data rewriting performance by suppressing variations in capacitance coupling of stacked gates when memory cells are miniaturized. An object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same. The present invention also makes it possible to miniaturize a memory cell without causing a decrease in the thickness of an element isolation insulating film due to the separation of a charge storage layer, and without causing a short circuit between gates or deterioration of element isolation performance. An object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0017]

According to the present invention, there is provided a nonvolatile semiconductor memory device, comprising: a semiconductor substrate; an element isolation insulating film formed on the semiconductor substrate for partitioning an element formation region; , A first gate formed via a first gate insulating film, and a second gate formed on the first gate.
And a memory cell array in which memory cells having second gates formed through the gate insulating film are arranged in an array. The first gate of the memory cells is formed from above the element formation region. A pattern is formed so as to partially overlap the element isolation insulating film, and the surface thereof is substantially flat.

According to the present invention, the surface of the first gate which is formed so as to partially overlap the element isolation insulating film from the element formation region and serves as a charge storage layer (that is, a floating gate) of the memory cell is made substantially flat. Thus, the variation in the capacitance coupling between the second gate and the first gate, which is the control gate, is small. The flatness of the first gate surface of such a memory cell is obtained by forming element isolation insulating films at a fine pitch so that the element formation region of the memory cell array region becomes a narrow recess and the element isolation insulating film becomes convex. Thus, it is obtained. That is, if the width of the concave portion in the element formation region is small, the concave portion can be filled when a gate material film is deposited thereon to a predetermined thickness so that the surface becomes flat.
At this time, assuming that the transistor size in the peripheral circuit region is larger than the memory cell, the first gate of the memory cell has a larger film thickness than the gate formed simultaneously with the first gate of the memory cell in the peripheral circuit transistor. Becomes

The nonvolatile semiconductor memory device according to the present invention also includes a semiconductor substrate, an element isolation insulating film formed on the semiconductor substrate for partitioning an element formation region, and a first gate formed on the semiconductor substrate. A memory cell array in which a first gate formed via an insulating film and a memory cell having a second gate formed on the first gate via a second gate insulating film are arranged in an array. A first gate of the memory cell is patterned so as to partially overlap the element isolation insulating film from above the element formation region, and the first gate of the memory cell is adjacent to the first gate. A protective insulating film is provided on the element isolation insulating film sandwiched between the formation regions.

As described above, by disposing the protective insulating film between the ends of the first gate on the element isolation insulating film, the film thickness of the element isolation insulating film is prevented, and the element isolation performance is prevented from deteriorating. You. In this case, by making the surface of the first gate substantially flat, the uniformity of the capacitive coupling is improved.
In addition, if the protective insulating film is continuously provided on the element isolation insulating film in a direction orthogonal to the longitudinal direction of the second gate, the protective insulating film extends over adjacent gates. No groove is formed in the gate, and it is possible to prevent the occurrence of a gate-to-gate short circuit accident.

The nonvolatile semiconductor memory device according to the present invention further includes a semiconductor substrate, and an element isolation insulating film formed on the semiconductor substrate to partition a plurality of element formation regions that are continuous in one direction at a predetermined interval. A plurality of memory cells arranged in an array on the semiconductor substrate, each memory cell having a charge storage layer formed in the element formation region via a first gate insulating film and a second charge storage layer formed on the charge storage layer; A memory cell array having a control gate continuously arranged over a plurality of memory cells arranged in a direction crossing the element isolation insulating film with the gate insulating film interposed therebetween. The layer is patterned and formed so as to partially overlap the element isolation insulating film from above the element formation region, and is adjacent to the charge storage layer and adjacent to the element formation region. And a protective insulating film covered by the control gate and the second gate insulating film on the insulating film is disposed.

In a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of depositing a first gate material film on a semiconductor substrate via a first gate insulating film; Patterning a mask material for element isolation, and etching the first gate material film and the semiconductor substrate using the mask material to form a plurality of element formation regions continuous in a first direction. The second orthogonal to the direction of
Forming an element isolation groove so as to be partitioned at predetermined intervals in the direction of, and embedding an element isolation insulating film in the element isolation groove so as to be at substantially the same surface position as the mask material. Patterning a laminated film of a protective insulating film for protecting the element isolation insulating film and a gate burying insulating film so as to be continuous in the first direction, and etching the mask material using the laminated film as a mask Removing the first gate material film and the second gate material separated on the element isolation insulating film by the laminated film by depositing and polishing the surface of the second gate material film Forming a charge storage layer having a layered structure of a film, and removing the gate isolation insulating film on the element isolation insulating film, and then forming a second gate insulating film on the charge storage layer and the protective insulating film. Through Depositing a third gate material film, and sequentially etching the third gate material film, the second gate insulating film, and the charge storage layer to form a control gate continuous in a second direction and self-aligned therewith. And forming a pattern of the charge storage layer separated in the first direction.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the semiconductor substrate is etched using a mask material to form an element formation region continuous in the first direction in a second direction orthogonal to the first direction. Forming an element isolation groove so as to be partitioned at predetermined intervals in the direction of, and embedding an element isolation insulating film in the element isolation groove so as to be at substantially the same surface position as the mask material. Patterning a laminated film of a protective insulating film for protecting the element isolation insulating film and a gate burying insulating film so as to be continuous in the first direction, and etching the mask material using the laminated film as a mask Removing and depositing a first gate material film on the semiconductor substrate via a first gate insulating film and polishing the surface of the first gate material film, thereby separating the first gate material film on the element isolation insulating film by the laminated film. Forming a charge storage layer, and removing the gate burying insulating film on the element isolation insulating film, and then forming a second gate insulating film on the charge storage layer and the protective insulating film via a second gate insulating film. Depositing a gate material film, and sequentially etching the second gate material film, the second gate insulating film and the charge storage layer to form a control gate continuous in a second direction and self-aligned with the control gate. Patterning the charge storage layer separated in one direction.

The structures, materials and the like used for each part of the storage device according to the present invention are as follows. The element isolation insulating film is formed by a method of forming a groove in a semiconductor substrate and filling the groove in the groove. It is not always necessary that the inside of the element isolation insulating film is an insulating film entirely. For example, a semiconductor such as polycrystalline silicon may be embedded in a groove formed in a semiconductor substrate via an insulating film via an insulating film, and the surface thereof may be covered with the insulating film. The element isolation insulating film can also be formed by a selective oxidation method (LOCOS). The element formation region is an active layer region partitioned by the element isolation insulating film. The first gate insulating film is a tunnel insulating film. The tunnel insulating film is preferably a silicon oxide film formed by thermal oxidation, a silicon nitride film formed by thermal nitridation or a deposition method, or a stacked film thereof (for example, an ONO film)
It is. Further, the tunnel insulating film may be a silicon oxynitride film.

The first gate is a charge storage layer, in other words, a floating gate. The first gate is made of polycrystalline silicon or amorphous silicon whose electric conductivity is increased by impurity doping. The second gate insulating film is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film of a silicon oxide film and a silicon nitride film (for example, an ONO film). The second gate is a control gate. The second gate
In addition to polycrystalline silicon or amorphous silicon whose electric conductivity is increased by impurity doping, silicide of a refractory metal such as tungsten (W), a laminated film of silicide and silicon, and titanium (Ti) on silicon Metals such as salicide and aluminum which are deposited and chemically reacted with each other are used. The protective insulating film provided on the element isolation insulating film needs to be an insulating film different from the element isolation insulating film, in other words, an insulating film having different etching characteristics from the element isolation insulating film. For example, when the element isolation insulating film is a silicon oxide film, a silicon nitride film or the like is used as the protective insulating film.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 shows an EEPR according to an embodiment 1.
3 shows a cross-sectional structure of a main part of the OM. FIG. 1A is a cross-sectional view of the memory cell section in the word line (WL) direction (the channel width direction of the memory cell), and FIG.
FIG. 3 is a cross-sectional view in the L) direction (the channel length direction of the memory cell). FIG. 1C shows a cross-sectional structure of a peripheral circuit transistor.

In the p-type silicon substrate 1, an element isolation region 2 is defined by embedding an element isolation insulating film 2 by, for example, the STI technique. In the memory cell array region, a tunnel insulating film 4 serving as a first gate insulating film is formed in an element forming region.
Through a first gate material film 5a and a second gate material film 5b as a charge storage layer.
(Floating gate) 5 is formed. A second gate (control gate) 8 made of a third gate material film is formed on the floating gate 5 with a second gate insulating film 7 interposed therebetween. The control gate 8 is continuously patterned in the plane of FIG. 1A, and this becomes a word line. An n + -type diffusion layer 6 serving as a source and a drain is formed in the control gate 8 in a self-aligned manner.

The second part forming the floating gate 5 of the memory cell
The gate material film 5b is patterned so as to partially overlap the element isolation insulating film 2 from the element formation region 3 which is sandwiched between the element isolation insulating films 2 and formed as shown in FIG. In addition, the upper surface of the floating gate 5 is substantially flat throughout. The flattening of the surface of the floating gate 5 can be achieved by narrowing the width of the element forming region 3 sandwiched between the element isolation insulating films 2 without performing an active planarization process. This can be achieved by selecting a deposition film thickness of the floating gate 5 larger than that.

On the other hand, the size of the peripheral circuit transistor is generally larger than that of the memory cell. Therefore, as shown in FIG. 1C, on the upper surface of the first gate 5 ′ formed using the same material as the memory cell array portion and the floating gate 5,
The step between the element isolation insulating film 2 and the element formation region 3 is reflected. At this time, the element formation region 3 of the memory cell
The thickness of the upper floating gate 5 is a + b. That is, the step difference b between the element isolation insulating film 2 and the element formation region 2 is added to the film thickness a on the element isolation insulating film 2. On the other hand, the film thickness of the first gate 5 'on the element formation region 3 of the peripheral circuit transistor is d. Therefore, the thickness a + b of the floating gate 5 on the element formation region of the memory cell is larger than the thickness d of the gate 5 ′ on the element formation region of the peripheral circuit transistor. In the peripheral circuit transistor, the first gate 5 'and the second gate 8' (the control gate 8 of the memory cell)
(Same material as above) is used as a gate electrode by short-circuiting at an appropriate position.

As described above, the upper surface of the floating gate 5 of the memory cell is substantially flat when the width of the element forming region is small and the deposited film thickness of the gate material film is thicker than a certain value. When the surface of the floating gate 5 is flat as described above, the variation in the capacitance coupling between the floating gate 5 and the control gate 8 is reduced, and the characteristics are uniform among a plurality of memory cells. Become. Therefore, it is possible to realize an EEPROM having excellent data rewriting performance, specifically, a small threshold distribution in a data write state or an erase state.

[Second Embodiment] FIG. 2 is a plan view of a memory cell array region of a NOR type EEPROM according to a second embodiment. FIG. 3A, FIG. 3B and FIG. 3C show cross sections AA ′, BB ′ and CC ′ of FIG. 2, respectively. In these figures, parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG.

The p-type silicon substrate 1 has an element which is elongated in the y direction (bit line direction) orthogonal to the x direction by the element isolation insulating films 2 formed at equal intervals in the x direction (word line direction) of FIG. The formation region 3 is divided into a plurality of sections. A charge storage layer (floating gate) 5 is formed in the element forming region 3 via a tunnel insulating film 4, and a control gate 8 is formed on the floating gate 5 via an inter-gate insulating film 7. The floating gate 5 is formed independently for each memory cell, and the control gate 8 is formed continuously in the x direction and becomes a word line WL.

The floating gate 5 has a first gate material film 5a and a second gate material film 5b as in the previous embodiment.
And the surface thereof is formed substantially flat. The control gate 8 and the floating gate 5 are formed with self-aligned side ends in the y direction. By performing ion implantation using the stacked gate as a mask, an n + type diffusion layer 6 serving as a source and a drain of the memory cell is formed.
The surface on which the memory cells are formed is covered with an interlayer insulating film 9, on which bit lines (BL) 10 are continuously arranged in the y direction.

The floating gate 5 is formed so as to partially overlap the element isolation region 2 from the element formation region 3 and, as shown in the cross section of FIG. And is separated into individual memory cells. Then, between the ends of the floating gates 5 which are adjacent to and opposed to each other in the x direction on the element isolation insulating film 2, in order to prevent the reduction of the thickness of the element isolation insulating film 2 while being self-aligned with this end. A protective insulating film 11 is provided. Actually, as described later, the second gate material film 5b of the floating gate 5 is buried by the damascene method so as to be aligned with the protective insulating film 11, and is cut by the protective insulating film 11 in the x direction. . As shown in FIG. 2, the protective insulating film 11 is continuously provided on the element isolation insulating film 2 in the y direction.
It is also provided in a region where the floating gate 5 and the control gate 8 are not provided.

The protective insulating film 11 needs to be an insulating film different from the element isolation insulating film 2. For example, when the element isolation insulating film 2 mainly includes a silicon oxide film, an insulating film mainly including a silicon nitride film is used as the protective insulating film 11. The thickness of the protective insulating film 11 is the same as that of the floating gate 5.
(More specifically, the film thickness of the second gate material film 5b).

Next, a manufacturing process of the EEPROM cell array according to this embodiment will be described with reference to FIGS. 4A to 4C to 10A to 10C which show process cross sections corresponding to FIGS. 3A to 3C, respectively. . As shown in FIGS. 4A to 4C, after a tunnel insulating film 4 is formed on a p-type silicon substrate 1 by thermal oxidation or the like, a first gate material film 5a is deposited, and a mask material 21 is pattern-formed thereon. . First
The gate material film 5a is, for example, a polycrystalline silicon film.
The mask material 21 is, for example, a silicon nitride film patterned so as to cover the element formation region. This mask material 2
1 to form a first gate material film 5a,
Etching is performed by E to form a groove 20 in the element isolation region.

Then, as shown in FIGS. 5A to 5C, an element isolation insulating film 2 made of a silicon oxide film is buried in a groove 20 formed in the substrate 1 so that the surface becomes flat. In order to flatten the surface, for example, a silicon oxide film may be deposited thicker than the groove depth, and a CMP process may be performed on the silicon oxide film using the mask material 21 made of a silicon nitride film as a stopper.

Next, as shown in FIGS. 6A to 6C, a protective insulating film 11 for protecting the element isolation insulating film 2 is deposited on the substrate which has been subjected to element isolation and flattened. A gate burying insulating film 22 for burying is deposited. Specifically, the protective insulating film 11 is a silicon nitride film, and the insulating film 22 for embedding the gate is made of TE.
This is an OS oxide film. Thereafter, as shown in FIGS. 7A to 7C, the gate-burying insulating film 22 is formed on the element isolation insulating film 2 as a mask pattern continuous in the y direction of FIG. 2 by lithography and etching. Then, using the insulating film 22 for burying the gate as a mask, the protective insulating film 11 is used.
, And the mask material 21 above the element formation region 3 is removed by etching.

Thereafter, a polycrystalline silicon film is thickly deposited as the second gate material film 5b on the entire surface, and is flattened by CMP using the gate burying insulating film 22 as a stopper. Thereby, as shown in FIGS. 8A to 8C,
In the x direction, the second gate material film 5b is separated from the element isolation insulating film 2 by the gate burying insulating film 22.
Is embedded. Thereafter, the gate burying insulating film 22 is formed.
Is removed by wet etching with hydrofluoric acid or the like. At this time, the protective insulating film 11 made of the silicon nitride film is not etched but remains on the element isolation insulating film 2. That is, the first
In the stacked film of the gate material film 5a and the second gate material film 5b, the memory cells adjacent to each other across the element isolation insulating film 2 are separated on the element isolation insulating film, The film 2 is covered with the protective insulating film 11.

In this embodiment, the gate-burying insulating film 22 is removed after the formation of the floating gate 5 as described above, but the protective insulating film 11 is left on the element isolation insulating film 2 as it is. Thereafter, as shown in FIGS. 9A to 9C,
An ONO film is formed as a second gate insulating film 7 on the entire surface,
A third gate material film 8a is deposited thereon. The third gate material film 8a is a polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal film, a metal silicide film, a salicide film, or the like. Thereafter, the third gate material film 8a is etched to form a pattern as a control gate 8 which becomes a word line WL continuous in the x direction, as shown in FIGS. 10A to 10C. At the same time, the underlying floating gate 5 is also patterned with the control gate 8 in a self-aligned manner. The position of the upper surface of the floating gate 5 is higher than the position of the upper surface of the protective insulating film 11 on the element isolation insulating film 2. Therefore, the control gate 8 is
Are formed not only on the upper surface but also on the side surfaces via the second gate insulating film 7.

3A to 3C by ion implantation.
The diffusion layer 6 is formed as shown in FIG. Then, an interlayer insulating film 9 is deposited, a contact hole is opened, and a bit line 10 is provided. As described above, according to this embodiment, each floating gate 5 is separated on the element isolation insulating film 2 by embedding the gate material film by a damascene method, not by etching the gate material film. Therefore, unlike the related art, a groove is not formed in the element isolation insulating film as in the case where the gate material film is slit on the element isolation insulating film. Thereby, short-circuit failure between control gates is suppressed. 7A to 7C, in the step of removing the mask material 21 used for processing the element isolation groove, the element isolation insulating film 2 is protected by the protective insulating film 11 and the mask material 22. Film reduction of the film 2 is prevented. Further, in the step of patterning the control gate 8 and the floating gate 5 shown in FIGS. 10A to 10C, an etching step of the gate insulating film 7 made of the ONO film is included.
As is clear from C, the surface of the element isolation insulating film 2 is protected by the protective insulating film 11, so that the element isolation insulating film 2 is prevented from being reduced in film thickness.

In the above embodiment, the protective insulating film 11 on the element isolation insulating film 2 is left without being removed to the end, but the gate burying insulating film 22 is removed in the state of FIG. 5B. After that, the protective insulating film 11 may be subsequently removed. In this case, the process of patterning the control gate 8 and the floating gate 5, in particular, the process of etching the gate insulating film 7 causes a decrease in the thickness of the element isolation insulating film 2. However, unlike the conventional method in which a groove is formed on the element isolation insulating film before depositing the gate material film, at least no groove is formed in the element isolation insulating film 2 at the time of depositing the gate material film. The effect of preventing a short circuit accident is obtained.

[Embodiment 3] FIGS. 11A and 11B show a sectional structure of an EEPROM cell array according to Embodiment 3 in correspondence with FIGS. 3A and 3B. In this embodiment, the conditions of the element isolation step and the gate formation step are different from the previous embodiment, and the upper end corner of the element formation region 3 is rounded. However, the basic structure is the same as that of the previous embodiment, and the plan view is the same as FIG.

The manufacturing process of this embodiment will now be specifically described with reference to FIGS. FIG.
As shown in (a), a mask material 3 for element isolation processing is formed on the surface of a p-type silicon substrate 1 via a sacrificial oxide film 4a.
1 is patterned. In this embodiment, the mask material 31 is polycrystalline silicon. The substrate is etched by RIE using the mask material 31 to form the element isolation groove 2.
0 is formed. Next, by performing thermal oxidation, an oxide film is formed on the exposed surface of the element isolation groove 20, and at the same time, a bird's beak oxide film is cut into the upper part of the element formation region 3.
Perform rounding. Thereafter, as shown in FIG.
A silicon oxide film is buried flat as the element isolation insulating film 2 in the same manner as in the previous embodiment. In order to flatten the surface, for example, a silicon oxide film is deposited thicker than the groove depth, and a CMP process may be performed on the silicon oxide film using the mask material 31 made of a polycrystalline silicon film as a stopper.

Next, as shown in FIG. 12 (c), a protective insulating film 11 for protecting the element isolation insulating film 2 is deposited on the element-isolated and flattened substrate, and a floating gate is formed separately. A gate burying insulating film 32 for deposition. Specifically, the protective insulating film 11 is a silicon nitride film,
The gate burying insulating film 32 is a TEOS oxide film.
Thereafter, as shown in FIG. 13A, the gate burying insulating film 32 is formed on the element isolation insulating film 2 by lithography and etching as a mask pattern that is continuous in the y direction of FIG. Then, the insulating film 32 for burying the gate is formed.
Is used as a mask to etch the protective insulating film 11, and then the mask material 31 in the element formation region is removed by etching.

Thereafter, a polycrystalline silicon film is deposited thickly as a first gate material film on the entire surface, and is flattened by a CMP process using the gate burying insulating film 32 as a stopper. As a result, as shown in FIG. 13B, the gate burying insulating film 32 is formed on the element isolation insulating film 2 in the x direction.
The floating gate 5 is patterned in a state separated by the above. After that, the gate burying insulating film 32 is removed by wet etching with hydrofluoric acid or the like. As a result, the floating gate 5 is separated on the element isolation insulating film 2 between the memory cells adjacent to each other with the element isolation insulating film interposed therebetween, and the floating gate 5 is in a state where the protective insulating film 11 is disposed at the isolation portion. Become.

The insulating film 32 for burying the gate is removed after the formation of the floating gate 5 as described above.
Is left on the element isolation insulating film 2 as it is. After this,
As shown in FIG. 13C, a control gate 8 is formed by depositing a second gate material film via an ONO film as a second gate insulating film 7. The second gate material film is a polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal film, a metal silicide film, a salicide film, or the like. Control gate 8
As shown in FIG. 2 or FIG. 3B, the floating gate 5 is patterned in a self-aligned manner with the control gate 8 at the same time as the word line WL continuous in the x direction. The position of the upper surface of the floating gate 5 is higher than the position of the upper surface of the protective insulating film 11 on the element isolation insulating film 2. Therefore, the control gate 8 is formed not only on the upper surface but also on the side surface of the floating gate 5 via the second gate insulating film 7.

In this embodiment, the floating gate 5 is formed via the first gate insulating film 4 after element isolation, but the mask material is removed by the protective insulating film 11 arranged on the element isolation insulating film 2. In the process, the thickness of the element isolation insulating film 2 is prevented from being reduced.
This is similar to the previous embodiment in that the film thickness reduction is prevented.

Fourth Embodiment In the second and third embodiments, only the memory cell array region has been described. However, a peripheral circuit formed simultaneously with the memory cell array preferably has a structure as shown in FIG. . FIG.
(A) and (b) each show one peripheral circuit transistor Q
And a plan view of the periphery thereof and a sectional view taken along the line CC ′. That is, the same protective insulating film 11 as the protective insulating film 11 formed on the element isolation insulating film 2 in the memory cell array region is formed as a dummy pattern on the element isolation insulating film 2 around the peripheral circuit transistor Q, for example, with a periodic pattern. .

As in the memory cell array region, the gates of the peripheral circuit transistor Q are overlapped with each other via a gate insulating film, and are short-circuited at an appropriate position.
Of the gates 8 ′. In this case, the first gate 5 'is flattened and embedded by the damascene method as described in the second and third embodiments. CMP
It is known that in a flattening step by processing, polishing progresses rapidly in a place where a space to be embedded is wide, and uniform flattening cannot be performed. As shown in FIG.
Is formed as a dummy pattern around the gate insulating film 11 in the step of polishing and embedding the material film of the gate 5 'formed simultaneously with the floating gate 5 of the memory cell, the protective insulating film 11 serves as a stopper, Flattening with good uniformity becomes possible.

The present invention is not limited to the above embodiment.
For example, in the embodiment, the NOR type EEPROM has been described. However, a NAND type, an AND type, and a DIN having a nonvolatile memory cell having a stacked gate structure of a charge storage layer and a control gate are provided.
The present invention can be similarly applied to other EEPROMs such as an OR type.

[0052]

As described above, according to the present invention, the floating gate surface is flattened, the variation in capacitance coupling when the memory cell is miniaturized is suppressed, and excellent data rewriting performance is exhibited. EEPRO
M can be obtained. In addition, by disposing a protective insulating film on the element isolation insulating film between the memory cells, it is possible to prevent the reduction of the element isolation insulating film and the short circuit between the gates to separate the charge storage layer, thereby miniaturizing the memory cell. EEPRO planned
M can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a sectional structure of a memory cell and a peripheral circuit transistor of an EEPROM according to a first embodiment of the present invention;

FIG. 2 is a plan view of a memory cell array of an EEPROM according to a second embodiment of the present invention.

FIG. 3A is a sectional view taken along line A-A 'of FIG. 2;

FIG. 3B is a sectional view taken along line B-B 'of FIG.

FIG. 3C is a sectional view taken along line C-C 'of FIG.

FIG. 4A is a cross-sectional view along AA 'showing an element isolation groove forming step of Embodiment 2;

FIG. 4B is a cross-sectional view along the line BB 'showing the same element isolation groove forming step.

FIG. 4C is a cross-sectional view along the line CC 'showing a step of processing the element isolation groove.

FIG. 5A is an AA ′ sectional view showing a step of embedding an element isolation insulating film of Embodiment 2;

FIG. 5B is a view illustrating a step of embedding the element isolation insulating film in FIG.
It is B 'sectional drawing.

FIG. 5C is a view illustrating a step of embedding the element isolation insulating film in FIG.
It is C 'sectional drawing.

FIG. 6A is a sectional view along AA ′ showing a step of forming a protective insulating film in Embodiment 2;

FIG. 6B is a cross-sectional view along the line BB 'showing the step of forming the protective insulating film.

FIG. 6C is a sectional view along a CC 'line showing the step of forming the protective insulating film.

FIG. 7A is a sectional view along AA 'showing a step of forming a protective insulating film pattern according to the second embodiment.

FIG. 7B is a cross-sectional view illustrating a step of forming the protective insulating film pattern.
It is B 'sectional drawing.

FIG. 7C is a view illustrating a protective insulating film pattern forming step C- in FIG.
It is C 'sectional drawing.

FIG. 8A is a sectional view along AA 'showing a step of forming a second gate material film of Embodiment 2;

FIG. 8B is a view showing a step of forming a second gate material film in FIG.
It is B 'sectional drawing.

FIG. 8C is a sectional view showing a step of forming the second gate material film, C-
It is C 'sectional drawing.

FIG. 9A is a sectional view along AA 'showing a step of forming a third gate material film of Embodiment 2;

FIG. 9B is a view illustrating a step of forming a third gate material film in FIG.
It is B 'sectional drawing.

FIG. 9C is a cross-sectional view showing a step of forming the third gate material film in FIG.
It is C 'sectional drawing.

FIG. 10A is a sectional view along AA 'showing a gate electrode patterning step in Embodiment 2;

FIG. 10B is a diagram illustrating a gate electrode patterning process B-
It is B 'sectional drawing.

FIG. 10C is a diagram illustrating a gate electrode patterning process C-
It is C 'sectional drawing.

FIG. 11 is an EEPROM according to a third embodiment of the present invention;
3A and 3B are cross-sectional views of the memory cell array of FIG.

FIG. 12 is a sectional view showing a manufacturing step of the memory cell according to the third embodiment;

FIG. 13 is a cross-sectional view showing a manufacturing step of the memory cell of Embodiment 3;

FIG. 14 is an EEPROM according to a fourth embodiment of the present invention.
2A and 2B are a plan view and a cross-sectional view illustrating a configuration of a peripheral circuit transistor region of FIG.

FIG. 15 is a plan view of a memory cell array of a conventional EEPROM.

FIG. 16 is a sectional view taken along line AA ′ and line BB ′ of FIG. 15;

FIG. 17 is a diagram showing dimensions of respective parts of a conventional memory cell structure.

FIG. 18 is a cross-sectional view showing a manufacturing step of a conventional memory cell.

FIG. 19 is a cross-sectional view showing a manufacturing step of a conventional memory cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate, 2 ... element isolation insulating film, element formation area, 4 ... gate insulating film, 5 ... 1st gate (electric storage layer, floating gate), 6 ... n-type diffusion layer, 7 ... gate insulation Film, 8 second gate (control gate), 9 interlayer insulating film, 10 bit line, 11 protective insulating film, 21 mask material, 20 groove, 22, 32 gate insulating film,
31 ... Mask material.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA01 AB08 AB09 AD53 AD60 AG12 AG22 AG40 5F083 EP02 EP22 EP23 EP76 EP78 EP79 ER21 JA04 KA05 NA01 PR36 PR38 PR40

Claims (11)

[Claims]
1. A semiconductor substrate, an element isolation insulating film formed on the semiconductor substrate for partitioning an element formation region, and a first insulating film formed on the semiconductor substrate via a first gate insulating film. And a memory cell array in which memory cells having a second gate formed on the first gate with a second gate insulating film interposed therebetween are arranged in an array. The nonvolatile semiconductor memory device according to claim 1, wherein the first gate is patterned so as to partially overlap the element isolation insulating film from the element formation region, and has a substantially flat surface.
2. The method according to claim 1, further comprising:
2. The gate of claim 1, wherein the thickness of the gate is larger than the thickness of the gate on the element forming region of the peripheral circuit transistor.
14. The nonvolatile semiconductor memory device according to claim 1.
3. A semiconductor substrate, an element isolation insulating film formed on the semiconductor substrate for partitioning an element forming region, and a first gate insulating film formed on the semiconductor substrate via a first gate insulating film. And a memory cell array in which memory cells having a second gate formed on the first gate with a second gate insulating film interposed therebetween are arranged in an array. The first gate is patterned and formed so as to partially overlap the element isolation insulating film from above the element formation region, and is adjacent to the first gate and interposed between the element formation regions. A nonvolatile semiconductor memory device, wherein a protective insulating film is disposed on a film.
4. The nonvolatile semiconductor memory device according to claim 3, wherein a surface of said first gate is substantially flat.
5. The semiconductor device according to claim 1, wherein the second gate is provided on the first gate and the protective insulating film continuously over a plurality of memory cells arranged in a direction crossing the element isolation insulating film. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is provided via a gate insulating film.
6. The nonvolatile semiconductor memory device according to claim 3, wherein a thickness of said protective insulating film is smaller than a thickness of said first gate on said element isolation insulating film.
7. The nonvolatile semiconductor memory device according to claim 5, wherein said protective insulating film is provided continuously on said element isolation insulating film in a direction orthogonal to a longitudinal direction of said second gate. .
8. A protection insulating film formed simultaneously with the protection insulating film in a region of the memory cell array on a device isolation insulating film around a peripheral circuit transistor is arranged as a dummy pattern. 3. The nonvolatile semiconductor memory device according to 3.
9. A semiconductor substrate, an element isolation insulating film formed on the semiconductor substrate to partition a plurality of element formation regions continuous in one direction at a predetermined interval, and a plurality of memory cells on the semiconductor substrate. The memory cells are arranged in an array, and each memory cell is provided with a charge storage layer formed in the element formation region via a first gate insulating film and the element isolation layer on the charge storage layer through a second gate insulating film. A memory cell array having a control gate continuously arranged over a plurality of memory cells arranged in a direction crossing an insulating film, wherein the charge storage layer of the memory cell is formed from above the element formation region. The second gate insulating film and the control gate are patterned on the element isolation insulating film so as to partially overlap with each other, and adjacent to the charge storage layer, on the element isolation insulating film interposed between the element formation regions. A non-volatile semiconductor memory device, wherein a protective insulating film covered with a heat treatment is disposed.
10. A step of depositing a first gate material film on a semiconductor substrate via a first gate insulating film, and a step of patterning a mask material for element isolation on the first gate material film. Etching the first gate material film and the semiconductor substrate using the mask material to partition an element formation region continuous in a first direction at a predetermined interval in a second direction orthogonal to the first direction; Forming an element isolation groove so as to perform the step of: burying an element isolation insulating film in the element isolation groove so as to be at substantially the same surface position as the mask material; and forming a first direction on the element isolation insulating film. Patterning a laminated film of a protective insulating film for protecting the element isolation insulating film and an insulating film for burying the gate so as to be continuous; etching the mask material using the laminated film as a mask; Game Depositing a gate material film and polishing the surface thereof, thereby accumulating the charge having the stacked structure of the first gate material film and the second gate material film separated on the element isolation insulating film by the stacked film. Forming a layer, and removing the gate isolation insulating film on the element isolation insulating film, and then forming a third gate material on the charge storage layer and the protective insulating film via a second gate insulating film. Depositing a film, and sequentially etching the third gate material film, the second gate insulating film and the charge storage layer to form a control gate continuous with a second direction and a first self-aligned control gate. Forming a charge storage layer separated in directions by a patterning method.
11. An element isolation groove formed by etching a semiconductor substrate using a mask material so as to partition an element formation region continuous in a first direction at a predetermined interval in a second direction orthogonal to the first direction. Forming an element isolation insulating film in the element isolation groove so as to be at substantially the same surface position as the mask material; and element isolation so as to be continuous in a first direction on the element isolation insulating film. A step of patterning a laminated film of a protective insulating film for protecting the insulating film and an insulating film for burying a gate; a step of etching and removing the mask material using the laminated film as a mask; a first gate on the semiconductor substrate; By depositing a first gate material film via an insulating film and polishing the surface thereof,
Forming a charge storage layer separated on the element isolation insulating film by the laminated film; and removing the gate burying insulating film on the element isolation insulating film, and then forming the charge storage layer and the protective insulating film on the element separation insulating film. Depositing a second gate material film via a second gate insulating film, and sequentially etching the second gate material film, the second gate insulating film and the charge storage layer in a second direction. Forming a charge storage layer which is self-aligned with the control gate and which is separated in a first direction from the control gate.
JP24620699A 1999-08-31 1999-08-31 Nonvolatile semiconductor memory and its manufacturing method Pending JP2001077333A (en)

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JP24620699A JP2001077333A (en) 1999-08-31 1999-08-31 Nonvolatile semiconductor memory and its manufacturing method
TW89117513A TW484228B (en) 1999-08-31 2000-08-29 Non-volatile semiconductor memory device and the manufacturing method thereof
US09/651,021 US6555427B1 (en) 1999-08-31 2000-08-30 Non-volatile semiconductor memory device and manufacturing method thereof
CNB200410031257XA CN1310332C (en) 1999-08-31 2000-08-31 Nonvolatile semiconductor memory
KR1020000051025A KR100349279B1 (en) 1999-08-31 2000-08-31 Nonvolatile semiconductor memory device and manufacturing method thereof
CNB2004100600933A CN1310333C (en) 1999-08-31 2000-08-31 Non-volatile semiconductor memory device and manufacturing method thereof
CN 00131690 CN1183601C (en) 1999-08-31 2000-08-31 Non-volatile semiconductor storage device and mfg. method thereof
US10/393,944 US6818508B2 (en) 1999-08-31 2003-03-24 Non-volatile semiconductor memory device and manufacturing method thereof
US10/956,109 US7122432B2 (en) 1999-08-31 2004-10-04 Non-volatile semiconductor memory device and manufacturing method thereof

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768161B2 (en) 2001-06-01 2004-07-27 Kabushiki Kaisha Toshiba Semiconductor device having floating gate and method of producing the same
KR100629356B1 (en) 2004-12-23 2006-09-29 삼성전자주식회사 Flash memory devices having pillar pattern and methods of fabricating the same
US7115940B2 (en) 2003-01-29 2006-10-03 Renesas Technology Corp. Semiconductor device
KR100762865B1 (en) 2001-06-20 2007-10-08 주식회사 하이닉스반도체 method for manufacturing of flash memory device
KR100908771B1 (en) 2006-04-14 2009-07-22 가부시끼가이샤 도시바 Semiconductor devices
JP2009164271A (en) * 2007-12-28 2009-07-23 Toshiba Corp Semiconductor device and its manufacturing method
US7906816B2 (en) 2005-05-31 2011-03-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device including memory cells having floating gates and resistor elements

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768161B2 (en) 2001-06-01 2004-07-27 Kabushiki Kaisha Toshiba Semiconductor device having floating gate and method of producing the same
KR100762865B1 (en) 2001-06-20 2007-10-08 주식회사 하이닉스반도체 method for manufacturing of flash memory device
US7115940B2 (en) 2003-01-29 2006-10-03 Renesas Technology Corp. Semiconductor device
US7355242B2 (en) 2003-01-29 2008-04-08 Renesas Technology Corp. Semiconductor device
KR100629356B1 (en) 2004-12-23 2006-09-29 삼성전자주식회사 Flash memory devices having pillar pattern and methods of fabricating the same
US7906816B2 (en) 2005-05-31 2011-03-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device including memory cells having floating gates and resistor elements
KR100908771B1 (en) 2006-04-14 2009-07-22 가부시끼가이샤 도시바 Semiconductor devices
KR101021378B1 (en) 2006-04-14 2011-03-14 가부시끼가이샤 도시바 Semiconductor device
JP2009164271A (en) * 2007-12-28 2009-07-23 Toshiba Corp Semiconductor device and its manufacturing method

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