JP6266688B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a memory cell and a nonvolatile semiconductor memory device.

  Conventionally, Japanese Unexamined Patent Application Publication No. 2011-129816 (Patent Document 1) discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see FIG. 16 in Patent Document 1). In practice, this memory cell includes a drain region to which a bit line is connected and a source region to which a source line is connected. One select gate structure is formed on the memory well from the drain region toward the source region. A memory gate structure and another selection gate structure are arranged and formed in order. In a memory cell having such a structure, a charge storage layer is provided in the memory gate structure, and data is written by injecting charges into the charge storage layer, or charges in the charge storage layer are extracted. Thus, data can be erased.

  In practice, in such a memory cell, when a charge is injected into the charge storage layer, a low bit voltage from the bit line is applied while the voltage is blocked by another selection gate structure connected to the source line. This is applied to the channel layer of the memory gate structure through the select gate structure. At this time, a high memory gate voltage is applied to the memory gate electrode in the memory gate structure, and charges can be injected into the charge storage layer by a quantum tunnel effect caused by a voltage difference between the bit voltage and the memory gate voltage.

  In a nonvolatile semiconductor memory device in which memory cells having such a configuration are arranged in a matrix, a memory gate line to which a high voltage memory gate voltage is applied is shared by a plurality of memory cells. Therefore, when a high memory gate voltage is applied to the memory gate line in order to inject charge into the charge storage layer of one memory cell, the charge is stored in the charge storage layer in other memory cells sharing the memory gate line. Even when the implantation is not performed, a high memory gate voltage is applied to the memory gate electrode.

  Therefore, in this case, in the memory cell in which no charge is injected into the charge storage layer, the voltage application to the channel layer is blocked by another selection gate structure connected to the source line, and one selection gate structure A high bit voltage from the bit line is applied to the channel layer of the memory gate structure. As a result, in the memory gate structure in which a high voltage memory gate voltage is applied to the memory gate electrode, a high bit voltage is applied to the channel layer, so that the voltage difference between the memory gate electrode and the channel layer is small. As a result, no charge can be injected into the charge storage layer without the quantum tunnel effect.

JP 2011-129816 JP

  Thus, in the conventional memory cell in which no charge is injected into the charge storage layer, in order to prevent charge injection into the charge storage layer, a high voltage is applied from the bit line to the channel layer in accordance with the high voltage memory gate voltage. It was necessary to apply a bit voltage. Therefore, in the memory cell having such a configuration, it is necessary to increase the thickness of the selection gate insulating film of one selection gate structure connected to the bit line so as to withstand a high voltage bit voltage. There was a problem that it was difficult to achieve high-speed operation.

  In addition, in such a conventional memory cell, a high bit voltage may be applied to the bit line when blocking the charge injection into the charge storage layer. Therefore, even in the peripheral circuit controlling the memory cell, In order to withstand the bit voltage of the voltage, it is necessary to increase the thickness of the gate insulating film of the field effect transistor, and there is a problem that the area of the peripheral circuit is increased accordingly.

  Accordingly, the present invention has been made in consideration of the above points, and an object thereof is to propose a memory cell and a non-volatile semiconductor memory device that can realize a higher speed operation than before and can reduce the area of a peripheral circuit. To do.

  In order to solve this problem, a memory cell of the present invention includes a drain region formed on the surface of a memory well and connected to a bit line, a source region formed on the surface of the memory well and connected to a source line, and the drain A memory gate structure formed between a source region and a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked in this order on the memory well; and the drain region And a first select gate electrode is formed on the memory well between the memory gate structures via a first select gate insulating film, and one side wall spacer is provided on one side wall of the memory gate structure. And a second selection gate on the memory well between the source region and the memory gate structure. And a second select gate structure having a structure in which a second select gate electrode is formed via a gate insulating film, and adjacent to the other side wall of the memory gate structure via another side wall spacer. A charge storage gate voltage required to inject charges into the charge storage layer by a quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the memory well surface facing the memory gate electrode. The first selection gate structure cuts off the electrical connection between the drain region and the channel layer, and the second selection gate structure cuts off the electrical connection between the source region and the channel layer. Thus, a depletion layer is formed so as to surround the channel layer whose channel potential has increased based on the charge storage gate voltage, and the memory gate electrode and the front A channel from the channel layer to the first selection gate insulating film and the second selection gate insulating film by the depletion layer while reducing a voltage difference between the channel layers and preventing charge injection into the charge storage layer. It is characterized by preventing the potential from reaching.

  The memory cell of the present invention includes a drain region formed on the surface of the memory well and connected to the bit line, a source region formed on the surface of the memory well and connected to the source line, the drain region and the source A memory gate structure formed between the regions, in which a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode are sequentially stacked on the memory well; and the drain region and the memory gate A first selection gate electrode is formed on the memory well between the structures via a first selection gate insulating film, and is adjacent to one side wall of the memory gate structure via one side wall spacer. A first select gate structure and a second select gate insulating film on the memory well between the source region and the memory gate structure. A second select gate structure having a configuration in which a second select gate electrode is formed, the second select gate structure being adjacent to another side wall of the memory gate structure via another side wall spacer; And the width of the other side wall spacer is 5 [nm] or more and 40 [nm] or less, and the film thickness of the first selection gate insulating film and the second selection gate insulating film is 3 [nm] or less. Features.

  In such a memory cell, a charge storage gate voltage necessary for injecting charges into the charge storage layer by the quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the surface of the memory well facing the memory gate electrode. However, the first selection gate structure cuts off the electrical connection between the drain region and the channel layer, and the second selection gate structure cuts off the electrical connection between the source region and the channel layer. A depletion layer can be formed to surround the channel layer where the channel potential has risen based on the storage gate voltage. As a result, the voltage difference between the memory gate electrode and the channel layer is reduced to prevent charge injection into the charge storage layer. However, the depletion layer prevents the channel potential from reaching the first select gate insulating film and the second select gate insulating film from the channel layer. You can stop.

The nonvolatile semiconductor memory device of the present invention is connected in series with a plurality of memory cells connected in series in the order of the first selection transistor, the memory transistor, and the second selection transistor, and is shared by the memory cell column. And a bit line connected to a drain region of the first selection transistor, a first selection gate line shared by a memory cell row and connected to a first selection gate electrode of the first selection transistor, and the first selection transistor The second selection gate line connected to the second selection gate electrode of the two selection transistor, the source line connected to the source region of the second selection transistor, and the plurality of memory cells arranged in the matrix are shared. and wherein a single memory gate lines connected to the memory gate electrode of the memory transistor, the one of the memory gate line are electrically connected from each other And characterized in that it comprises a one memory gate line are shared in one of the memory cell rows, and other memory gate lines which are shared with other memory cell rows.

  According to the present invention, the bit line in the first selection gate structure and the second selection gate structure is not restricted by the charge storage gate voltage necessary for injecting the charge into the charge storage layer by the quantum tunnel effect. Since the voltage value of the bit line and the source line can be lowered to the voltage value necessary to cut off the electrical connection of the channel layer and the electrical connection of the source line and the channel layer. In accordance with the voltage reduction at the source line, each film thickness of the first selection gate insulating film of the first selection gate structure and the second selection gate insulating film of the second selection gate structure can be reduced. High speed operation can be realized.

  In addition, according to the present invention, since the voltage applied to the bit line and the source line can be reduced, the film thickness of the gate insulating film of the field effect transistor can be reduced even in the peripheral circuit for controlling the memory cell. The circuit area can be reduced.

1 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device including a memory cell of the present invention. FIG. 3 is a cross-sectional view showing a side cross-sectional configuration of a memory cell according to the present invention. It is the schematic where it uses for description of the gate insulating film capacity | capacitance and depletion layer capacity | capacitance in a memory gate structure. 6 is a table showing an example of voltage values at each portion during a data write operation, a data read operation, and a data erase operation. FIG. 5A is a schematic diagram showing a state immediately after the charge is injected into the charge storage layer in the memory cell of Comparative Example 1 in which the charge storage layer is also formed in the side wall spacer between the memory gate electrode and the first selection gate electrode. FIG. 5B is a schematic view showing a state in which charges in the charge storage layer are diffused with time after the charge is injected into the charge storage layer of FIG. 5A. It is the schematic which shows a mode when an electric charge is inject | poured into the charge storage layer in the memory cell by this invention. FIG. 7A shows Comparative Example 2 in which impurity diffusion regions are formed on the memory well surface between the memory gate structure and the first select gate structure and on the memory well surface between the memory gate structure and the second select gate structure, respectively. FIG. 7B is a schematic diagram showing the width of the depletion layer in the memory cell of the present invention, and FIG. 7C is a schematic diagram showing the width of the depletion layer when the impurity concentration of the memory well is changed. It is.

Hereinafter, modes for carrying out the present invention will be described. The description will be in the following order.
1. 1. Overall configuration of nonvolatile semiconductor memory device 2. Detailed configuration of memory cell 3. Operation principle for injecting charge into charge storage layer in write selection memory cell 4. Regarding an operation principle in which charge is not injected into the charge storage layer in a write non-selected memory cell in which a high voltage charge storage gate voltage is applied to the memory gate electrode. 5. Voltages during various operations in the nonvolatile semiconductor memory device 6. Structure of charge storage layer in memory cell of the present invention Action and effect8. Other embodiments

(1) Overall Configuration of Nonvolatile Semiconductor Memory Device In FIG. 1, reference numeral 1 denotes a nonvolatile semiconductor memory device, which has a configuration in which memory cells 2a, 2b, 2c, 2d according to the present invention are arranged in a matrix. The non-volatile semiconductor memory device 1 includes one bit line BL1 (1b) in memory cells 2a, 2c (2b, 2d) arranged in one direction (in this case, the column direction) among these memory cells 2a, 2b, 2c, 2d. BL2) is shared, and a predetermined bit voltage can be uniformly applied to each bit line BL1, BL2 by the bit voltage application circuit 10. In addition, the nonvolatile semiconductor memory device 1 includes one first selection gate line DGL1 (DGL2) in memory cells 2a and 2b (2c and 2d) arranged in another direction (in this case, the row direction) orthogonal to one direction. ), And the first selection gate voltage application circuit 11 can uniformly apply a predetermined first selection gate voltage to each of the first selection gate lines DGL1 and DGL2.

  Further, in the case of this embodiment, in the nonvolatile semiconductor memory device 1, one memory gate line MGL, one second selection gate line SGL, and one source line SL are connected to all the memory cells 2a. , 2b, 2c, and 2d, a predetermined memory gate voltage is applied to the memory gate line MGL by the memory gate voltage application circuit 13, and a predetermined value is applied to the second selection gate line SGL by the second selection gate voltage application circuit 14. The second selection gate voltage is applied, and the source voltage application circuit 15 can apply a predetermined source voltage to the source line SL.

  In this embodiment, one memory gate line MGL, one second selection gate line SGL, and one source line SL are shared by all the memory cells 2a, 2b, 2c, 2d. However, the present invention is not limited to this. For each memory cell 2a, 2b (2c, 2d) arranged in the other direction (row direction), a memory gate line and a second selection gate line are provided. And the source line may be shared.

  Incidentally, in this nonvolatile semiconductor memory device 1, all the memory cells 2a, 2b, 2c, 2d are formed in one memory well MPW made of, for example, P type, and a predetermined voltage is applied to the memory well MPW by the substrate voltage application circuit 17. The substrate voltage can be applied. Here, since these memory cells 2a, 2b, 2c, and 2d all have the same configuration, the following description will be focused on the memory cell 2a in the first row and the first column.

  In this case, the memory cell 2a has a bit line BL1 connected to a drain region (not shown) formed on the surface of the memory well MPW and a source region (not shown) formed on the surface of the memory well MPW. The source line SL is connected, and the memory gate structure 4, the first selection gate structure 5, and the second selection gate structure 6 are formed on the drain region and the memory well MPW between the source regions. Have a configuration.

  In practice, the memory cell 2a includes a first select gate structure 5 via a side wall spacer (not shown) on one side wall of the memory gate structure 4 formed on the memory well MPW between the drain region and the source region. And the second select gate structure 6 is disposed on the other side wall of the memory gate structure 4 via the side wall spacer, and the first select gate structure 6 is arranged on the memory well MPW from the bit line BL1 toward the source line SL. The selection gate structure 5, the memory gate structure 4, and the second selection gate structure 6 are arranged in this order.

  Here, in the first selection gate structure 5, the first selection gate electrode DG is formed on the memory well MPW between the sidewall spacer and the drain region via the first selection gate insulating film. A first selection gate line DGL1 is connected to the electrode DG. The first selection gate structure 5 includes a bit voltage applied from the bit line BL1 to the drain region of the surface of the memory well MPW at one end, and a first selection applied from the first selection gate line DGL1 to the first selection gate electrode DG. Due to the voltage difference with the gate voltage, a channel layer can be formed on the surface of the memory well MPW facing the first selection gate electrode DG.

  In this case, the first select gate structure 5 is formed by forming a channel layer on the surface of the memory well MPW facing the first select gate electrode DG, so that the bit line BL1 and the memory gate structure 4 are arranged. The channel layer on the surface of the well MPW is electrically connected, and the bit voltage from the bit line BL1 can be applied to the channel layer of the memory gate structure 4. On the other hand, the first select gate structure 5 has a channel layer formed by the bit line BL1 and the memory gate structure 4 by not forming a channel layer on the surface of the memory well MPW facing the first select gate electrode DG. The electrical connection with the layer can be cut off, and the application of the bit voltage from the bit line BL1 to the channel layer of the memory gate structure 4 can be prevented.

  In the second selection gate structure 6, the second selection gate electrode SG is formed on the memory well MPW between the sidewall spacer and the source region via the second selection gate insulating film, and the second selection gate electrode SG 2 Select gate line SGL is connected. The second selection gate structure 6 includes a source voltage applied from the source line SL to a source region on the surface of the memory well MPW at one end, and a second selection applied from the second selection gate line SGL to the second selection gate electrode SG. Due to the voltage difference with the gate voltage, a channel layer can be formed on the surface of the memory well MPW facing the second selection gate electrode SG.

  In this case, the second select gate structure 6 is configured such that the channel layer is formed on the surface of the memory well MPW facing the second select gate electrode SG, so that the source line SL and the memory in which the memory gate structure 4 is arranged The channel layer on the surface of the well MPW can be electrically connected. On the other hand, the second select gate structure 6 has a channel layer not formed on the surface of the memory well MPW facing the second select gate electrode SG, so that the source line SL and the channel layer of the memory gate structure 4 The electrical connection can be cut off, and the application of the source voltage from the source line SL to the channel layer of the memory gate structure 4 can be blocked.

  The memory gate structure 4 on the memory well MPW between the first select gate structure 5 and the second select gate structure 6 includes a lower gate insulating film, a charge storage layer EC, an upper gate insulating film on the memory well MPW, The memory gate electrode MG is stacked in this order, and the memory gate line MGL is connected to the memory gate electrode MG. The memory gate structure 4 having such a configuration generates a quantum tunnel effect due to a voltage difference between the memory gate electrode MG and the memory well MPW, and injects charges into the charge storage layer EC, or within the charge storage layer EC. It is designed to pull out the charge from.

(2) Detailed Configuration of Memory Cell Here, FIG. 2 is a sectional view showing a side sectional configuration of the memory cell 2a (2b). In practice, as shown in FIG. 2, for example, in the memory cell 2a, a P-type memory well MPW is formed on an insulating substrate 20 such as SiO ₂ via an N-type deep well layer DNW. A memory gate structure 4 that forms a transistor structure, a first selection gate structure 5 that forms an N-type MOS (Metal-Oxide-Semiconductor) transistor structure, and a second selection that also forms an N-type MOS transistor structure A gate structure 6 is formed in the memory well MPW.

In practice, a drain region 31 at one end of the first select gate structure 5 and a source region 34 at one end of the second select gate structure 6 are formed on the surface of the memory well MPW with a predetermined distance. The bit line BL1 is connected to the drain region 31, and the source line SL is connected to the source region. In the case of this embodiment, the drain region 31 and the source region 34 are selected to have an impurity concentration of 1.0E21 / cm ³ or more, while the memory well MPW has a surface region (where the channel layer CH is formed) for example, the impurity concentration of the region) from the surface to 50 [nm] is 1.0E19 / cm ³ or less, preferably is selected to be 3.0E18 / cm ³ or less.

The memory gate structure 4 is formed on the memory well MPW between the drain region 31 and the source region 34 via a lower gate insulating film 24a made of an insulating material such as SiO ₂ , for example, silicon nitride (Si ₃ N ₄ ), It has a charge storage layer EC made of silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), etc., and further on the charge storage layer EC via an upper gate insulating film 24b also made of an insulating member. It has a memory gate electrode MG. Thus, the memory gate structure 4 has a configuration in which the charge storage layer EC is insulated from the memory well MPW and the memory gate electrode MG by the lower gate insulating film 24a and the upper gate insulating film 24b.

  A side wall spacer 28a made of an insulating member is formed along one side wall of the memory gate structure 4, and the first selection gate structure 5 is adjacent to the memory gate structure 4 via the side wall spacer 28a. The sidewall spacer 28a formed between the memory gate structure 4 and the first selection gate structure 5 is formed with a predetermined film thickness, and the memory gate structure 4 and the first selection gate structure The body 5 can be insulated.

  The first selection gate structure 5 is an insulating member on the memory well MPW between the side wall spacer 28a and the drain region 31, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less. A first selection gate insulating film 30 is formed, and a first selection gate electrode DG to which a first selection gate line DGL1 is connected is formed on the first selection gate insulating film 30.

  Here, when the distance between the memory gate structure 4 and the first selection gate structure 5 is less than 5 [nm], the sidewall spacer 28a is applied when a predetermined voltage is applied to the memory gate electrode MG or the first selection gate electrode DG. On the other hand, when the memory gate structure 4 and the first select gate structure 5 exceed 40 [nm], the memory well between the memory gate electrode MG and the first select gate electrode DG The resistance at the MPW increases, and it becomes difficult for a read current to be generated between the memory gate structure 4 and the first selection gate structure 5 at the time of data reading described later. Therefore, in the case of this embodiment, the side wall spacer 28a between the memory gate structure 4 and the first selection gate structure 5 is preferably selected to have a width of 5 [nm] or more and 40 [nm] or less.

  A sidewall spacer 28b made of an insulating member is also formed on the other sidewall of the memory gate structure 4, and the second select gate structure 6 is adjacent to the sidewall spacer 28b via the sidewall spacer 28b. The side wall spacer 28b formed between the memory gate structure 4 and the second selection gate structure 6 is also formed with the same film thickness as the one side wall spacer 28a. The second select gate structure 6 can be insulated.

  The second selection gate structure 6 is an insulating member on the memory well MPW between the side wall spacer 28b and the source region 34, and has a thickness of 9 [nm] or less, preferably 3 [nm] or less. A second selection gate insulating film 33 is formed, and a second selection gate electrode SG connected to the second selection gate line SGL is formed on the second selection gate insulating film 33.

  Here, when the distance between the memory gate structure 4 and the second selection gate structure 6 is less than 5 [nm], the side walls when a predetermined voltage is applied to the memory gate electrode MG or the second selection gate electrode SG On the other hand, when the space between the memory gate structure 4 and the second selection gate structure 6 exceeds 40 [nm], there is a risk that a breakdown voltage failure may occur in the spacer 28b, between the memory gate electrode MG and the second selection gate electrode SG. The resistance in the memory well MPW is increased, and a read current is hardly generated between the memory gate structure 4 and the second selection gate structure 6 at the time of data reading described later. Therefore, in the case of this embodiment, it is desirable that the side wall spacer 28a between the memory gate structure 4 and the second selection gate structure 6 is also selected to have a width of 5 [nm] or more and 40 [nm] or less.

  Incidentally, in the case of this embodiment, the first selection gate electrode DG and the second selection gate electrode SG formed along the side wall of the memory gate electrode MG via the side wall spacers 28a and 28b are respectively connected to the memory gate electrode MG. As the distance increases, the top is formed in a side wall shape that descends toward the memory well MPW.

  The memory cells 2a, 2b, 2c, and 2d having such a configuration can be formed by a general semiconductor manufacturing process using a photolithography technique, a film forming technique such as oxidation or CVD, an etching technique, and an ion implantation method. The description is omitted here.

  Incidentally, the first selection gate electrode DG and the second selection gate electrode SG having the sidewall shape described above are formed by first forming the memory gate electrode MG covered with the sidewall spacers 28a and 28b on the memory well MPW, and then By forming a conductive layer on the memory well MPW so as to cover the side wall spacers 28a and 28b around the gate electrode MG, and then etching back the conductive layer, the side wall spacers 28a and 28b on the side wall of the memory gate electrode MG are formed. It can be formed in a sidewall shape along.

  Thus, the memory gate electrode MG is formed before the first selection gate electrode DG and the second selection gate electrode SG. In addition, the first selection gate electrode DG and the second selection gate electrode SG are formed using a conductive layer different from the memory gate electrode MG by a process subsequent to the semiconductor manufacturing process for forming the memory gate electrode MG. Yes.

(3) Operation principle of injecting charge into charge storage layer in write selection memory cell Next, for example, a case where charge is injected into the charge storage layer EC of the memory cell 2a and data is written into the memory cell 2a will be described below. . In this case, as shown in FIG. 2, a memory cell (also referred to as a write selection memory cell) 2a for injecting charges into the charge storage layer EC is supplied from the memory gate line MGL to the memory gate electrode MG of the memory gate structure 4. The channel layer CH can be formed along the surface of the memory well MPW opposed to the memory gate electrode MG by applying the charge storage gate voltage of V]. At this time, a gate-off voltage of 0 [V] is applied to the second selection gate structure 6 from the second selection gate line SGL to the second selection gate electrode SG, and 0 [V] from the source line SL to the source region 34. Source off voltage can be applied. Thus, the second select gate structure 6 includes the source region 34 to which the source line SL is connected, the memory gate MPW, without the channel layer being formed on the surface of the memory well MPW facing the second select gate electrode SG. The electric connection with the four channel layers CH can be cut off, and the voltage application from the source line SL to the channel layer CH of the memory gate structure 4 can be blocked.

  On the other hand, in the first selection gate structure 5, a first selection gate voltage of 1.5 [V] is applied from the first selection gate line DGL1 to the first selection gate electrode DG, and 0 [ V] charge storage bit voltage can be applied. As a result, the first select gate structure 5 becomes conductive in the memory well MPW facing the first select gate electrode DG, the drain region 31 to which the bit line BL1 is connected, the channel layer CH of the memory gate structure 4 and Can be electrically connected, and the channel layer CH of the memory gate structure 4 can be set to 0 [V] which is a charge storage bit voltage. At this time, the same substrate voltage of 0 [V] as the charge storage bit voltage can be applied to the memory well MPW.

  Thus, in the memory gate structure 4, since the memory gate electrode MG is 12 [V] and the channel layer CH is 0 [V], a large voltage of 12 [V] is generated between the memory gate electrode MG and the channel layer CH. A difference (12 [V]) is generated, and charges can be injected into the charge storage layer EC by the quantum tunnel effect generated thereby, and data can be written.

(4) Regarding the operation principle in which charge is not injected into the charge storage layer in a write non-selected memory cell in which a high voltage charge storage gate voltage is applied to the memory gate electrode. Here, in the nonvolatile semiconductor memory device 1 shown in FIG. Since the memory gate line MGL is shared by all the memory cells 2a, 2b, 2c, 2c, for example, the memory is injected only into the charge storage layer EC of the memory cell 2a in the first row and the first column. When a high-voltage charge storage gate voltage is applied to the gate line MGL, other memory cells (also referred to as write non-selected memory cells) 2b, 2c, and 2d that do not inject charge into the charge storage layer EC also pass through the memory gate line MGL. Thus, a high voltage charge storage gate voltage can be applied to each memory gate electrode MG.

  Here, in this case, in other memory cells 2b, 2c, and 2d that do not inject charge into the charge storage layer EC, even if a high voltage charge storage gate voltage is applied from the memory gate line MGL to the memory gate electrode MG, Thus, there is no need to apply a high bit voltage to the bit lines BL1 and BL2 in accordance with the high voltage charge storage gate voltage, and the bit line BL1 and the memory gate structure 4 can be connected by the first selection gate structure 5. The memory gate structure is simply cut off from the electrical connection with the channel layer CH and the electrical connection between the source line SL and the channel layer CH of the memory gate structure 4 by the second selection gate structure 6. The charge injection into the charge storage layer EC of the body 4 can be prevented.

  Here, focusing on the memory cell 2b in the first row and the second column among the memory cells 2b, 2c, and 2d, as shown in FIG. 2, the memory gate structure 4 of the other memory cell 2b is also Since a 12 [V] charge storage gate voltage is applied from the memory gate line MGL to the memory gate electrode MG, the charge storage gate voltage is transmitted to the memory well MPW, and the surface of the memory well MPW facing the memory gate electrode MG A channel layer CH may be formed along

  In the second select gate structure 6 of the memory cell 2b, a gate-off voltage of 0 [V] is applied from the second select gate line SGL to the second select gate electrode SG, and 0 [V] is applied from the source line SL to the source region 34. A source off voltage of V] can be applied. As a result, the second select gate structure 6 of the memory cell 2b becomes non-conductive at the memory well MPW facing the second select gate electrode SG, and the source region 34 to which the source line SL is connected and the memory gate structure 4 The electrical connection with the channel layer CH can be cut off.

  In addition to this, a first selection gate voltage of 1.5 [V] is applied to the first selection gate structure 5 of the memory cell 2b from the first selection gate line DGL1 to the first selection gate electrode. An off voltage of 1.5 [V] can be applied to the drain region 31 from the line BL2. As a result, in this first select gate structure 5, the memory well MPW facing the first select gate electrode DG is turned off, the drain region 31 to which the bit line BL2 is connected, and the channel of the memory gate structure 4 The electrical connection with the layer CH can be interrupted.

  As described above, in the memory gate structure 4 of the memory cell 2b, the memory well MPW is in a non-conducting state under the first selection gate structure 5 and the second selection gate structure 6 on both sides. The channel layer CH formed on the surface of the memory well MPW by MG is in a state where the electrical connection between the drain region 31 and the source region 34 is cut off, and the depletion layer D can be formed around the channel layer CH.

  Here, a capacitance (hereinafter referred to as a gate insulating film capacitance) C2 obtained by the three-layer configuration of the upper gate insulating film 24b, the charge storage layer EC, and the lower gate insulating film 24a is formed in the memory well MPW. As for the capacity of depletion layer D (hereinafter referred to as depletion layer capacity) C1 surrounding channel layer CH, as shown in FIG. 3, gate insulating film capacity C2 and depletion layer capacity C1 are connected in series. For example, assuming that the gate insulating film capacitance C2 is three times the depletion layer capacitance C1, the channel potential Vch of the channel layer CH can be obtained from the following equation.

  Therefore, in this embodiment, the substrate voltage CV of the memory well MPW is 0 [V], and the memory gate voltage MV of the memory gate electrode MG is 12 [V]. The potential Vch is 9 [V].

  Thus, in the memory gate structure 4, even when a charge storage gate voltage of 12 [V] is applied to the memory gate electrode MG, the channel potential Vch of the channel layer CH surrounded by the depletion layer D in the memory well MPW is 9 Therefore, the voltage difference between the memory gate electrode MG and the channel layer CH is as small as 3 [V]. As a result, charge injection into the charge storage layer EC can be performed without the quantum tunnel effect. Can be blocked.

  In addition, in this memory cell 2b, an impurity diffusion region having a high impurity concentration is not formed in the memory well MPW region between the memory gate structure 4 and the first selection gate structure 5. The depletion layer D can be reliably formed around the channel layer CH formed around the surface of the memory well MPW, and the channel potential Vch can reach the first selection gate insulating film 30 from the channel layer CH by the depletion layer D. Can be blocked.

  As a result, in the first select gate structure 5, even if the first select gate insulating film 30 is thinly formed in accordance with the low voltage applied to the drain region 31 from the bit line BL2, the channel Since the channel potential Vch of the layer CH is blocked by the depletion layer D, the dielectric breakdown of the first select gate insulating film 30 due to the channel potential Vch can be prevented.

  In addition, since the impurity diffusion region having a high impurity concentration is not formed in the region of the memory well MPW between the memory gate structure 4 and the second selection gate structure 6, the memory well MPW The depletion layer D can be reliably formed around the channel layer CH formed around the surface, and the depletion layer D can prevent the channel potential Vch from reaching the second selection gate insulating film 33 from the channel layer CH.

  As a result, even in the second selection gate structure 6, even if the film thickness of the second selection gate insulating film 33 is reduced in accordance with the low source voltage applied from the source line SL to the source region 34, the channel layer Since the channel potential Vch of CH is blocked by the depletion layer D, the dielectric breakdown of the second select gate insulating film 33 due to the channel potential Vch can be prevented.

  When the above operation is executed in the write selected memory cell 2a or the write non-selected memory cell 2b, the channel potential at the start of the operation varies depending on the charge accumulation state in the memory cells 2a and 2b. There is a risk of doing. Therefore, before the write operation, the potential of the bit lines BL1, BL2 or the source line SL is set to, for example, 0 [V], the first selection gate electrode DG or the second selection gate electrode SG is set to, for example, 1.5 [V], and the memory gate More preferably, the electrode MG is set to 1.5 [V], for example, and an operation of aligning the channel potentials of the memory cells 2a, 2b, 2c, and 2d with the potentials of the bit lines BL1 and BL2 or the source line SL is added. In that case, after the channel potentials are aligned, the first selection gate electrode DG or the second selection gate electrode SG is returned to the gate-off voltage of 0 [V], and then the write operation is started.

(5) Voltage during Various Operations in Nonvolatile Semiconductor Memory Device Here, FIG. 4 shows a data write operation for injecting charge into, for example, the charge storage layer EC of the memory cell 2a in the nonvolatile semiconductor memory device 1 of the present invention. (“Prog”), during a data read operation (“Read”) on whether or not charges are stored in the charge storage layer EC of the memory cell 2a, and the charges in the charge storage layer EC of the memory cells 2a and 2c 6 is a table summarizing voltage values of respective parts during a data erasing operation (“Erase”).

  Here, the column “Read” in FIG. 4 indicates the voltage value during the data read operation. In this case, for example, in the selected column in which the memory cell 2a for reading data is arranged, the second select gate line SGL A second selection gate voltage of 1.5 [V] is applied to the source line SL, and a source voltage of 0 [V] is applied to the source line SL, whereby the second selection gate structure 6 of the memory cell 2a is provided. The memory well MPW becomes conductive, and the source line SL and the channel layer CH of the memory gate structure 4 can be electrically connected. At this time, a first selection gate voltage of 1.5 [V] is applied to the first selection gate line DGL1 connected to the first selection gate structure 5 of the memory cell 2a from which data is read, and the first selection gate A read voltage of 1.5 [V] can be applied to the bit line BL1 connected to the drain region 31 adjacent to the structure 5.

  Further, 0 [V] can be applied from the memory gate line MGL to the memory gate electrode MG in the memory gate structure 4 of the memory cell 2a from which data is read. At this time, in the memory cell 2a from which data is read, when charges are accumulated in the charge accumulation layer EC of the memory gate structure 4 (when data is written), the memory well below the memory gate structure 4 The MPW becomes non-conductive, and the memory gate structure 4 can cut off the electrical connection between the first select gate structure 5 and the second select gate structure 6. Thereby, in the memory cell 2a from which data is read, the read voltage of 1.5 [V] on the bit line BL1 connected to the drain region adjacent to the first select gate structure 5 can be maintained as it is.

  On the other hand, in the memory cell 2a from which data is read, when no charge is accumulated in the charge accumulation layer EC of the memory gate structure 4 (when data is not written), the memory well MPW below the memory gate structure 4 Is in a conductive state, and the first selection gate structure 5 and the second selection gate structure 6 are electrically connected via the memory gate structure 4, and as a result, 0 [V] is supplied via the memory cell 2a. The source line SL is electrically connected to the 1.5 [V] bit line BL1. Thus, in the memory cell 2a that reads data, the read voltage of the bit line BL1 is applied to the source line SL of 0 [V], so that the read voltage of 1.5 [V] applied to the bit line BL1 is increased. descend. Thus, in the nonvolatile semiconductor memory device 1, data indicating whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2a is read by detecting whether or not the read voltage of the bit line BL1 has changed. Can do.

  In the memory cell 2c (FIG. 1) that is connected to the bit line BL1 to which a read voltage of 1.5 [V] is applied and that does not read data, the first selection gate as shown in “non-selected row” in FIG. When 0 [V] is applied to the line DGL1 and the memory well MPW below the first select gate structure 5 is turned off, the charge accumulation state in the charge accumulation layer EC affects the read voltage of the bit line BL1. Can be prevented.

  Incidentally, the column “Erase” in FIG. 4 shows a voltage value at the time of data erasing operation for extracting charges in the charge storage layer EC of the memory cells 2 a and 2 c in the nonvolatile semiconductor memory device 1. In this case, a memory gate voltage of -12 [V] is applied to the memory gate structure 4 of each memory cell 2a, 2c from the memory gate line MGL to the memory gate electrode MG. Data in the charge storage layer EC can be extracted toward the memory well MPW to erase data.

  Note that the column “Prog” in FIG. 4 indicates the voltage value (“selected column” and “selected row”) when the charge is injected into the charge storage layer EC of the memory cell 2a, and the charge storage layer EC of the memory cell 2a. Indicates the voltage value (“non-selected column” or “non-selected row”) when no charge is injected, and “(3) Operation principle for injecting charge into the charge storage layer in the write selected memory cell” described above and “(4) In the write non-selected memory cell in which a high voltage charge storage gate voltage is applied to the memory gate electrode, there is an overlapping explanation with respect to the operation principle that charges are not injected into the charge storage layer”. Description is omitted.

(6) Configuration of Charge Storage Layer in Memory Cell of the Present Invention Here, FIG. 5A in which the same reference numerals are assigned to the corresponding parts to FIG. 2 shows the memory cell 100 which is Comparative Example 1, and the memory gate electrode The memory cell 2a is different from the memory cell 2a of the present invention shown in FIG. 2 in that the charge storage layer EC1 is also formed in the sidewall spacer 102 between the MG and the first selection gate electrode DG. FIG. 5A shows only the charge storage layer EC1 between the memory gate electrode MG and the first selection gate electrode DG, but the memory gate electrode MG and the second selection gate electrode SG (not shown in FIG. 5A). Similarly, charge storage layers are formed in the side wall spacers therebetween.

  In practice, the charge storage layer EC1 shown in the comparative example extends from the end of the charge storage layer EC provided in the region ER1 below the memory gate electrode MG to the region between the memory gate electrode MG and the first selection gate electrode DG. After extending, it is refracted at a right angle and extends along the side wall of the memory gate electrode MG in the side wall spacer 102 between the memory gate electrode MG and the first selection gate electrode DG.

  In the memory cell 100 of Comparative Example 1 having such charge storage layers EC and EC1, due to the quantum tunnel effect caused by the voltage difference between the memory gate electrode MG and the channel layer (not shown) on the surface of the memory well MPW, Charges can be injected from the memory well MPW into the charge storage layer EC. However, as shown in FIG. 5B in which parts corresponding to those in FIG. 5A are denoted by the same reference numerals, in the memory cell 100 of Comparative Example 1, the charges in the charge storage layer EC are changed over time to the memory gate electrode MG and It gradually diffuses into the charge storage layer EC1 between the first selection gate electrodes DG and directly above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG as well as the charge storage layer EC. There is a possibility that the charge is accumulated in the charge accumulation layer EC1.

  As described above, in the memory cell 100 of Comparative Example 1, the charge is stored up to the charge storage layer EC1 immediately above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG. As a result, the resistance in the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG is increased, so that the memory current is reduced in the read operation, and the read performance is difficult to improve. There was a problem that it was difficult to operate.

  On the other hand, in the memory cell 2a of the present invention, as shown in FIG. 6, the charge storage layer EC is provided only in the region ER1 where the memory gate electrode MG faces the memory well MPW. Also, a charge storage layer is not provided in the side wall spacer 28a between the first select gate electrode DG and in the side wall spacer 28b between the memory gate electrode MG and the second select gate electrode SG (not shown in FIG. 6). It is configured.

  Thus, when charge is injected into the charge storage layer EC, the memory cell 2a causes the side wall spacers 28a and 28b to transfer the charge in the charge storage layer EC to the first selection gate electrode DG and the second selection gate electrode SG. Without reaching the vicinity, it is possible to stay in the region ER1 below the memory gate electrode MG and to prevent charge accumulation immediately above the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG. . Thus, in the memory cell 2a, the resistance value in the region ER2 of the memory well MPW between the memory gate electrode MG and the first selection gate electrode DG can be maintained in a low resistance state, and the read performance can be improved and the memory cell 2a can be operated at high speed.

(7) Operation and Effect In the above configuration, in the memory cell 2a, the lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the memory gate are formed on the memory well MPW between the drain region 31 and the source region 34. The memory gate structure 4 is stacked in the order of the electrodes MG, the first selection gate structure 5 is formed on one side wall of the memory gate structure 4 via the side wall spacer 28a, and the memory gate structure 4 The second select gate structure 6 is formed on the other side wall via the side wall spacer 28b.

  The first selection gate structure 5 includes a first selection gate on the memory well MPW between the drain region 31 to which the bit line BL1 is connected and one sidewall spacer 28a provided on the sidewall of the memory gate structure 4. The first selection gate electrode DG is formed through the insulating film 30. On the other hand, the second select gate structure 6 has a second region on the memory well MPW between the source region 34 to which the source line SL is connected and the other side wall spacer 28b provided on the side wall of the memory gate structure 4. The second selection gate electrode SG is formed via the selection gate insulating film 33.

  In addition to this, in the memory cell 2a, when no charge is injected into the charge storage layer EC, the charge storage gate voltage necessary for the charge injection into the charge storage layer EC is applied to the memory gate electrode MG, and the memory gate electrode MG is opposed. Even if the channel layer CH is formed on the surface of the memory well MPW, the electrical connection between the drain region 31 and the channel layer CH is cut off by the first selection gate structure 5 and the source by the second selection gate structure 6 The electrical connection between the region 34 and the channel layer CH is also cut off.

  As a result, in the memory cell 2a, a depletion layer D is formed around the channel layer CH, and the channel potential Vch of the channel layer CH rises based on the charge storage gate voltage, so that the memory cell electrode MG and the channel layer CH are between. The depletion layer D can block the voltage application from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 while reducing the voltage difference and preventing charge injection into the charge storage layer EC. .

  Therefore, in the memory cell 2a, the first selection gate structure 5 and the second selection gate are not constrained by the high voltage charge storage gate voltage necessary for injecting charges into the charge storage layer EC by the quantum tunnel effect. In the structure 6, the bit line BL1 and the source line SL are brought to a voltage value necessary to cut off the electrical connection between the bit line BL1 and the channel layer CH and the electrical connection between the source line SL and the channel layer CH. The voltage value of can be lowered. Thus, in the memory cell 2a, the thickness of the first selection gate insulating film 30 of the first selection gate structure 5 and the second selection gate structure 6 are adjusted in accordance with the voltage reduction in the bit line BL1 and the source line SL. The thickness of the second select gate insulating film 33 can be reduced, and high speed operation can be realized accordingly.

  In the memory cell 2a of the present invention, the voltage applied to the bit line BL1 and the source line SL can be reduced, so that the gate insulating film thickness of the field effect transistor can be reduced even in the peripheral circuit that controls the memory cell 2a. Accordingly, the area of the peripheral circuit can be reduced.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 1 in which the memory cells 2a, 2b, 2c, and 2d are arranged in a matrix includes a bit voltage application circuit 10, a first selection gate voltage application circuit 11, and a memory gate. A voltage application circuit 13, a second selection gate voltage application circuit 14, a source voltage application circuit 15, and a substrate voltage application circuit 17 are provided.For example, when injecting charges into the charge storage layer EC of the memory cell 2a, The bit lines BL1, BL2, the first select gate lines DGL1, DGL2, the source line SL, the second, in all operations such as when the charge is extracted from each charge storage layer EC of the memory cells 2a, 2b, 2c, 2d The voltage value applied to the selection gate line SGL can be kept at 1.5 [V] or less.

  Therefore, the nonvolatile semiconductor memory device 1 of the present invention includes the bit voltage application circuit 10, the first selection gate voltage application circuit 11, the second selection gate voltage application circuit 14, the memory gate voltage application circuit 13, and the source voltage application circuit 15 In addition to the peripheral circuits of the substrate voltage application circuit 17, for example, a CPU (Central Processing Unit), an ASIC (Application-Specific Integrated Circuit), a logic circuit, and an input / output circuit whose maximum operating voltage is set to 1.5 [V] Various other peripheral circuits and the like can be mixedly mounted on one semiconductor substrate together with the memory cells 2a, 2b, 2c, 2d, the bit voltage application circuit 10, and the like.

  In this case, in the nonvolatile semiconductor memory device 1 of the present invention, for example, the film thicknesses of the first selection gate insulating film 30 and the second selection gate insulating film 33 formed in the memory cells 2a, 2b, 2c, 2d The film thickness of the gate insulating film of the field-effect transistor constituting the circuit is selected to be the thinnest or less, and the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 is the bit A film of the gate insulating film of the field effect transistor constituting the bit voltage application circuit 10 connected to the lines BL1 and BL2 and the gate insulating film of the field effect transistor constituting the source voltage application circuit 15 connected to the source line SL It is desirable that the film thickness be the same as the thickness.

  As a result, in the nonvolatile semiconductor memory device 1 of the present invention, the first select gate insulating film 30 and the second select gate insulating film 33 are thinned on the semiconductor substrate on which the peripheral circuit is embedded, so that the high speed operation is achieved. Further, the area of the peripheral circuit arranged around the memory cells 2a, 2b, 2c, 2d can be reduced.

  Here, the memory cell 2a of the present invention shown in FIG. 2 will be described with reference to a memory cell 201 as shown in FIG. The memory cell 201 shown in FIG. 7A is a comparative example 2 in which an impurity diffusion region 207a is formed on the surface of the memory well MPW between the memory gate structure 204 and the first selection gate structure 205, and the memory gate structure This is different from the memory cell 2a shown in FIG. 2 described above in that an impurity diffusion region 207b is also formed on the surface of the memory well MPW between the fourth and second selection gate structures 206.

  In this case, in the memory cell 201 of Comparative Example 2, when no charge is injected into the charge storage layer EC, a charge storage gate voltage of 12 [V] is applied to the memory gate electrode MG, as in the above-described embodiment. Then, a channel layer CH whose potential is increased based on the charge storage gate voltage is formed on the surface of the memory well MPW facing the memory gate electrode MG.

  However, in the memory cell 201 of Comparative Example 2, impurity diffusion regions 207a and 207b having a higher impurity concentration than the memory well MPW in which the channel layer CH is formed are formed on the surface of the memory well MPW on both sides of the memory gate structure 204. Therefore, the channel potential of the channel layer CH is applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 through the impurity diffusion regions 207a and 207b.

  Therefore, in the memory cell 201 of Comparative Example 2, when the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 is reduced, the first selection is performed by the channel potential applied from the impurity diffusion regions 207a and 207b. There is a problem that the gate insulating film 30 and the second selection gate insulating film 33 may be broken down.

  On the other hand, in the memory cell 2a of the present invention, the surface of the memory well MPW between the memory gate structure 4 and the first selection gate structure 5, as shown in FIG. No impurity diffusion region is formed on the surface of the memory well MPW between the gate structure 4 and the second selection gate structure 6, and the impurity diffusion concentration is the same as that of the memory well in which the channel layer CH is formed. Thus, the channel potential Vch of the channel layer CH is relaxed by the depletion layer having the width DW1 formed around the channel layer CH, and the channel layer CH is transferred to the first selection gate insulating film 30 and the first selection gate insulating film 33. Application of the channel potential Vch can be cut off.

  Thus, in the memory cell 2a of the present invention, the application of the channel potential Vch from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be reliably blocked, so that the bit line BL1 and the source line SL Even if the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 is reduced in accordance with the low voltage applied from the first selection gate insulating film 30 and the second selection gate insulating film 33 Insulation breakdown can be prevented.

  Incidentally, at this time, the width DW1 of the depletion layer is formed larger than the thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33, so that the memory cell 201 of the comparative example 2 shown in FIG. Compared to the case, the electric field applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be suppressed to about half or less. In this case, for example, as shown in FIG. 4, since the maximum voltage value of the voltage applied to the bit line BL1 and the source line SL in each operation is suppressed to 1.5 [V] or less, the first selection gate insulation The film 30 and the second select gate insulating film 33 can be formed to a thickness of 9 [nm] or less.

(8) Other Embodiments The present invention is not limited to this embodiment, and various modifications are possible within the scope of the present invention. For example, in a memory well, a channel layer The impurity concentration of the surface region where CH is formed may be 3E18 / cm ³ or less. Here, FIG. 7C, in which the same reference numerals are assigned to the parts corresponding to FIG. 7B, shows the present invention formed by the memory well MPW1 in which the impurity concentration of the surface region where the channel layer CH is formed is 3E18 / cm ³ or less The memory cell 41 is shown.

  Even in this case, similarly to the above-described embodiment, in the memory cell 41, a high-voltage charge storage gate voltage is applied to the memory gate electrode MG, and the channel layer CH is formed on the surface of the memory well MPW1 facing the memory gate electrode MG. Even if formed, the memory gate structure MP4 is formed on the surface of the opposed memory well MPW1 by bringing the memory well MPW1 opposed to the first selection gate structure 5 and the second selection gate structure 6 into a non-conductive state. In addition, a depletion layer (not shown) can be formed around the channel layer CH, and charge injection into the charge storage layer EC can be prevented.

At this time, in the memory cell 41 using the memory well MPW1 having an impurity concentration of 3E18 / cm ³ or less, the width DW2 of the depletion layer formed around the channel layer CH is extended, and the width DW2 of the depletion layer is extended. The electric field applied to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be relaxed, and thus the first selection gate insulating film 30 and the second selection gate insulating film 33 can be made thinner. For example, in the memory cell 41 formed in the memory well MPW1 having an impurity concentration of 3E18 / cm ³ or less, when the depletion layer is formed around the channel layer CH, the first selection gate insulating film 30 and the second selection gate insulating film Since the electric field applied to 33 can be reduced to about 1/4 compared to the memory cell 2a (FIG. 2) using the memory well MPW having an impurity concentration of 1.0E19 / cm ³ , the first selection gate The thickness of the insulating film 30 and the second select gate insulating film 33 can be formed to 3 [nm] or less.

Incidentally, the memory well MPW1 between the first selection gate electrode DG and the second selection gate electrode SG only needs to have an impurity concentration of 3E18 / cm ³ or less in a region from the surface to 50 [nm]. By forming the depletion layer, the electric field applied from the channel layer CH to the first selection gate insulating film 30 and the second selection gate insulating film 33 can be relaxed, and the film thickness of the first selection gate insulating film 30 and the second selection gate insulating film 33 can be reduced. It can be formed below 3 [nm].

  In the above-described embodiment, the P-type memory well MPW is used to form the memory gate structure 4 that forms the N-type transistor structure and the first selection gate structure that forms the N-type MOS transistor structure. 5 and the case where the first selection gate structure 6 that also forms the N-type MOS transistor structure is provided. However, the present invention is not limited to this, and the N-type memory well is used to form the P-type. A memory gate structure for forming the transistor structure, a first selection gate structure for forming the P-type MOS transistor structure, and a second selection gate structure for forming the P-type MOS transistor structure. Good.

  In this case, since the N-type and P-type polarities are opposite to those of the memory cell 2a described in the above embodiment, the memory gate structure, the first selection gate structure, and the second selection gate structure The voltages applied to the bit line and the source line also change accordingly. However, even in this case, as in the above-described embodiment, the voltage applied to the bit line and the source line is not restricted by the charge storage gate voltage applied to the memory gate electrode. In the region of the second selection gate structure, the voltage can be lowered to a voltage value necessary to make the memory well nonconductive. Therefore, even in this case, since the voltage values of these bit lines and source lines can be reduced, the first selection gate insulating film of the first selection gate structure and the second selection gate insulating film of the second selection gate structure The thickness can be reduced, and accordingly, high-speed operation can be realized, and the area of the peripheral circuit can be reduced.

  Furthermore, in the above-described embodiment, a case has been described in which data is written by injecting charges into the charge storage layer EC of the memory cell 2a, and data is erased by extracting charges from the charge storage layer EC. The present invention is not limited to this, and conversely, data is written by extracting charges in the charge storage layer EC of the memory cell 2a, and data is erased by injecting charges into the charge storage layer EC. You may do it.

  Furthermore, the nonvolatile semiconductor memory device 1 of the present invention is not limited to the voltage value shown in FIG. 4 described above, and the memory gate structure 4 injects charges into the charge storage layer EC by the quantum tunnel effect. Alternatively, the memory well MPW is made non-conductive in the regions of the first selection gate structure 5 and the second selection gate structure 6, and the depletion layer is formed around the channel layer CH in the memory well MPW provided with the memory gate structure 4. Other various voltage values may be used as long as D is formed and charge injection into the charge storage layer EC can be prevented. In addition, regarding the voltage value of each part during the data read operation, various other voltages can be used as long as information on whether or not charges are accumulated in the charge accumulation layer EC of the memory cells 2a, 2b, 2c, and 2d can be read. A value may be used.

1 Nonvolatile semiconductor memory device
2a, 2b, 2c, 2d memory cells
4 Memory gate structure
5 First selection gate structure
6 Second selection gate structure
30 First selection gate insulating film
31 Drain region
33 Second selection gate insulating film
34 Source area
CH channel layer
D depletion layer
BL1, BL2 bit line
SL source line
MGL memory gate line
DGL1, DGL2 First selection gate line
SGL Second selection gate line
MPW, MPW1 Memory well
MG memory gate electrode
DG first selection gate electrode
SG Second selection gate electrode
EC charge storage layer

Claims (2)

A plurality of memory cells connected in series in the order of a first selection transistor, a memory transistor, and a second selection transistor, and arranged in a matrix;
A bit line shared by memory cell columns and connected to the drain region of the first select transistor;
A first selection gate line shared by memory cell rows and connected to a first selection gate electrode of the first selection transistor;
A second selection gate line connected to a second selection gate electrode of the second selection transistor;
A source line connected to a source region of the second selection transistor;
A memory gate line shared by a plurality of memory cells arranged in a matrix and connected to a memory gate electrode of the memory transistor;
The one memory gate line includes one memory gate line that is electrically connected to each other and shared by one memory cell row, and another memory gate line that is shared by other memory cell rows. See
In a write non-selected memory cell in which charge is not injected into the charge storage layer of the memory transistor,
A charge storage gate voltage required to inject charges into the charge storage layer by a quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the memory well surface opposed to the memory gate electrode,
A first selection gate voltage of 1.5 [V] or lower is applied to the first selection gate electrode, and an off voltage of 1.5 [V] or lower is applied to the drain region, so that the electric potential of the drain region and the channel layer is increased. Is connected to the second selection gate electrode, and a gate-off voltage of 0 [V] is applied to the source region. A depletion layer is formed so as to surround the channel layer in which electrical connection between the channel layer is cut off and a channel potential is increased based on the charge storage gate voltage, and a voltage difference between the memory gate electrode and the channel layer is reduced. A nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is reduced to prevent charge injection into the charge storage layer . A plurality of memory cells connected in series in the order of a first selection transistor, a memory transistor, and a second selection transistor, and arranged in a matrix;
A bit line shared by memory cell columns and connected to the drain region of the first select transistor;
A first selection gate line shared by memory cell rows and connected to a first selection gate electrode of the first selection transistor;
A second selection gate line connected to a second selection gate electrode of the second selection transistor;
A source line connected to a source region of the second selection transistor;
A memory gate line shared by a plurality of memory cells arranged in a matrix and connected to a memory gate electrode of the memory transistor;
The one memory gate line includes one memory gate line that is electrically connected to each other and shared by one memory cell row, and another memory gate line that is shared by other memory cell rows. ,
In the write selection memory cell in which charge is injected into the charge storage layer of the memory transistor,
A charge storage gate voltage required to inject charges into the charge storage layer by a quantum tunnel effect is applied to the memory gate electrode, and a channel layer is formed on the memory well surface opposed to the memory gate electrode,
A first selection gate voltage of 1.5 [V] or less is applied to the first selection gate electrode, and a charge accumulation bit voltage of 0 [V] is applied to the drain region, so that the drain region and the channel layer are Electrically connected, and a gate-off voltage of 0 [V] is applied to the second selection gate electrode, and a source-off voltage of 0 [V] is applied to the source region, whereby the source region and the source region electrical connection of the channel layer is blocked, the charge storage gate voltage and the charge storage bit voltage to inject nonvolatile semiconductor memory device you wherein the charge on the charge storage layer by voltage difference.

Images