KR101668839B1 - Dual poly non-volatile memory - Google Patents

Abstract

A dual poly nonvolatile memory is disclosed. A select transistor formed on a first P-well; A read transistor formed on the first P-well; A first floating gate poly formed on the first P-well and the second P-well for formation of the read transistor; A second poly formed on the first P-well for forming the select transistor and formed along an outline of the first floating gate poly; And forms a read gate capacitor formed by etching a second poly formed along an outer sidewall of the first floating gate poly to access a cell. According to the dual poly nonvolatile memory poly nonvolatile memory of the present invention described above, since a cell is formed through a separate lead gate capacitor having a relatively low coupling ratio as compared with a conventional control gate formed on the second P-well, So that a lower voltage is applied to the first floating gate poly to maximize the VT change of the cell during a read operation after programming so that the endurance reliability of the cell can be improved.

Description

[0001] DUAL POLY NON-VOLATILE MEMORY [0002]

The present invention relates to a memory, and more specifically to a dual poly nonvolatile memory.

Existing EEPROM (electrically erasable programmable read-only memory) is accompanied by FN tunneling at the time of program or erase.

Around the read transistor between the tunnel oxide film and the silicon interface, an electron trap phenomenon occurs due to the FN tunneling phenomenon.

Such a charge trap causes a problem that the threshold voltage of the erase operation rises as the number of repetitions increases at the time of programming or erasing.

Structurally, conventional EEPROMs implement a program / erase / read operation using a single control gate, but a stumbling block occurs in securing the VT window.

As a result, a failure occurs in the cell and adversely affects the durability of the EEPROM.

An object of the present invention is to provide a dual poly nonvolatile memory.

The dual poly nonvolatile memory according to the present invention includes: a select transistor formed on a first P-well; A read transistor formed on the first P-well; A first floating gate poly formed on the first P-well and the second P-well for formation of the read transistor; A second poly formed on the first P-well for forming the select transistor and formed along an outline of the first floating gate poly; And a read gate capacitor formed by etching a second poly formed along an outer sidewall of the first floating gate poly to access the cell. .

A program gate formed on the first P-well; A control gate formed on the second P-well; And a read gate formed on the second poly on the second P-well.

The lead gate capacitor may include a separate oxide film in addition to the oxide film of the control gate and the read transistor, and the oxide film may be thicker than the oxide film of the control gate and the read transistor.

And the read gate capacitor may be configured to have a coupling ratio that is lower than a coupling ratio of the control gate.

The read gate capacitor may be programmed and the read gate of the read transistor may be configured to operate at a reuse time, using a difference in thickness between the oxide film of the read gate capacitor and the oxide film of the read transistor.

Subsequently, a deep N (not shown) isolating the cell and the P-substrate so as to be able to apply +/- VPP without being affected by the voltage of the P-substrate at the time of program or erase, - < / RTI > wells (deep N-wells).

According to the dual polyvolatile memory polyvolatile memory of the present invention described above, the cell is read using a separate lead capacitor (read gate) having a lower coupling ratio relative to the control gate It is possible to read a cell with a VT window that is larger than that when reading by using the control gate even if the program is programmed with the same voltage. Therefore, the VT reliability margin of the cell can be further secured, thereby contributing to an increase in product life.

1 is a top view of a dual poly nonvolatile memory in accordance with one embodiment of the present invention.
2 is a cross-sectional view of a dual poly nonvolatile memory according to an embodiment of the present invention, taken along the line AA '.
3 is a cross-sectional side view of a dual poly nonvolatile memory according to an embodiment of the present invention on the BB 'side.
4 is a cross-sectional side view of a dual poly nonvolatile memory according to an embodiment of the present invention, taken along the CC 'line.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail to the concrete inventive concept.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, .

On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a dual poly nonvolatile memory according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a dual poly nonvolatile memory according to an embodiment of the present invention, FIG. 4 is a cross-sectional view of a dual poly nonvolatile memory according to an embodiment of the present invention, taken along line CC ''. FIG.

Referring to FIGS. 1 to 4, a dual poly nonvolatile memory 100 according to an exemplary embodiment of the present invention includes a select transistor 110, a read transistor 120, a first floating gate poly a floating gate poly 130, a second poly 140, a read gate capacitor 150, a source 160, a program gate 170, a control gate 170, gate 180, and a bit line 190, as shown in FIG.

The dual poly nonvolatile memory 100 may be configured to access the cell by forming a separate lead gate capacitor 150 having a lower coupling ratio than the conventional control gate. Thus, even if the same charge is injected into the first floating gate poly 130, the cell can be accessed with a further increased VT window by reading the cell using the read gate capacitor 150 The durability of the cell is improved.

 Although the dual poly nonvolatile memory 100 is composed of two poly, the final shape is formed in the form of a single poly.

The dual poly nonvolatile memory 100 can read the cell using a coupling ratio 150 of the lead gate capacitor 150 that is lower than the conventional control gate, Can be increased.

Hereinafter, the detailed configuration will be described.

The select transistor 110 may be formed by the second poly 140 on the first P-well 101.

The read transistor 120 may be formed by a first floating gate poly 140 and a second poly 140 on a first P-well 101. [

The first floating gate poly 130 may be formed on the first P-well 101 and the second P-well 102 for the formation of the read transistor 120. [

The second poly 140 may be formed on the first P-well 101 and formed along the outline of the first floating gate poly 130 for formation of the select transistor 110. [

The read gate capacitor 150 may be formed by etching a second poly 140 formed along an outer sidewall of the first floating gate poly 130 to access the cell.

The source 150 and the program gate 170 may be formed on the first P-well 101.

The control gate 180 may be formed on the second P-well 102.

Meanwhile, the read gate capacitor 150 may be configured to include an oxide film other than the oxide film of the control gate 170 and the read transistor 120. The oxide film may be formed thicker than the oxide film of the control gate 170 and the lead transistor 120.

In addition, the read gate capacitor 150 may be configured to have a coupling ratio that is lower than the coupling ratio of the control gate 170.

Here, the lead gate capacitor 150 operates at a program / erase time by using the difference in thickness between the oxide film of the read gate capacitor 150 and the oxide film of the read transistor 120, The gate 200 may be configured to operate upon a read.

A control gate 180 having a high coupling efficiency is used for programming / erasing, and a low voltage is applied to the first floating gate poly 130 by accessing the cell using the read gate capacitor 150 during a read operation So as to maximize the VT change of the cell upon a read after program.

Subsequently, a dip that isolates the cell and the P-substrate 104 so that +/- VPP can be applied without being affected by the voltage of the P-substrate at the time of program or erase, An N-well 103 may be further included.

Well 103 may be formed between the first P-well 101 and the second P-well 102 and the P-substrate 104.

The fabrication of such a dual poly nonvolatile memory 100 may be accomplished by tunnel oxidation, deposition of a first floating gate poly 130, floating gate photolighography, thick film oxidation, deposition of a second gate poly 140 , A gate poly-photolithography process is applied.

In the last gate polyphotolithography process, side wall poly is formed around the first floating gate poly 130 by dry etching to produce the lead gate capacitor 150. Here, a gate oxide for a 5V element is formed between the sidewall poly gate electrode 150 and the first floating gate poly 130.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. There will be.

101: first P-well
102: second P-well
103: Deep N-Well
104: P-substrate
110: select transistor
120: Lead transistor
130: first floating gate poly
140: second poly
150: Leaded gate capacitor
160: source
170: program gate
180: Control gate
190: bit line
200: Lead gate

Claims (6)

A select transistor formed on a first P-well;
A read transistor formed on the first P-well;
A first floating gate poly formed on the first P-well and the second P-well for formation of the read transistor;
A second poly formed on the first P-well for forming the select transistor and formed along an outline of the first floating gate poly;
And a read gate capacitor formed by etching the second poly formed along an outer sidewall of the first floating gate poly to access a cell,
A program gate formed on the first P-well and a control gate formed on the second P-well,
Wherein the read gate capacitor comprises:
Wherein the control gate and the read transistor have a separate oxide film in addition to the oxide film of the control gate and the read transistor, and the oxide film is thicker than the oxide film of the control gate and the read transistor.
delete delete 2. The semiconductor memory device according to claim 1, wherein the read-
And a coupling ratio lower than the coupling ratio of the control gate. ≪ RTI ID = 0.0 > 16. < / RTI & 5. The method of claim 4,
Wherein the read gate capacitor is configured to operate at a program time and the read gate of the read transistor to operate at a reuse time by using a difference in thickness between the oxide film of the read gate capacitor and the oxide film of the read transistor. Dual poly nonvolatile memory.
6. The method of claim 5,
Subsequently, a deep N-MOS transistor isolating the cell and the P-substrate so as to be able to apply +/- VPP without being affected by the voltage of the P-substrate upon program or erase, Wherein the memory cell is further configured to include a deep N-well.

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