201124992 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種非揮發性記憶體（NonVolatile Mem〇ry)低壓快速抹 除方法’特別是關於-種可於低電壓，藉由逆向偏壓及變換閘極電壓來產 生適莖熱電洞進行低壓快速抹賴作之轉發性記憶體的低壓快速抹除方 法。 【先前技術】 女互補式金屬氧化半導體（Complementary Metal Oxide S_>ndUCt〇r ’ CMOS)製程技術已成為特殊應用積體電路（卿 specificinte㈣edcircuit，纖）之常用製造方法。在電腦資訊產品發達的 今天’奸咖細咖__ (細如丨丨_____ 細I邮Men卿，職0M)由於具備有電性編寫和抹除資料之非揮發 性記憶體雜，且在電源财會敎，所磁廣泛使祕電子產 非揮發性記憶體係為可程式化的，其係用以儲存電荷以改變記憶體之 電晶體_罐’細輪_顺_编軸剛。 ^操侧侧梅，餅所 =憶體™刪之電晶體之閘峨。在㈣揮發性記憶體之 等Γ不a伏特，而且抹___秒㈤ 而且先進_面積"絲本㈣加，更絲相健快速抹除的目的， 而且，先進的製程技術抹除非揮發性 201124992 增加了製造的困難度，也提高了生產成本。 【發明内容】 繁於以上_題，本發_主要目的在於提供-辦揮發性記憶體的 低壓快速抹除方法’藉由升高汲極輕，並魏_，以產生適量熱 電洞來進行抹除，以達舰壓且高速抹除之功效。 本發明之另目的在於提供一種非揮發性記憶體的低壓快速抹除方 法’是使用正負壓來達到超低操作電壓、低操作·、高可靠度之功效， 且使整體非揮發性記憶體之體積可小型化。 因此’為達上述目的，本發明所揭露之非揮發性記憶體的低壓快速抹 除方法，綱於非揮發性記憶體，此非揮發性記憶凝在半導體基底中設 有堆疊閘極結構，堆疊閘極結構包含以_介電層相隔開之浮接閘極與控 制間極堆疊在穿隧介電層表面，穿隧介電層位於半導縣底上或隔離井 中，且有源極及錄位於閘極堆構二側。其中，半導體基底或隔離井 為P型’源極和汲極為N型；或者，半導體基底或隔離井可為n型，源極 和汲極為P型。 此非揮發性記憶體的低壓快速抹除方法，乃包括抹除時變換問極電 磨，並且祕大於雜電壓，以產生適狀快速抹除方^，或利用 負難置’以_超低操作電壓、低操作電流。本發縣可以加快抹除速 度達10〜1GG倍’並降低抹除電壓。凡湘本發明之料使鱗發性記憶體 兀件以不同之結構變化來進行抹除之操作，皆在本發明之範圍中。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明 之目的、技術内容、特點及其所達成之功效。 201124992 【實施方式】 第1圖為本發明之第一實施例所提供之非揮發性記憶體結構的剖視 圖。非揮發性記憶體結構100包括一堆疊閘極結構於一 p型半導體基底13〇 中’堆疊閘極結構包含一浮接閘極112疊設於穿隧介電層m上方、一控制 閘極117藉由一閘間介電層116設置於浮接閘極112上方，以及源極113201124992 VI. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory (NonVolatile Mem〇ry) low-voltage rapid erasing method, particularly related to low voltage, by reverse bias And a low-voltage rapid erasing method for translating the transmissive memory by transforming the gate voltage to generate a suitable stem thermoelectric hole. [Prior Art] The process technology of Complementary Metal Oxide Semiconductor (ndUCt〇r ’ CMOS) has become a common manufacturing method for special application integrated circuits (Qing singer, edcircuit, fiber). In today's computer information products developed, 'small coffee __ (fine as 丨丨 _____ fine I post Men Qing, job 0M) because of the non-volatile memory with electrical writing and erasing data, and Power accounting, the magnetic widely used secret electronic products non-volatile memory system is programmable, it is used to store the charge to change the memory of the transistor _ can's fine wheel _ _ _ axis. ^ The side of the side of the plum, the cake = the memory of the body TM cut the gate of the transistor. In (4) volatile memory, etc. is not a volt, and wipe ___ seconds (five) and advanced _ area " silk (four) plus, more silky fast erase purpose, and, advanced process technology wipes unless volatile Sex 201124992 increases the difficulty of manufacturing and increases production costs. [Summary of the Invention] In the above _ questions, the main purpose of this is to provide a low-voltage rapid erasing method for volatile memory, by raising the bungee light and Wei _ to generate a proper amount of thermoelectric holes for wiping In addition, to achieve the effect of ship pressure and high speed erase. Another object of the present invention is to provide a low-voltage rapid erasing method for non-volatile memory, which uses positive and negative voltages to achieve ultra-low operating voltage, low operation, high reliability, and overall non-volatile memory. The volume can be miniaturized. Therefore, in order to achieve the above object, the low-voltage rapid erasing method of the non-volatile memory disclosed in the present invention is directed to a non-volatile memory, and the non-volatile memory is provided in a semiconductor substrate with a stacked gate structure, stacked. The gate structure comprises a floating gate and a control interlayer separated by a dielectric layer stacked on the surface of the tunneling dielectric layer, and the tunneling dielectric layer is located on the bottom of the semi-conducting county or in the isolation well, and the source is recorded Located on the two sides of the gate stack. Wherein, the semiconductor substrate or the isolation well is a P-type source and the anode is substantially N-type; or, the semiconductor substrate or the isolation well may be an n-type, and the source and the anode are extremely P-type. The low-voltage rapid erasing method of the non-volatile memory includes changing the electric grinder during the erasing, and the secret is greater than the impurity voltage, so as to produce a suitable quick erasing method, or using the negative hard-setting _ ultra-low Operating voltage, low operating current. The county can speed up the erasing speed by 10 to 1 GG times and reduce the erase voltage. It is within the scope of the present invention to practice the wiping of the scalar memory element with different structural changes. The purpose, technical contents, features and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings. [Embodiment] Fig. 1 is a cross-sectional view showing the structure of a non-volatile memory according to a first embodiment of the present invention. The non-volatile memory structure 100 includes a stacked gate structure in a p-type semiconductor substrate 13A. The stacked gate structure includes a floating gate 112 overlying the tunneling dielectric layer m and a control gate 117. The buffer layer 112 is disposed above the floating gate 112 by a gate dielectric layer 116, and the source 113
及汲極114位於P型半導體基底130内。其中，源極113及汲極114係為N 型離子摻雜區。 此非揮發性記憶體結構100為設有四個端點之結構，如第丨圖所示， 該四個端齡別為祕、絲、鋪.以絲底連減構，並於基底13〇、 源極113、;及極114、控制閘極117上分別施加基底電壓v_、源極電壓％、 没極電壓乂(1與控侧極電壓Vc;第2圖為其等效電路。此非揮發性記憶體 結構100之低壓快速抹除過程的條件如下： a. "Vgub 為接地（=〇 ); b. Vd>5V，Vs接近或等於〇 ;及 c· Vd>Vc20 ’ Ve隨抹除時間遞減。 非揮發性s己憶體結構1〇〇從寫入進行到抹除的操作過程中，藉由升高 沒極電塵，在驅動時，由於没極電制發通道能障降低效應（drain_induced barrier lowering effeet ’ DIBL)的影響’且元件在飽和模式，因此沒極電壓 vd大於元件的飽和電壓Vdsat，且（Ve_Vs) >Vths，飽和臨界電壓4會小於 最大的臨界· Vthmax。錄，由於Vd_Vd4位能差之熱電雜量增益， (drain-avalanche-hot hole injection ； DAHH)到浮接_。_，儲存於浮接_的電子減少，故臨界電壓& 201124992 降低’源極-沒極電流會增加。之後，逐漸降低㈣閘極電壓％，減少源極 -汲極電流’而保持抹除速度。或者’當此轉發性記麵結構⑽滿足下 列條件，亦可達到低壓且快速之抹除： a· Vsub為負壓； b. Vs接近或等於vsub ;及 c-Vd>Vc，Vc隨抹除時間遞減。 第3圖為本發明之第二實施綱提供的非揮發性記憶觀構的剖視 圖。本發明之非揮發性記憶體結構2〇〇亦可由一堆叠間極結構於於一 N型 半導體基底230所構成’則源極加及沒極為p型離子摻雜區，而堆 疊閘極結構包含堆疊的一浮接閘極212與一控制閘極217。 對於非揮發性$憶體結構2〇〇進行低壓快速抹除過程時，是對於基底 230、源極213、汲極214、控制閘極217上分別施加基底電壓、源極電 壓Vs、祕賴％無綱極韻ν。；第4圖為其等效電路。其條件如 下： a. 乂⑽與 VS>5V ; b. Vd接近或等於〇 ;及 e-Vc>Vd ’ Vc隨抹除時間遞增。 非揮發性記憶體結構2〇〇從寫入進行到抹除的操作過程中，藉由升高 源極與汲極之電壓差，在驅動時，由於汲極電壓引發通道能障降低效應 (drain-induced barrier l〇weringeffect，DIBL)的影響，且元件在飽和模式， 因此汲極與源極電壓差Vds大於元件的飽和電壓Vdsat，且|Vc Vs|>|v叫，飽 和臨界電壓Ά輯值會小於最大的臨界賴vthmax。然後，自於n 201124992 的位能差之熱電子能量增益，會發生汲極累增崩潰熱電洞注入 (drain-avalanche-hot electron injection ; DAHEI)到浮接閘極。繼而，儲存 於浮接閘極的電洞減少，故臨界電壓Vth上升，源極·没極電流會增加。之 後，逐漸提高控制閘極電壓Ve，減少源極-汲極電流，而保持抹除速度。 第5圖為本發明之第三實施顺提供的非揮發性記憶舰構的剖視 圖。非揮發性記憶體結構300包括堆疊閘極結構於一 N型半導體基底33〇 中，源極313及汲極314為P型離子摻雜區，且源極313及汲極314下方 • t包括一 p型井316’而堆疊閘極結構包含堆疊的-浮接閘極;m與一控制 閘極317。 對於非揮發性記憶體結構300低壓快速抹除過程時，是對於基底33〇、 P型井316、源極313、汲極314、控制閘極317上分別施加基底電壓L、 p型井電壓Vpwell、源極電壓Vs、没極電壓％與控制閘極電壓V。，其條件 如下： a· Vpwell 為接地（=〇 ); _ b· VWV ’ vs接近或等於〇 ;及 e· Vd>V<^〇 ’ Ve隨抹除時間遞減。 . 或者’當此非揮發性記憶體結構3〇〇滿足下列條件，亦可達到低壓且 快速之抹除： a· Vpweii為負壓； b-Vs接近或等於Vpwe|1 ;及 e· Vd>Vc ’ vc隨抹除時間遞減。 第6圖為本發明之第四實施績提供的非揮發性記憶體結構的剖視 201124992 圖非揮發性S己憶體結構4〇〇包括堆疊閘極結構於一 p型半導體基底43〇 中源極413及汲極4_ν型離子摻雜區，且源極413及没極似更包 括一 Ν型井416 ’而堆疊閘極結構包含堆疊的-浮接閘極412與-控制閘 極 417。 對於單_非揮發性記麵結構·低壓快速抹除過辦，是對於基 底430、Ν型井416、源極413、沒極414、控制閘極417上分別施加基底 電壓sub Ν财f屋Vnwei|、源極電壓Vs、汲極電壓％與控侧極電壓 Vc，其條件如下： a· Vnwe"與 Vs > 5 V ; b· Vnwe"^ Vs ; c· Vd接近或等於〇 ;及 d‘V_i^Vc>Vd ’ vc隨抹除時間遞增。 根據本發明所提供之非揮發性記麵的健快速抹除方法，可藉由升 高源極與祕之電壓差，並變賴極龍來產生適量熱電騎行健快速 抹除操作’以制高速抹除之魏4外，可藉由施加正負麵於沒極、 閘極及半導體基底或井區’來產生適量熱電洞，以降低絕對電壓，達成降 低電壓的目的嘯此’本發明可以加快抹除速度達1G〜⑽倍，並降低抹除 電壓。 以上所述係藉由實施例·本發明之特點，其目的在使翻該技術者 能暸解本侧之魄雌財施，树限林㈣之糊翻，故，凡其 他未脫離本發騎麵之鱗所完叙#跡飾雜改，仍餘含在以下 所述之申請專利範圍中。 201124992 【圖式簡單說明】 第1圖為本發明之第一實施例的非揮發性記憶體結構之剖視圖。 第2圖為本發明之第一實施例結構之等效電路。 第3圖為本發明之第二實施例的非揮發性記憶體結構之剖視圖。 . 第4圖為本發明之第二實施例結構之等效電路。 第5圖為本發明之第三實施例的非揮發性記憶體結構之剖視圖。 第6圖為本發明之第四實施例的非揮發性記憶體結構之剖視圖。 【主要元件符號說明】 100 111 112 113 114 116 117 130 200 212 213 214 217 非揮發性記憶體結構 穿隧介電層 浮接閘極 源極 汲極 閘間介電層 控制閘極 P型半導體基底 非揮發性記憶體結構 浮接閘極 源極 汲極 控制閘極 230 N型半導體基底 201124992 300非揮發性記憶體結構 312 浮接閘極 313 源極 314 汲極 316 P型井 317控制閘極 330 N型半導體基底 400非揮發性記憶體結構 412浮接閘極 413 源極 414 汲極 416 N型井 417控制閘極 430 P型半導體基底The drain 114 is located within the P-type semiconductor substrate 130. The source 113 and the drain 114 are N-type ion doped regions. The non-volatile memory structure 100 is a structure having four end points. As shown in the figure, the four end-lengths are secret, silk, and paved. The source voltage v_, the source voltage %, the gate voltage 乂 (1 and the control side voltage Vc are respectively applied to the source 113, the gate 114, and the control gate 117; FIG. 2 is an equivalent circuit thereof. The conditions of the low voltage fast erase process of the volatile memory structure 100 are as follows: a. "Vgub is ground (=〇); b. Vd>5V, Vs is close to or equal to 〇; and c·Vd>Vc20 'V with smear In addition to the time diminishing. Non-volatile s-resonance structure 1 〇〇 from the writing to the erasing operation, by raising the immersed electric dust, when driving, due to the lack of electric power generation channel energy barrier The effect of the drain_induced barrier lowering effeet 'DIBL' and the component is in saturation mode, so the gate voltage vd is greater than the saturation voltage Vdsat of the component, and (Ve_Vs) > Vths, the saturation threshold voltage 4 will be less than the maximum critical value Vthmax. Recorded, due to the Vd_Vd4 potential difference thermoelectric gain, (drain-avalanche-hot hole injec Ting; DAHH) to float _._, the electrons stored in the floating _ are reduced, so the threshold voltage & 201124992 decreases the 'source-no-pole current will increase. After that, gradually decrease (four) gate voltage %, reduce the source - bungee current ' while maintaining the erase speed. Or 'when this transferable note structure (10) satisfies the following conditions, it can also achieve low voltage and fast erase: a · Vsub is negative pressure; b. Vs is close to or equal to vsub; And c-Vd>Vc, Vc decreases with erasing time. Figure 3 is a cross-sectional view of the non-volatile memory structure provided by the second embodiment of the present invention. The non-volatile memory structure 2 of the present invention may also be A stacked inter-pole structure is formed on an N-type semiconductor substrate 230, and the source is added to the non-p-type ion doped region, and the stacked gate structure includes a stacked floating gate 212 and a control gate 217. For the non-volatile $ memory structure 2〇〇, the low voltage fast erase process is applied to the substrate 230, the source 213, the drain 214, and the control gate 217, respectively, to apply a substrate voltage, a source voltage Vs, and a secret % has no outline ν.; Figure 4 is its equivalent circuit. The pieces are as follows: a. 乂(10) and VS>5V; b. Vd is close to or equal to 〇; and e-Vc>Vd 'Vc increases with erasing time. Non-volatile memory structure 2〇〇 from writing to erasing During the operation, by increasing the voltage difference between the source and the drain, during the driving, the drain-induced barrier l〇wering effect (DIBL) is induced due to the drain voltage, and the component is saturated. Mode, so the drain-source voltage difference Vds is greater than the saturation voltage Vdsat of the component, and |Vc Vs|>|v, the saturation threshold voltage value will be less than the maximum critical value of vthmax. Then, from the thermal energy gain of the potential difference of n 201124992, a drain-avalanche-hot electron injection (DAHEI) is generated to the floating gate. Then, the hole stored in the floating gate is reduced, so that the threshold voltage Vth rises and the source/minus current increases. Thereafter, the control gate voltage Ve is gradually increased to reduce the source-drain current while maintaining the erase speed. Figure 5 is a cross-sectional view of a non-volatile memory vessel provided by a third embodiment of the present invention. The non-volatile memory structure 300 includes a stacked gate structure in an N-type semiconductor substrate 33, a source 313 and a drain 314 are P-type ion doped regions, and a source 313 and a drain 314 are included. The p-well 316' and the stacked gate structure includes a stacked-floating gate; m and a control gate 317. For the low-voltage rapid erasing process of the non-volatile memory structure 300, the substrate voltage L and the p-type well voltage Vpwell are respectively applied to the substrate 33〇, the P-type well 316, the source 313, the drain 314, and the control gate 317. , source voltage Vs, gate voltage % and control gate voltage V. The conditions are as follows: a· Vpwell is grounded (=〇); _ b· VWV ' vs is close to or equal to 〇 ; and e· Vd>V<^〇 ’ Ve decreases with erase time. Or 'When this non-volatile memory structure 3〇〇 meets the following conditions, it can also achieve low voltage and fast erase: a· Vpweii is negative pressure; b-Vs is close to or equal to Vpwe|1; and e·Vd> Vc ' vc decreases with erase time. Figure 6 is a cross-sectional view of a non-volatile memory structure provided by the fourth embodiment of the present invention. 201124992. The non-volatile S-resonant structure 4A includes a stacked gate structure in a p-type semiconductor substrate 43. The pole 413 and the drain 4_ν type ion doped region, and the source electrode 413 and the pole electrode further include a germanium type well 416 ' and the stacked gate structure includes a stacked floating gate 412 and a control gate 417. For the single-non-volatile surface structure and the low-voltage rapid erasing, the substrate voltage is applied to the substrate 430, the germanium well 416, the source 413, the gate 414, and the control gate 417, respectively. |, source voltage Vs, drain voltage %, and control side voltage Vc, the conditions are as follows: a· Vnwe" and Vs > 5 V ; b· Vnwe"^ Vs ; c· Vd is close to or equal to 〇; 'V_i^Vc> Vd ' vc is incremented with the erase time. According to the method of the present invention, the non-volatile recording method can quickly generate a high-speed riding and fast erase operation by increasing the voltage difference between the source and the secret. In addition to the Wei 4, the right amount of thermoelectric holes can be generated by applying positive and negative to the gate, gate and semiconductor substrate or well region to reduce the absolute voltage and achieve the purpose of reducing the voltage. The invention can speed up the wipe. In addition to the speed of 1G ~ (10) times, and reduce the erase voltage. The above description is based on the features of the present invention, and the purpose of the present invention is to enable the person skilled in the art to understand the female wealth of the side, and to limit the forest (4), so that the other does not leave the hair riding surface. The complete classification of the scales is still included in the scope of the patent application described below. 201124992 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the structure of a nonvolatile memory of a first embodiment of the present invention. Fig. 2 is an equivalent circuit of the structure of the first embodiment of the present invention. Figure 3 is a cross-sectional view showing the structure of a non-volatile memory of a second embodiment of the present invention. Fig. 4 is an equivalent circuit of the structure of the second embodiment of the present invention. Figure 5 is a cross-sectional view showing the structure of a non-volatile memory of a third embodiment of the present invention. Figure 6 is a cross-sectional view showing the structure of a non-volatile memory of a fourth embodiment of the present invention. [Main component symbol description] 100 111 112 113 114 116 117 130 200 212 213 214 217 Non-volatile memory structure tunneling dielectric layer floating gate source-drain gate dielectric layer control gate P-type semiconductor substrate Non-volatile memory structure floating gate source drain gate control gate 230 N-type semiconductor substrate 201124992 300 non-volatile memory structure 312 floating gate 313 source 314 bungee 316 P-well 317 control gate 330 N-type semiconductor substrate 400 non-volatile memory structure 412 floating gate 413 source 414 drain 416 N-well 417 control gate 430 P-type semiconductor substrate