1288416 18172twf.doc/r 九、發明說明： 【發明所屬之技術領域] 本發明是有關於-種記憶體的抹 關於一種非揮發性記憶體的抹除方法。 4 寸別疋有 【先前技術】 吕己憶體’顧名思義债县用y___ 元件。舍二 存貧料或數據的半導體 式與運算越來越龐大時，記+ 片進仃之私 了制、旦士日#一^ °己u版之尚未也就越來越高，為 了衣造合里大且便朗記憶體以滿足 作記憶體元件之_與製程，已成A主道勢衣 積集度挑獻驅動力。 成科導體科技持續往高 >在各種記憶體產品中，具有可進行多次資料之存入、 讀取或抹除等動作，且存人之:#料麵電後也不會消失之 優點的非揮發性記憶體，已成為個人電腦和電子設備所廣 泛採用的一種記憶體元件。 、當記憶體在進行㈣之抹除時，是將基底、源極/汲極 區或控制’的相對電位提高，並利甩穿隨效應使電子由 電荷陷人層穿過穿隨介電層而排至基底或源極/汲極中。對 於快閃記憶體而言，通常是以通㈣電子（channd hot-electron ’ CHE)注入模式進行程式化，並且利用ρ_Ν穿 隨(Fowler-Nordheim tunneling)模式將電子從電荷陷入層經 由穿隧介電層拉出以進行抹除。 然而，使用F-N穿隧模式抹除快閃記憶體中的資料 日守，由於電子自閘極注入電荷陷入層中，而使電壓的變化 5 1288416 18172twf.doc/r =平缓，且穿隧介電層中的電流密度下降出現抹除飽和 狀您咖此如_丨011)’因此造成抹除時間拉長，影響元 效能。 曰 差鱼知非揮發性記龍之抹除方法中起始電屢 t广m之關係圖。& w為習知非揮發性記憶體之 二二牙：電層中的電流密度與抹除時間之關係 = ，對基底施加不同 ν基底⑴V、 .:門:9ν、8观，可發現於進行抹除操作-1288416 18172twf.doc/r IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method of erasing a non-volatile memory. 4 inch 疋 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 When the semiconductor type and operation of the two materials are more and more huge, the record + film enters the private system, and the day of the day is still higher and higher, for the clothing Heli has a large and easy memory to satisfy the _ and process of memory components, and has become the driving force for the accumulation of A main road. Chengke Conductor Technology continues to move high. In various memory products, it has the functions of depositing, reading or erasing multiple data, and it saves people: #The advantage of not disappearing after the surface is electric Non-volatile memory has become a memory component widely used in personal computers and electronic devices. When the memory is erased (4), the relative potential of the substrate, the source/drain region or the control is increased, and the electrons are passed through the dielectric layer by the charge trapping layer. It is discharged to the substrate or source/drain. For flash memory, it is usually programmed in the channd hot-electron 'CHE injection mode, and the electrons are trapped from the charge trapping layer by tunneling using the Fowler-Nordheim tunneling mode. The electrical layer is pulled out for erasing. However, the FN tunneling mode is used to erase the data in the flash memory, because the electrons are injected into the layer from the gate, and the voltage changes 5 1288416 18172twf.doc/r = gentle, and tunneling dielectric The current density drop in the layer appears to erase the saturation. You can do this as _丨011)', thus causing the erase time to lengthen, which affects the performance of the element.曰 Poor fish knows the relationship between the starting electric and the t-m in the method of wiping the non-volatile recording dragon. & w is the second or second tooth of the conventional non-volatile memory: the relationship between the current density in the electric layer and the erasing time =, applying different ν substrate to the substrate (1)V, .: gate: 9ν, 8 views, can be found in Erase operation -
!：1 ni V2 ^ V V基1為“二狀恕為H底為12V時餘和狀態為S2; ▽為V%飽和狀態為S3;v Ν，V基底為9Vh车今▲ 町把狎狀您為 〜。也_二4==物_和狀態為 電荷陷入層拉出的二=達餘和狀態時，電子從 :遂介電層中的電流密度也增加’且 :二㈣長了抹除操==時:電荷陷入層 本發明的目的就是在提 崎购之抹 除方法，心財種_發性記憶體之抹 本發明提出一種非揮::度。 包括-控制閑極、_電:⑽體之抹除方法，適用於 没極區的非揮發性記憶體;揮-5底、-源極區與一 匕非揮电性記憶體之抹除方法 I2884lll4twf.doc/ 是先於基底施加第一電壓，且於控制閘極施加第二電承 使源極區與汲極區為浮置，其中第—電壓與第二電】怠丄 塵差足以產生F_N㈣效應，使電子從電荷陷人==電 然後，隨抹除時間增加而逐次減小第一電壓。9 。 依照本發明實施例所述之非揮發性記憶體 上述之逐次減小第一電壓的方法例如是先於施加第— 龟壓一段時間後，將第一電壓減小一個固定值。 罘 依照本發明實_所狀轉發性記憶體 法，上述之時間例如為施加第一電壓以 =方 層拉出時所產生的電塵達到-個臨界值的時間。'何Κ 依照本發明實施例所述之非揮發性^體 法，上述之固定值例如為IV。 禾除方 依照本發明實施例所述之非揮發性 法，上述之電壓差例如是介於8V〜脚1_之抹除方 法 法 依照本發明實施觸述之非揮發性記 上述之控制閘極的材質例如為摻雜多晶矽。 示方 依照本發財關料之神發㈣ 上述之電荷陷入層的材質例如為氮化石夕:抹除方 本發㈣m轉發性記憶體之 ;匕括一控制閘極、一電荷陷入層、一基广、’，適用 —汲極區的非揮發性記憶體， =&、—源極區與 ，是先於基底施加第-電愿，且抹除方 电壓’使源極n與汲極區為浮 加第二 堡之錢R以產生F_N穿隨/，、=—麵與第二電 牙W應’使電子從電荷陷入層 7 1288416 18172twf.doc/r 排出。然後，逐次於一個固定時間後，一“ 個固定值。 ：弟一電壓減小一 依照本發明實施例所述之非揮發性記 法，上述之固定時間例如為1〇微秒。 。抹除方 依照本發明實施例所述之非揮發性 法，上述之固定值例如為〇·1ν。 心紅之抹除方 依照本發明實施例所述之非揮發性 法，上述之電壓差例如是介於8ν〜20ν^^"肢之抹除方 依照本發明實施例所述之非揮發性 法，上述之控制閘極的材質例如為之抹除方 依照本發明實施例所述之非揮發性^體 法’上述之電荷陷入層的材質例如為氮化矽-之抹除方 制閘=:===:=減少對控 操作時，起靖差達到飽和狀 二：：===問題，且並 以本發明之抹二:“：上而增加元件效能。此外， 體進行抹除，與利用帶對帶^; 可以得到更佳的可靠Γ除對§己憶體進行抹除比較起來， 易懂其他目的、賴和優點能更明顯 下。下料舉貫關，趣合所關式，作詳細說明如 8 1288416 18172twf.doc/r 【實施方式】 圖2為依照本發明一實施例所繪示的非揮發性記憶體 之剖面示意圖。請參照圖2，在以下實施例中，非揮發性 記憶體20包括基底2〇〇、穿隧介電層2〇2、電荷陷入層 204、電荷阻擒層206、控制閘極208、源極區210與;;及極 區212。控制閘極208設置於基底200上。控制閘極2〇8 的材質例如是摻雜多晶矽。穿隧介電層2〇2、電荷陷入層 204與電荷阻擋層206依序設置於基底2〇〇上，且位於控 制閉極208與基底200之間。穿隧介電層观的材質例如 ，氧化石夕。電荷陷入層綱的材質例如是氮化石夕、摻雜多 曰曰石夕、金屬或其他電荷儲存材質。電荷阻擋層挪的材質 1如=氧!Γ源極區210與汲極區212設置於控制閑極 兩側的基底2〇〇中。 圖3為依照本發明一實施例所綠示 之抹除操作流程示意圓。首先，衫_ 生‘脰 中，於I无明茶恥圖3，在步驟300 使馮二：弟一電壓，且於控制閘極施加第二電壓， 錄區為浮 除時間增加而逐次減小第一電塵。逐二地:;隨抹 法例如是於施加第—電墨一段時間。3 =電麗的方 m ，值(飽和狀態）的時間。然後，爯蔣當一 电£減小一個固定值，此固定值例如為lv。再將弟 以下將以13V〜1〇V的第—電屋為例來對本發明之一 9 ⑽ 8416 】8l72twf.d〇c/r 種非揮發性記之袜除方法做說明。 袜除方 === ，圖心曲線U表 4差舆抹除時間之關係曲線。由曲線Lj可看:°电 f作進行-段時間之後，起始電壓差V2會到達飽和：： 1 °曲線L2表示當第_電壓為12 ，二=、 -段時Η= ί 2可看出，在抹除操作進行 L3 I t —’千星差％會到達餘和狀態心。曲線 μ#Χ；Λ^1 =，_差v2會到達飽和狀 I二為::：，，起始_差與抹除時間之關係曲線： 雷;^蕃v ^ ’在抹除操作進行—段時間之後，起妗 電£差V2會到達飽和狀態&。 ° 在本實施财，首先，對於基底施力 為/于置。當起始電壓差V:接近曲線L1 ^ 時，例如是抹除時間歷經〗毫秒之後，將 ς、」 別減小至12V，而此時對12V的 ；，】： 始電壓差v2尚未達到飽和狀態S2。然二2!:1 ni V2 ^ VV base 1 is "the second is for the bottom of the bottom is 12V when the balance and the state is S2; ▽ is the V% saturation state is S3; v Ν, V base is 9Vh car today ▲ For ~. Also _ 2 4 = = object _ and the state is the charge trapped layer pulled out of the two = reach the state and the state, the electrons from the 遂 dielectric layer also increase the current density 'and: two (four) long erased Operation ==: Charge trapping layer The purpose of the present invention is to erase the method of extracting the product, and the invention of the invention is to provide a non-swing:: degree. : (10) Body wiping method, suitable for non-volatile memory in the non-polar region; wiping -5, - source region and a non-volatile memory erasing method I2884lll4twf.doc/ is prior to the substrate Applying a first voltage, and applying a second electrical support to the control gate, the source region and the drain region are floating, wherein the first voltage and the second electrical noise are sufficient to generate an F_N (four) effect, causing the electron to be trapped from the charge Person ==Electricity, then, the first voltage is successively decreased as the erasing time increases. 9. The non-volatile memory according to the embodiment of the invention sequentially reduces the first voltage The method is, for example, reducing the first voltage by a fixed value after applying the first tortoise pressure for a period of time. 罘 In accordance with the present invention, the time is, for example, applying a first voltage to = The time when the electric dust generated by the square layer is pulled out reaches a critical value. 'Κ Κ According to the non-volatile method according to the embodiment of the present invention, the above fixed value is, for example, IV. In the non-volatile method described in the embodiment, the voltage difference is, for example, 8V to the foot 1_. The method for erasing the non-volatile method according to the present invention is characterized in that the control gate is doped, for example, doped. Polycrystalline germanium. The square according to the fortune of the money (4) The material of the above charge trapping layer is, for example, nitride nitride: erasing the square hair (4) m transmissive memory; including a control gate, a charge trapping layer, a broad base , ', applicable—non-volatile memory in the bungee region, =&,-source region and, is to apply the first-electrical wish before the substrate, and erase the square voltage to make the source n and the drain region Float the second Fort's money R to produce F_N wear / /, The = face and the second tooth W should be 'discharged from the charge trapping layer 7 1288416 18172twf.doc/r. Then, after a fixed time, one "fixed value." The second voltage is reduced by a non-volatile method according to an embodiment of the present invention, and the fixed time is, for example, 1 〇 microsecond. . Wipe In accordance with the non-volatile method of the embodiment of the present invention, the above fixed value is, for example, 〇·1ν. The non-volatile method according to the embodiment of the present invention, wherein the voltage difference is, for example, 8ν~20ν^^" The material of the above-mentioned control gate is, for example, a non-volatile method according to an embodiment of the present invention. The material of the charge trapping layer is, for example, a tantalum nitride-wiping square gate = :===:=When the control operation is reduced, the difference is up to the saturation of the second::=== problem, and the wiper of the invention is used: ": to increase the component performance. In addition, the body is erased, Compared with the use of the belt to the belt ^; can get a better reliable elimination of the § memory, compared to the easier to understand other purposes, and the advantages can be more obvious. 2 is a detailed description of a non-volatile memory according to an embodiment of the invention. Referring to FIG. 2, in the following embodiments, The volatile memory 20 includes a substrate 2, a tunneling dielectric layer 2, and a charge trapping layer 204. The charge blocking layer 206, the control gate 208, the source region 210, and the polar region 212. The control gate 208 is disposed on the substrate 200. The material of the control gate 2〇8 is, for example, doped polysilicon. The dielectric layer 2 〇 2, the charge trapping layer 204 and the charge blocking layer 206 are sequentially disposed on the substrate 2 , and located between the control opening 208 and the substrate 200. The material of the tunneling dielectric layer is, for example, oxidized stone. The material of the charge trapping layer is, for example, a nitride rock, a doped polysilicon, a metal or other charge storage material. The material of the charge blocking layer is 1 such as oxygen; the source region 210 and the drain region 212. It is disposed in the substrate 2〇〇 on both sides of the control idler. Fig. 3 is a schematic diagram showing the flow of the erasing operation procedure of the green display according to an embodiment of the present invention. First, the shirt_生'脰中,在一无明茶耻图3. In step 300, feng 2: a voltage is applied, and a second voltage is applied to the control gate, and the recording area is successively decreased by the increase of the floating time, and the first electric dust is successively decreased. Apply the first electric ink for a period of time. 3 = the time of the square m of the electric, the value (saturated state). Then, Jiang Jiangyi The electric value is reduced by a fixed value, for example, lv. Further, the first electric house of 13V~1〇V will be used as an example to treat 9(10) 8416 】8l72twf.d〇c/r of the present invention. The method of removing the non-volatile socks is explained. The socks are divided into the ===, the curve of the heart curve U is the relationship between the time and the erase time. It can be seen from the curve Lj: ° electric f is performed after the period of time The initial voltage difference V2 will reach saturation:: 1 ° curve L2 means that when the _ voltage is 12, two =, - segment Η = ί 2 can be seen, in the erase operation, L3 I t - '千千差%% Reach the balance and state heart. Curve μ#Χ;Λ^1 =, _ difference v2 will reach saturation I is two:::,, the relationship between the start _ difference and the erase time: Ray; ^ Fan v ^ ' After the erase operation is performed for a period of time, the voltage difference V2 will reach the saturation state & ° In this implementation, first, the force is applied to the substrate. When the starting voltage difference V: is close to the curve L1 ^, for example, after the erasing time has elapsed after s milliseconds, the ς, 别 is reduced to 12V, and at this time to 12V;,]: the initial voltage difference v2 has not reached saturation State S2. Second 2
fM I和狀恶S2日守，例如是抹除時間歷經9 電壓VI讚減一同樣地，對^ 1288416 18172twf.doc/r 來說’此時起始電壓差V2尚 再以11V的第一電壓Vi進 5狀怨s3。接著， 近曲線L3上的飽和狀態s 1乍至起始電壓差V2接 毫秒之後，將第-電壓ν Γ =例如疋抹除時間歷經40 1、； ιην从梦】UV減小至1〇V。接荖，i 以H)V的弟-麵v]進行抹除操作至起 接者， 曲線L4上的飽和狀態S4時， D士土差V2接近 秒之後，將第一電麗v]從疋未除广:歷經毫 定的值.以完成抹除操作。或者到達預 小第一電壓％，例如將第___ 丨月況而要繼績減 4士 a 士 弟電昼Vi減小為8V，繼續i隹耔 „ ’直到起始_差％到達預定的電壓值。因此， ，上以的抹除操作(曲線M1)中，因為起始 飽和狀態而導致抹除時間延長的情況便不會發1。]達 憶體之發明^實，所緣示的非揮發性記 中，於基底施加第圖5 ’在步驟_ π纟、 电土且於L·制閘極施加第二電壓， 居〆二:;及極區為浮置。第一電壓與第二電塵之電壓差 1疋；丨；V〜20卩之間然後，在步驟502中，逐次於 =固定=後，將第_電顧小一個固定值。在本實施 歹’:固1時間例如為10微秒。固定值例如為0.1V。 非播二了知“ 13.5V的第一電壓為例來對本發明之另-種 軍舍’記憶體之抹除方法做說明。fM I and the sinister S2 day guard, for example, the erasing time is 9 voltage VI praised the same, for ^ 1288416 18172twf.doc / r 'At this time the starting voltage difference V2 is still at the first voltage of 11V Vi enters 5 grievances s3. Then, after the saturation state s 1 近 on the near curve L3 to the initial voltage difference V2 is connected to the millisecond, the first voltage ν Γ = for example, the erase time is over 40 1 , and the ιην is reduced from the dream UV to 1 〇V. . Then, i erases the operation from the younger face of H)V to the splicer, and when the saturation state S4 on the curve L4 is close to the second, the first dynasty v] Undivided: After a certain value, complete the erase operation. Or reach the pre-small first voltage%, for example, the ___ 丨 month condition and the succession of 4 士a 士士电昼 Vi is reduced to 8V, continue i隹耔„ ' until the start _ difference % arrives at the scheduled Therefore, in the erasing operation (curve M1), the erasing time is prolonged because the initial saturation state is not generated.] The invention of Dumex is true. In the non-volatile recording, the fifth voltage is applied to the substrate in Fig. 5 'in step _ π 纟, the electric earth and the second voltage is applied to the L · gate, and the second region is floating; the first voltage and the first voltage The voltage difference between the two electric dusts is 1 疋; 丨; V 〜 20 卩 Then, in step 502, after the = fixed = after, the _ _ _ _ a small fixed value. In this implementation 歹 ': solid 1 time For example, it is 10 microseconds, and the fixed value is, for example, 0.1 V. The non-broadcasting method of "the first voltage of 13.5 V is taken as an example to explain the erasing method of the memory of the other type of military of the present invention".
_時參照圖4與圖5，首先，對於基底施加13.5V 11 1288416 18172twf.doc/rReferring to FIG. 4 and FIG. 5, first, 13.5 V 11 1288416 18172 twf.doc/r is applied to the substrate.
的第一電壓Vl，且於控制閘極施加ov的第二電壓，源極 -區與/及極區為浮置。經過10微秒後，將第一電壓V】減少 〇·1 V至13.4V。經過10微秒後，將13·4ν的第一電壓Vl ，少0.1V至13.3V。經過1〇微秒後，將13·3ν的第一電 壓Vi減少0·1 V至13.2V。經過1〇微秒後，將13·2ν的第 一，壓V!減少咖至131v。經過1〇微秒後，將mV 21!二減少〇.1¥至13V。之後，可視情況需要繼 •、’貝/ 〃弟一電塑Vl，直到起始電屢差V2到達預定的電厣 ，以完成抹除操作。因此，在上述的抹除操作(曲線ΜΓ) 起始差V2不會到達鮮狀態而導致抹除時間延 5發明以逐次減少施加於控制閘極之電β 的方式來對記憶體進行抹除操作，避免 電壓差逐漸值到飽和狀_ 時，在錢抹料啊㈣問題。同The first voltage V1, and the second voltage applied by the control gate ov, the source-region and/or the polar region are floating. After 10 microseconds, the first voltage V] is reduced by 〇·1 V to 13.4V. After 10 microseconds, the first voltage V1 of 13·4 ν is reduced by 0.1V to 13.3V. After 1 〇 microsecond, the first voltage Vi of 13·3 ν is reduced by 0·1 V to 13.2 V. After 1 microsecond, the first of 13·2ν, the pressure V! is reduced to 131v. After 1 microsecond, reduce mV 21! by 〇.1¥ to 13V. After that, it is necessary to continue the electric discharge V1 according to the situation, until the initial electric difference V2 reaches the predetermined electric power to complete the erasing operation. Therefore, in the above erase operation (curve ΜΓ), the start difference V2 does not reach the fresh state, resulting in the erasing time delay. The invention erases the memory in such a manner as to gradually reduce the electric β applied to the control gate. To avoid the voltage difference gradually to the saturation _ when the money is smeared (four) problem. with
使得理的前提之下， 產生，效Ι:ΐ;二:，之抹除方法 =抹除’與利用帶對帶熱電二;記二:3記憶體 比較起來，可以得到更佳的可靠度。〜知抹除的方式 本發^ _以㈣ 圍内，當可作些許之更動與潤飾，因= 12 1288416 18172twf.doc/r 專利範圍所界定者為準。 差與抹除時間發性記億體之抹除方法尹起始 圖1Β為習知非揮發性 層中的電流密度與抹除時間係圖袜除方法中穿遂介電Under the premise of rationality, the effect is: ΐ; 2:, the wiping method = erasing ‘with the use of the belt pair with the thermoelectric two; note 2: 3 memory, compared to, can get better reliability. ~ Know the way to erase This hair ^ _ to (4) inside, when you can make some changes and retouch, because = 12 1288416 18172twf.doc / r The scope of patent definition shall prevail. Difference and erasing time 性 记 亿 体 尹 尹 尹 尹 尹 尹 尹 尹 尹 尹 尹 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图
圖2為依照本發明—實施例所 之剖面示意圖。 S不的非揮發性記憶體 圖3為依照本發明一實施例所给— 之抹除方法之流程示意圖。 、胃不的非揮發性記憶體 圖4為依照本發明實施例所泠示 抹除方法中起始電壓差與抹除時的非諱發性記憶體之 圖5為依照本發明另一實施:之關係圖。 體之抹除方法之流程示意圖。彳所鳋示的非揮發性記憶 【主要元件符號說明】 20 :非揮發性記憶體 200 :基底 202 :穿隧介電層 204 ·電何陷入層 2〇6 :電荷阻擋層 208 ·控制閘極 210 ··源極區 212 :汲極區 300〜302、500〜502 :步驟 1288416 18172twf.doc/r L卜 L2、L3、L4、M卜 M2 :曲線 S!、s2、s3、s4、s5、s6:飽和狀態Figure 2 is a schematic cross-sectional view of an embodiment in accordance with the present invention. Non-volatile Memory of S No Figure 3 is a flow chart showing the method of erasing a method according to an embodiment of the present invention. Non-volatile Memory of the Stomach No. FIG. 4 is a diagram showing the initial voltage difference in the erasing method and the non-burst memory in the erasing method according to an embodiment of the present invention. FIG. 5 is another embodiment of the present invention: Diagram of the relationship. Schematic diagram of the process of the body erasing method. Non-volatile memory indicated by 【 [Main component symbol description] 20 : Non-volatile memory 200 : Substrate 202 : Tunneling dielectric layer 204 · Electrical trapping layer 2 〇 6 : Charge blocking layer 208 · Control gate 210 · source region 212: bungee region 300~302, 500~502: step 1288416 18172twf.doc/r L b L2, L3, L4, M Bu M2: curve S!, s2, s3, s4, s5, S6: saturated state
Vj :第一電壓 v2:起始電壓差 V基;£ :施加於基底之電壓Vj: first voltage v2: initial voltage difference V base; £: voltage applied to the substrate
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