CN104779285B - FINFET semiconductor devices and preparation method thereof - Google Patents
FINFET semiconductor devices and preparation method thereof Download PDFInfo
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- CN104779285B CN104779285B CN201410011019.6A CN201410011019A CN104779285B CN 104779285 B CN104779285 B CN 104779285B CN 201410011019 A CN201410011019 A CN 201410011019A CN 104779285 B CN104779285 B CN 104779285B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
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Abstract
The invention mainly relates to FINFET device, more precisely, being related to a kind of FINFET semiconductor devices with stack fin and preparation method thereof, to enhance grid control and current driving ability.Including a substrate, with the stack fin positioned at substrate, the gate structure for being centered around stack fin both sides and top is further included, wherein stack fin includes hourglass-shaped a lower part fin and the trapezoidal or rectangular top fin on the fin of lower part.
Description
Technical field
The invention mainly relates to FINFET semiconductor devices, more precisely, being related to a kind of with stack fin
FINFET semiconductor devices and preparation method thereof, to enhance grid control and current driving ability.
Background technology
As semiconductor devices maintains low cost and has the demand of higher competitiveness performance, transistor unit in device
Density is always in reduction, to mos field effect transistor in the overall dimensions of increase and device
（MOSFET）For, with the diminution of device overall dimensions, some undesirable negative effects are also following, for example work as raceway groove
When narrowing down to certain value（Such as less than 100nm）, the distance between source area and drain region are also corresponding to be shortened, and easily brings short ditch
Channel effect, grid cut down the control ability of raceway groove, the difficulty increase of grid pinch off raceway groove, negative sub-threshold leakage phenomenon
It is also easier to generate.The defects of transistor based on conventional planar is intrinsic, fin-shaped field effect transistor（Fin Field
Effect Transistor, FinFET）Aforementioned problem is overcome by industry is widely used.Typically at the top of fin and two
Side all forms gate structure, to improve grid control ability.
When semiconductor industry thinks 22nm or following technology node hair is drive on boldly, a challenge is how FinFET has
There are smaller size and higher driving current, be especially desirable to provide the FinFET influenced with the factor that is stressed, for example
It is appropriate to use stress material and draw the stress in raceway groove to lure and strengthen the mobility of carrier.But existing FinFET manufactures energy
Power obviously can not meet such technology requirement.By the subsequent detailed description of the present invention and appended claim, with reference to this hair
Bright adjoint schema and prior art, the feature and scheme that the present invention discloses will become apparent.
Invention content
In one embodiment, FinFET semiconductor devices, including：One substrate and the stack fin positioned at substrate
Piece；It is centered around the gate structure of stack fin both sides and top；Wherein described stack fin includes a hourglass-shaped lower part
The top fin of fin and the trapezoidal shape on the fin of lower part.
One of both above-mentioned FinFET semiconductor devices, the upper and lower part fin are Si materials, and another one is
SiGe materials.
Above-mentioned FinFET semiconductor devices, the substrate include a base substrate and the burial on base substrate
Insulating layer, the stack fin are arranged on above buried insulator layer.
Above-mentioned FinFET semiconductor devices, the stack fin positioned at gate structure both sides, both sides and top setting
There is source/drain epitaxial region.
Above-mentioned FinFET semiconductor devices, the source/drain epitaxial region of N-type FinFET are included outside the SiC of elongation strain
The source/drain epitaxial region of Yan Qu, p-type FinFET include the SiGe epitaxial regions of compression strain.
In another embodiment of the invention, FinFET semiconductor devices, including：One substrate and positioned at substrate
Stack fin；It is centered around the gate structure of stack fin both sides and top；Wherein described stack fin includes a hourglass
The top fin of the lower part fin of shape and the square shape on the fin of lower part.
In a kind of preparation method of FinFET semiconductor devices of the present invention, include the following steps：It provides one and includes the
First, the substrate of the second semiconductor layer；It etches the first semiconductor layer and forms top fin；The second semiconductor layer is etched not by top fin
The region that piece covers is to form the hour-glass in shape lower part fin below the fin of top；Formation is centered around comprising top, lower part
The stack fin both sides of fin and the gate structure of top.
Above-mentioned method, it is rectangular on the first semiconductor layer into a hard mask layer and to scheme in the step of forming top fin
The caseization hard mask layer；The region exposed using the first semiconductor layer of hard mask layer dry etching with opening figure is formed
Depth is less than the groove of the first semiconductor layer original thickness in first semiconductor layer；Using hard mask layer along the groove with each
The first semiconductor layer of anisotropy wet etching, so as to form up-narrow and down-wide trapezoidal shape top fin.
In the step of above-mentioned method, formation lower part fin, anisotropy is carried out to the region of the second semiconductor layer exposure
Wet etching, formed top and bottom width be more than middle part width hourglass-shaped lower part fin.
In the step of above-mentioned method, formation lower part fin, first with the second semiconductor layer of hard mask layer dry etching, shape
Into the lower part fin with vertical sidewall pattern；Then anisotropic wet etching is carried out to the side wall of lower part fin exposure,
The width for forming top and bottom is more than the hourglass-shaped lower part fin of middle part width.
In the step of above method, formation top fin, using the first semiconductor layer of hard mask layer dry etching, so as to shape
Into the top fin with vertical sidewall pattern；Then the inner wall of the opening in hard mask layer, top fin side wall and
Side wall layer is sacrificed in covering one on the top surface of hard mask layer；Eatch-back sacrifices side wall layer formation and is covered in opening inner wall and top fin
Sacrifice side wall on side wall；Lower part fin is formed using the region for sacrificing side wall and hard mask layer etching the second semiconductor layer exposure
Piece.
In the step of above-mentioned method, formation lower part fin, anisotropy is carried out to the region of the second semiconductor layer exposure
Wet etching, formed top and bottom width be more than middle part width hourglass-shaped lower part fin.
In the step of above-mentioned method, formation lower part fin, first with hard mask layer and side wall dry etching second is sacrificed
Semiconductor layer forms the lower part fin with vertical sidewall pattern；Then anisotropy is carried out to the side wall of lower part fin exposure
Wet etching, formed top and bottom width be more than middle part width hourglass-shaped lower part fin.
Above-mentioned method is formed after gate structure, is autoregistration mask in the upper surface of top fin using gate structure
Source/drain region is lightly doped in injection；And side wall is then formed on the side wall of gate structure, and in the stack of gate structure both sides
Source electrode/drain electrode doped area is implanted into fin.
Above-mentioned method is formed after gate structure, is selected in the both sides of the stack fin of gate structure both sides and top
The epitaxial growth source/drain epitaxial region of selecting property.Above-mentioned method, the source/drain epitaxial region of N-type FinFET institutes epitaxial growth
SiC epitaxial regions including elongation strain, the source/drain epitaxial region of p-type FinFET institutes epitaxial growth include compression strain
SiGe epitaxial regions.
Description of the drawings
Read it is described further below and with reference to the following drawings after, feature and advantage of the invention will be evident：
Fig. 1 shows the top epitaxial layer set in base substrate and bottom epitaxial layer.
Fig. 2~5 show that etching top epitaxial layer forms the flow chart of the top fin of inverted trapezoidal.
Fig. 6 A~6B are etching bottom epitaxial layers to prepare the schematic diagram of hourglass-shaped lower part fin.
Fig. 7 is the birds-eye view of the stack fin comprising top, lower part fin.
Fig. 8 is the flow chart that gate insulating layer and grid material are prepared on stack fin and buried insulator layer.
Fig. 9 is the flow diagram that patterned grid insulating layer and grid material prepare gate structure.
Figure 10 is to form the schematic diagram of side wall in the both sides of gate structure.
Figure 11 is the schematic diagram of selective epitaxial growth source/drain epitaxial region.
Figure 12 A show the method that etching top epitaxial layer forms the top fin with vertical sidewall.
Figure 12 B~12C are to prepare the method for sacrificing side wall.
Figure 12 D~12F are to carry out etching bottom epitaxial layer formation lower part fin as mask to sacrifice side wall and hard mask layer.
Figure 12 G are the flow diagrams that patterned grid insulating layer and grid material prepare gate structure.
Figure 12 H are the schematic diagrames of selective epitaxial growth source/drain epitaxial region.
Specific embodiment
Fig. 1 illustrates a typical silicon-on-insulator（Silicon-On-Insulator, SOI）Wafer, at one
The top of base substrate 101 is equipped with buried insulator layer 102, such as a buried oxide layer and also in buried insulator layer 102
Top has the one layer of bottom epitaxial layer 103 formed and one layer of top epitaxial layer 104, epitaxial layer 104,103 successively from the bottom to top
Respectively to should be used as first semiconductor layer and second semiconductor layer in buried insulator layer 102.As demonstration, one
In a little optional embodiments, for example, bottom epitaxial layer 103 is Si material epitaxial layers, and top epitaxial layer 104 can be
GeSi materials or bottom epitaxial layer 103 are GeSi material epitaxial layers, and top epitaxial layer 104 can be Si materials etc..In Fig. 2
In, a hard mask layer 105 is prepared in advance, is covered in 104 top of top epitaxial layer, wherein hard mask layer 105 can be individual layer
Structure, such as typical SiN etc. or the lamination layer structure containing multilayer.It must be, it is emphasized that wafer here be not one
Surely it is SOI wafer, in other embodiments, SOI wafer can also be by the pure silicon substrate institute without any buried insulator layer
It substitutes.
As shown in figs. 34, using conventional photoetching process, patterned hard mask layer 105 forms opening figure therein,
Such as the opening 105a etched in hard mask layer 105.Then hard mask layer 105 is recycled to be used as an etch mask, it is right
The region that top epitaxial layer 104 below exposes carries out dry etching, forms groove 104a, notices that this etching terminates in top
Without etching through its whole thickness in epitaxial layer 104, so the depth of groove 104a is less than the original of top epitaxial layer 104
Beginning thickness.It then proceedes to by the use of hard mask layer 105 as etch mask, 104a implements anisotropic wet etch work along groove
Skill, etching top epitaxial layer 104 are exposed to the region in groove 104a, due to the presence of groove 104a and each of subsequent execution to
Anisotropic etch after top epitaxial layer 104 is etched and run through by 104a along groove, can form the top fin of multiple strips
Piece 104' is substantially rendered as up-narrow and down-wide trapezoidal shape structure.Multiple top fin 104' are arranged in parallel to each other, top
The etching groove through 104 thickness of top epitaxial layer between fin 104', which detaches adjacent upper fin 104', to be disconnected, and is paid attention to
The side wall of top fin 104' at this time has a pattern of inclined surface, the vertical section of top fin 104' for it is up-narrow and down-wide be because
Undercutting is formd below hard mask layer 105 for etch step, by the corner part compared with top of top fin 104' both sides respectively
A part of region to being removed.General requirement, when etching top epitaxial layer 104, the material of bottom epitaxial layer 103 can
The etching technics performed to top epitaxial layer 104 is resisted, without being influenced by the etch step.
Fig. 6 A~6B are the schematic diagrames of further etching bottom epitaxial layer 103, at this time hard mask layer 105 and top fin
104' is etched away the region that bottom epitaxial layer 103 exposes together as etch mask, and forms final vertical section and be
Hourglass-shaped lower part fin 103'.In fig. 6, first lower part fin is initially formed via isotropic etching bottom epitaxial layer 103
The vertical sidewall of 103', such as dry etching, then using anisotropic etching, such as using wet etching in lower part fin 103'
Vertical sidewall on etching form groove recessed inwardly, the presence of groove causes the side wall of lower part fin 103' to have phase
The upper side wall 103'a of inclined surface and the lower wall 103'b of inclined surface are rendered as to vertical direction.Set hourglass-shaped lower part fin
The relatively middle part of piece 103' is most narrow, then in the vertical direction, middle part is up and down respectively in a manner of being stepped up width
It is continuous with top and bottom.Upper side wall 103'a, lower wall 103'b are<110>Crystal face or<111>Crystal face, can be according to bottom outside
Prolong the crystal orientation of 103 top surface of layer<100>Depending on crystal face, upper side wall 103'a, lower wall 103'b<100>Crystal face, can be according to bottom outside
Prolong the crystal orientation of 103 top surface of layer<110>Depending on crystal face.In this step, buried insulator layer 102 is not influenced by etching, and
It is formed after the top fin 104' and hourglass-shaped lower part fin 103' of trapezoidal shape, it is also necessary to which hard mask layer 105 is corroded into stripping
From falling.
In other alternative embodiments, using hard mask layer 105 and top fin 104' as mask, dry method is not used to carve
It loses and is directly performed etching using the region that anisotropic wet etching exposes bottom epitaxial layer 103, do not form lower part fin
The vertical sidewall of the transition of piece 103', and the inclined surface on side wall i.e. upper side wall 103'a and lower wall 103'b is directly formed,
Such side wall can be referred to as Σ shape side walls again, i.e., the step of Fig. 6 B is directly performed by the step of Fig. 5.So as to bottom epitaxial layer
103 nationalitys by etching and foring the lower part fin 103' of multiple strips, between adjacent lower fin 103' outside entire bottom
They are detached disconnection, these lower parts fin 103' general parallel orientation arrangement settings to each other by the etching groove for prolonging 103 thickness of layer.
During etching bottom epitaxial layer 103, the material of top epitaxial layer 104 can resist the etching technics performed to bottom epitaxial layer 103,
Without being influenced by the etch step.
The vertical section figure of Fig. 6 B and the birds-eye view of Fig. 7 illustrate the stack fin of a plurality of setting that is arranged parallel to each other well
Piece 150.Stack fin 150 includes lower part fin 103' and the top fin 104' being stacked on right over the fin 103' of lower part,
Respectively to should be used as first fin and second fin, these stack fins 150 are all located at covering by fin 104', 103'
102 top of enterree.Fin ray is typically all mono-material in the FinFET of known technology, and is common in sectional elevation and is
In the structure of rectangle, and the stack fin 150 of Fig. 7 of the present invention is composite bed, and the material of different layers can also be different, this is to examining
The effect that the beneficial stress engineering of worry raceway groove is displayed with respect to known technology is that milli is unsuspecting, and subsequent content will continue to give
To be discussed in detail.
In fig. 8, continue to cover one layer of gate insulating layer 106 at the top of each stack fin 150 and both sides, such as
In an oxidizing environment thermal oxide stack fin 150 and the oxide that generates, the classification of oxide depend on top epitaxial layer 104
With the material of bottom epitaxial layer 103, such as silica or germanium dioxide.Gate insulating layer 106 can also be Direct precipitation
The high dielectric constant insulation object such as silica, silicon nitride etc. or for example HfSiO, it is exhausted that gate insulating layer 106 is also covered in burial simultaneously
Edge layer 102 is not dumped on the region that stacked fin 150 covers.In fig. 8, it also needs to thereafter again on gate insulating layer 106
Side's one layer of gate material layers 107 of deposition, gate material layers 107 are conductive material, it is typical comprising for example polysilicon, one layer or more
Layer metal material or combination thereof etc., it is contemplated that the gap width between adjacent stacks formula fin 150 is with the size of device
Reduction is also to tend to reduce, so gate material layers 107 want the flawless gap being filled between adjacent stacks formula fin 150
In, such as without cavity, just must try to reduce the high-aspect-ratio in gap, lower part fin 103' and upper can be adjusted in the present invention
The height of portion fin 104', we generally set the thickness of bottom epitaxial layer 103 and top epitaxial layer 104 6nm~
Between 20nm.
In fig.9, the gate mask etching grid material layer 107 and gate insulating layer 106 not illustrate, formation surrounds
Gate structure 160 in each 150 both sides of stack fin and top, gate structure 160 are included via 106 figure of gate insulating layer
Case and come gate insulation layer 106' and the grid 107' including being patterned via gate material layers 107, grid 107' fold
It is added in above gate insulation layer 106'.In some embodiments, the length extending direction of the gate structure 160 of strip is orthogonal to often
The length direction of a stack fin 150.The channel region of FinFET is included in every stack fin 150 by gate structure at this time
160 cladding and around live part, with respect to plane MOSFET, three sides of the channel region of FinFET are by gate structure
160 control undoubtedly enhances the ability of driving current.Especially, according to present invention spirit, on the one hand, in lower part fin
The groove being inwardly recessed etched on the side wall of piece 103', being equivalent to can enable the area of the fin both sides side wall increase
Add, on the other hand, in the trapezium structure of top fin 104', although so that the top surface area of top fin 104' slightly subtracts
It is few, but its both sides side wall the area that reduces considerably beyond top surface of increased area.Take this to increase in stack fin 150
Effective channel width of the channel region enveloped by gate structure 160, in the case where not increasing transistor unit size condition, is related to
The channel width-over-length ratio of current control this factor be improved significantly, this be those skilled in the art be happy to see its into.
In some embodiments, can be after grid mechanism 160 be formed, source/drain region is lightly doped in implementation（Lightly
Doped drain, LDD）Process can be from right directly using gate structure 160 without providing additional ion implantation mask
Quasi- mask and the upper surface of top fin 104' injection source/drain region is lightly doped（It does not illustrate）, in order to formed lightly-doped source/
Drain region and the relatively light dopant of doping concentration are implanted to the upper table of the top fin 104' positioned at 160 both sides of grid mechanism
In face, N-channel FinFET is preferably implanted into arsenic ion, and P-channel FinFET is preferably implanted into boron ion.And then in gate structure 160
On the side wall of both sides formed side wall 108, as shown in Figure 10, formed side wall 108 the step of can first deposit side wall coating to cover
Cover on gate structure 160, stack fin 150 and the exposed region of buried insulator layer 102, then be etched back side wall coating so as to
Unwanted region etch is fallen and only retains the side wall 108 on 160 side wall of gate structure.Finally, it is also necessary to positioned at grid
The source doping region of heavy doping is injected in the exposed stack fin 150a of 160 side of pole structure and in gate structure
The drain doping region of heavy doping is injected in the exposed stack fin 150b of 160 opposite sides, their doping concentration compares LDD
Area is much greater.
In the embodiment of Figure 10, also in the epitaxial growth of 160 both sides of gate structure selectivity for example source electrode extension
Area 109a and drain epitaxial area 109b, it is that the arbitrary region of the top of buried insulator layer 102 is all grown to notice that this epitaxial step is not
Epitaxial region, it is only selective on stack fin 150a, 150b of 160 both sides of gate structure to start to grow epitaxial region
109a、109b.Referring to Figure 10~11, the source electrode epitaxial region 109a grown positioned at 160 side of gate structure, which is centered around, to be located at
The both sides and top of the stack fin 150a of 160 homonymy of gate structure, and positioned at the opposite opposite side of gate structure 160
The drain epitaxial area 109b grown is then centered around the both sides of each stack fin 150b positioned at 160 opposite side of gate structure
And top.In but the embodiment that is not restricted optional at some, the source/drain of the FinFET institutes epitaxial growth of N-type channel
Epitaxial region 109a, 109b include the SiC epitaxial regions of tool elongation strain ability, the source of the FinFET institutes epitaxial growth of P-type channel
Pole/drain epitaxial area 109a, 109b includes the SiGe epitaxial regions of tool compression strain, to change the mobility of carrier.
The method flow of Figure 12 A~12H is a kind of embodiment that trapezoidal top fin is replaced with the top fin of rectangle.
In fig. 12, using conventional photoetching process, patterned hard mask layer 105 forms opening figure therein, such as etches hard
Opening 105a in mask layer 105, then recycle hard mask layer 105 be used as an etch mask, to top below outside
Prolong layer 104 to perform etching.Dry etching top epitaxial layer 104, so as to which top epitaxial layer 104 is exposed to the region in opening 105a
It will be etched away, top epitaxial layer 104 forms the top fin 104' of multiple strips, and general parallel orientation arranges to each other for they,
The etching groove through top epitaxial layer 104 between adjacent upper fin 104', which detaches them, to be disconnected, and pays attention to top at this time
Fin 104' has sidewall profile generally vertically.When etching top epitaxial layer 104, the material of bottom epitaxial layer 103 can
The etching technics performed to top epitaxial layer 104 is resisted, without being influenced by the etch step.Then one layer of sacrifice side wall is deposited
Layer 110, as shown in Fig. 1 2B, side wall layer 110 typical such as silica or silicon nitride are sacrificed side wall layer 110 and are covered at this time
On the top surface of hard mask layer 105 and be attached to opening 105a inner wall on, be also attached on the side wall of top fin 104' and
It is covered in bottom epitaxial layer 103 not covered on exposed upper surface by top fin 104', isotropism is etched back to later
Side wall layer 110 is sacrificed, the sacrifice side wall layer that will be covered on the top surface of the hard mask layer 105 and top surface of bottom epitaxial layer 103
110 etchings remove, as indicated in fig. 12 c.Formed sacrifice side wall is only retained after sacrifice side wall layer 110 is etched
110' is attached on the inner wall of opening 105a and on the side wall of top fin 104'.As shown in Figure 12 D~12E, sacrifice is utilized
Side wall 110', top fin 104' and hard mask layer 105 are used as mask, and etching bottom epitaxial layer 103 is not by top fin 104'
Or sacrifice side wall 110' and cover and the region of exposure, form lower part fin 103'.
In one embodiment, fin 103' in lower part can be initially formed via isotropic etching bottom epitaxial layer 103
Its vertical sidewall, such as Figure 12 D, then using anisotropic etching, on the vertical sidewall of lower part fin 103' etching formed to
The groove that inside is recessed, such as Figure 12 E, the presence of groove causes the side wall of lower part fin 103' to have opposed vertical direction and present
For the upper side wall 103'a of the inclined surface and lower wall 103'b of inclined surface.In this step, buried insulator layer 102 is not etched
Influence, and after rectangular-shaped top fin 104' and hourglass-shaped lower part fin 103' is formed, need hard mask
Layer 105 and the 110' strippings of sacrifice side wall remove, as shown in Figure 12 F.In other alternative embodiments, with hard mask layer 105,
Top fin 104' and sacrifice side wall 110' does not use dry etching and directly uses anisotropic wet etching as mask
The region exposed to bottom epitaxial layer 103 performs etching, and does not form the vertical sidewall of the transition of lower part fin 103', but directly
Inclined surface, that is, upper side wall the 103'a and lower wall 103'b, such side wall formed on side wall can be referred to as Σ shape side walls again.From
And 103 nationality of bottom epitaxial layer is by etching and foring the lower part fin 103' of multiple strips, passing through between adjacent lower fin 103'
They are detached disconnection by the etching groove for wearing entire 103 thickness of bottom epitaxial layer, these lower parts fin 103' is substantially flat to each other
Row arrangement setting.In etching bottom epitaxial layer 103, whether the material of top epitaxial layer 104 can be resisted to bottom epitaxial layer
103 etching technics performed become to recede into the background, because it is constantly subjected to hard mask layer 105 and sacrifices the protection of side wall 110'.
The step of method and step of Figure 12 G~12H and Fig. 8~11, is substantially the same, therefore repeat no more substantially.But it is worth note
Meaning, maximum difference is with Fig. 8~11, in the FinFET of Figure 12 G~12H, the vertical section of top fin 104'
No longer it has been up-narrow and down-wide trapezoidal, section is equal rectangular of about one width, and stack fin at this time
150 include the top fin 104' of hourglass-shaped a lower part fin 103' and the square shape on the fin 103' of lower part.
It is easy to learn the step of Figure 12 A~12F, top fin 104' is with sidewall profile generally vertically in subsequent step
It is constantly subjected to sacrifice the protection of side wall 110', can't be corroded out Σ connected in stars on side wall, so top fin 104'
Square structure is maintained.
In some embodiments, alkaline corrosive liquid is used to etching and forms the side wall with reeded Σ shapes, such as
Lower part fin 103' and the respective Σ shapes side walls of top fin 104' are prepared in the present invention, typically can be used as contained tetramethyl hydrogen
Amine-oxides（TMAH）Or NH4OH or NaOH or KOH or ethylene diamine pyrocatechol（Ethylenediamine
Pyrocatechol, EDP）Corrosive liquid etc..
More than, by explanation and attached drawing, give the exemplary embodiments of the specific structure of specific embodiment, foregoing invention
Existing preferred embodiment is proposed, but these contents are not intended as limiting to.For a person skilled in the art, in reading
State it is bright after, various changes and modifications undoubtedly will be evident.Therefore, appended claims, which should be regarded as, covers the present invention
True intention and range whole variations and modifications.In Claims scope the range of any and all equivalence with it is interior
Hold, be all considered as still belonging to the intent and scope of the invention.
Claims (9)
1. a kind of preparation method of FinFET semiconductor devices, which is characterized in that include the following steps：
One substrate for including first, second semiconductor layer is provided；
It etches the first semiconductor layer and forms top fin；
The region that the second semiconductor layer do not cover by top fin is etched to be formed under hour-glass in shape below the fin of top
Portion's fin；
Formation is centered around comprising top, the stack fin both sides of lower part fin and the gate structure of top；
It is rectangular on the first semiconductor layer into a hard mask layer and to pattern the hard mask layer in the step of forming top fin；
The region exposed using the first semiconductor layer of hard mask layer dry etching with opening figure forms the first semiconductor layer
Middle depth is less than the groove of the first semiconductor layer original thickness；
It is up-narrow and down-wide so as to be formed using hard mask layer along the groove with the first semiconductor layer of anisotropic wet etch
Trapezoidal shape top fin.
2. the method as described in claim 1, which is characterized in that sudden and violent to the second semiconductor layer in the step of forming lower part fin
The region of dew carries out anisotropic wet etching, and the width for forming top and bottom is more than the hourglass-shaped lower part of middle part width
Fin.
3. the method as described in claim 1, which is characterized in that in the step of forming lower part fin, done first with hard mask layer
Method etches the second semiconductor layer, forms the lower part fin with vertical sidewall pattern；
Then anisotropic wet etching is carried out to the side wall of lower part fin exposure, the width for forming top and bottom is more than
Between portion's width hourglass-shaped lower part fin.
4. the method as described in claim 1, which is characterized in that formed after gate structure, covered by autoregistration of gate structure
In the upper surface of top fin, source/drain region is lightly doped in injection to film；And
Then side wall is formed on the side wall of gate structure, and source/drain is implanted into the stack fin of gate structure both sides
Pole doped region.
5. the method as described in claim 1, which is characterized in that formed after gate structure, the stacking in gate structure both sides
The both sides of formula fin and the epitaxial growth source/drain epitaxial region of top selectivity.
6. method as claimed in claim 5, which is characterized in that the source/drain epitaxial region packet of N-type FinFET institutes epitaxial growth
The SiC epitaxial regions of elongation strain are included, the source/drain epitaxial region of p-type FinFET institutes epitaxial growth includes the SiGe of compression strain
Epitaxial region.
7. a kind of FinFET semiconductor devices, which is characterized in that prepared by application such as any one of claim 1-6, wrap
It includes：
One substrate and the stack fin positioned at substrate；
It is centered around the gate structure of stack fin both sides and top；
Wherein described stack fin includes the upper of hourglass-shaped a lower part fin and the trapezoidal shape on the fin of lower part
Portion's fin.
8. FinFET semiconductor devices as claimed in claim 7, which is characterized in that it in described upper and lower part fin the two
One is Si materials, and another one is SiGe materials.
9. FinFET semiconductor devices as claimed in claim 7, which is characterized in that the substrate includes a base substrate and position
Buried insulator layer on base substrate, the stack fin are arranged on above buried insulator layer.
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