TWI527229B - Semiconductor devices - Google Patents

Description

Semiconductor component

The present invention relates to a semiconductor device, and more particularly to a metal-oxide-semiconductor (MOS transistor) device having an epitaxial source/drain.

Epitaxial structures are widely used in semiconductor processes. For example, conventional techniques often use a selective epitaxial growth (SEG) technique to form a crystal lattice in a single crystal substrate. Arrange the same epitaxial structure as the substrate, such as silicon germanium (SiGe) epitaxial structure, as a raised source/drain, or embedded source/drain ). The lattice constant of the germanium epitaxial structure is larger than that of the germanium substrate lattice, and the germanium epitaxial structure strains the channel region of the MOS transistor, thereby increasing the carrier mobility of the channel region (carrier) Mobility) and thereby increase the speed of the MOS transistor.

The use of epitaxial structures as source/drain electrodes can effectively improve component performance, but the fabrication of epitaxial structures greatly increases the complexity of semiconductor processes and the difficulty of process control. In addition, different conductivity type components require different types of stress, and even components of the same conductivity type require different types of stresses of different sizes due to different functions performed by them, thereby increasing the design and design of semiconductor components having an epitaxial structure. Difficult to make.

It can be seen that although the existence of the epitaxial structure can effectively improve the component performance, the industry continues to face challenges as the complexity of semiconductor processes and products continues to increase.

Accordingly, it is an object of the present invention to provide a semiconductor device having stresses of the same type but different sizes.

According to the claimed invention, there is provided a semiconductor device comprising a substrate, a first gate structure and a second gate structure respectively disposed on the substrate, and a first source/drain And a first source/drain, respectively disposed in the substrate on both sides of the first gate structure and the second gate structure. The first gate structure and the second gate structure comprise the same conductivity type; but the first source/drain is different from the second source/drain.

According to the semiconductor element provided by the present invention, the transistor elements of the same conductivity type may have different source/drain electrodes, for example, source/drain electrodes having different stress values, and thus the semiconductor element provided by the present invention can satisfy the integrated body. Performance requirements for various types of components on the circuit.

Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are schematic diagrams showing a first preferred embodiment of a semiconductor component provided by the present invention. As shown in FIG. 1, the semiconductor device 100 of the preferred embodiment includes a substrate 102 having a first region 104 and a second region 106 defined thereon. The first region 104 and the second region 106 are respectively component regions for accommodating different functional elements, and the first region 104 and the second region 106 are electrically isolated by a shallow isolation (STI) 108. A first gate structure 110 and a second gate structure 112 are disposed in the first region 104 and the second region 106 on the substrate 102, respectively. The first gate structure 110 and the second gate structure 112 respectively comprise a gate dielectric layer 114, which may comprise a high dielectric constant (high-k) material or germanium oxide. The first gate structure 110 and the second gate structure 112 also respectively include a gate electrode 116 defined by the patterned hard mask 118, which may comprise a metal material or a polysilicon. It should be noted that the first gate structure 110 and the second gate structure 112 comprise the same conductivity type. For example, the first gate structure 110 and the second gate structure 112 in the preferred embodiment are respectively a gate structure of a p-type transistor element. In addition, the light-doped drains (LDDs) 124 are respectively disposed in the bases 102 on both sides of the first gate structure 110; and the bases 102 on both sides of the second gate structure 112 are also respectively disposed. There are LDDs 124, and LDDs 124 contain the same conductivity type. A sidewall 126 is formed on the sidewalls of the first gate structure 110 and the second gate structure 112, respectively. On the substrate 102, a patterned mask layer 128a is formed to cover the second region 106 to expose the first region 104.

Please refer to Figure 2. Next, an etching process is performed using the patterned mask layer 128a, the patterned hard mask 118, and the sidewall spacers 126 as an etch mask, and a sacrificial spacer 128c is further formed on the sidewall spacers 126. A first recess 130 is formed in each of the bases 102 on both sides of the first gate structure 110 in the first region 104. A cleaning step is then performed to remove native oxide or other impurities in the first recess 130.

Please refer to Figure 3. After the cleaning step, a SEG process is performed to form a first epitaxial structure 140 in the first recess 130. The first epitaxial structure 140 includes a first semiconductor material and a second semiconductor material, the first semiconductor material has a first lattice constant, the second semiconductor material has a second lattice constant, and the second crystal The lattice constant is greater than the first lattice constant. In the preferred embodiment, the first semiconductor material may comprise germanium and the second semiconductor material may comprise germanium. That is, the first epitaxial structure 140 includes germanium, but is not limited thereto. In addition, the first epitaxial structure 140 has a first epitaxial concentration C ₁ , that is, the second semiconductor material has a first epitaxial concentration C ₁ , and the first epitaxial concentration C ₁ is greater than 30%, and preferably greater than 45%. By using the lattice constant of germanium to be larger than the lattice constant of the substrate 102, the epitaxial layer is structurally strained as a strained crucible structure, and drives the lattice and band structure of the single crystal germanium in the channel region. The band structure changes, which in turn increases the carrier mobility of the channel region. In addition, the surface of the first epitaxial structure 140 and the surface of the substrate 102 may be non-coplanar as shown in FIG. 3, and the surface of the first epitaxial structure 140 is higher than the surface of the substrate 102.

After the first epitaxial structure 140 is formed, after the first epitaxial structure 140 is formed, even when the first epitaxial structure 140 is formed, an ion implantation process or a synchronous ion doping process may be performed to The desired dopant is doped into the first epitaxial structure 140 such that the first epitaxial structure 140 can serve as the source/drain of the first transistor component 150. In the preferred embodiment, the first epitaxial structure 140 is the p-type first source/drain 120 of the p-type first transistor element 150; in other words, the first having the first epitaxial structure 140. The source/drain 120 is formed in the first recess 130. Since the ion implantation process described above and the optional doping system are known to those skilled in the art, they are not described herein.

In addition, before the cleaning step and before the SEG process, an undoped epitaxial layer 140a is selectively formed in the first recess 130, and the second semiconductor material in the undoped epitaxial layer 140a is formed. The concentration of the first epitaxial concentration C _{1 of the} first epitaxial structure 140 is even zero, that is, the undoped epitaxial layer 140a may be an epitaxial layer or a pure germanium layer having a low germanium concentration. The crystal is used to avoid a problem that the element starting voltage suddenly drops due to excessive difference in the lattice constant of the junction between the first epitaxial structure 140 and the substrate 102. After forming the first epitaxial structure 140, an undoped epitaxial layer 140b may be selectively formed on the surface of the first epitaxial structure 140, and the second semiconductor material is not doped in the epitaxial layer 140b. The concentration is also smaller than the first epitaxial concentration C _{1 of the} first epitaxial structure 140, or even almost zero, that is, the undoped epitaxial layer 140b can also be an epitaxial layer or a pure germanium layer having a low germanium concentration. Epitaxial crystal is used as a reaction site for the subsequent metal telluride process to avoid the problem of agglomeration of metal and tantalum in the metal telluride process.

Please refer to Figure 4. After forming the first epitaxial structure 140, the patterned mask layer 128a and the sacrificial sidewall spacer 128c are removed, and another patterned mask layer 128b is formed in the first region 104, and then the patterned mask layer 128b is utilized. The patterned hard mask 118 and the sidewall spacers 126 are used as an etch mask for another etching process, and a sacrificial sidewall spacer 128d is formed on the sidewalls 126 of the second gate structure 112 in the second region 106. A second recess 132 is formed in each of the bases 102 on both sides of the second gate structure 112.

Please refer to FIG. 5, which is a schematic diagram of a variation of the preferred embodiment. As shown in FIG. 5, in the present variation, the depths of the first groove 130 and the second groove 132 are different. For example, the first groove 130 has a first depth D ₁ , and the second groove 132 has a second depth D ₂ , and the first depth D ₁ is greater than the second depth D ₂ as shown in FIG. 5 . Since the first depth D _{1 is} greater than the second depth D ₂ , the first epitaxial structure 140 formed in the first recess 130 can provide stress to the channel region of the first transistor element 150 more efficiently.

Please refer to FIG. 6. FIG. 6 is a schematic view showing another variation of the preferred embodiment. As shown in FIG. 6, in the present variation, the shapes of the first groove 130 and the second groove 132 are different, and thus the epitaxial structure formed in the first groove 130 and the second groove 132 is also Get different shapes. For example, after a dry etching, a suitable wet etching may be selected to etch a crystal face of different angles in the substrate 102, so that the first groove 130 may be a first oblique sidewall 130a having different inclination directions. The second inclined side wall 130b has a groove formed by the flat bottom portion 130c. Unlike the first recess 130, the second recess 132 has only an approximately vertical sidewall 132a and a flat bottom 132b, such as a wet etch that is only dry etched or a shorter etch time. Therefore, the first epitaxial structure 140 formed in the first recess 130 obtains a diamond shape and has a sharp corner directed to the channel region. The sharp corners of the first epitaxial structure 140 provide the required stress on both sides of the channel region, thereby increasing the carrier mobility of the channel region of the first transistor element 150.

Of course, the second groove 132 can also have the same depth and shape as the first groove 130 as shown in FIGS. 4 and 7. After the second recess 132 is formed, a cleaning step is performed to remove native oxide or other impurities in the second recess 132. Please refer to Figure 7. After the cleaning step, an SEG process is performed to form a second epitaxial structure 142 in the second recess 132. The second epitaxial structure 142 also includes the first semiconductor material and the second semiconductor material described above; that is, the second epitaxial structure 142 also includes germanium, but is not limited thereto. The second semiconductor material within the second epitaxial structure 142 may also be different than the second semiconductor material within the first epitaxial structure 140. In addition, the second epitaxial structure 142 has a second epitaxial concentration C ₂ , that is, the second semiconductor material in the second epitaxial structure 142 has a second epitaxial concentration C ₂ . It is noted that the second epitaxial concentration C ₂ is different from the first epitaxial concentration C ₁ , and the first epitaxial concentration C ₁ is greater than the second epitaxial concentration C ₂ . For example, the second epitaxial concentration C ₂ is less than 30%, and preferably less than 25%. It is noted that since the first epitaxial concentration C ₁ is greater than the epitaxial second concentration C ₂ , the first epitaxial structure 140 provides a stress greater than that provided by the second epitaxial structure 142.

Similarly, before the second epitaxial structure 142 is formed, after the second epitaxial structure 142 is formed, even when the second epitaxial structure 142 is formed, an ion implantation process or a synchronous ion doping process may be performed. The second epitaxial structure 142 can be used as the source/drain of a second transistor element 152 to incorporate the desired dopant into the second epitaxial structure 142. In the preferred embodiment, the second epitaxial structure 142 is a p-type second source/drain 122 of a p-type second transistor element 152; in other words, having a second epitaxial structure 142. The two source/drain electrodes 122 are formed in the second recess 132. Since the ion implantation process described above and the optional doping system are known to those skilled in the art, they are not described herein. After forming the second epitaxial structure 142, the patterned mask layer 128b and the sacrificial sidewall spacer 128d may be removed.

Similarly, an undoped epitaxial layer 142a may be selectively formed in the second recess 132 after the cleaning step and before the SEG process; and after the second epitaxial structure 142 is formed, the selective epitaxial layer 142 may be selectively formed. An undoped epitaxial layer 142b is further formed on the surface of the second epitaxial structure 142. Moreover, the concentration of the second semiconductor material in the undoped epitaxial layers 142a and 142b is smaller than the second epitaxial concentration C _{2 of the} second epitaxial structure 142, or even almost zero, that is, the undoped epitaxial layers 142a and 142b. Both can be a low germanium epitaxial layer or a pure germanium epitaxial layer.

According to the semiconductor device 100 provided by the first preferred embodiment, the first transistor component 150 and the second transistor component 152 are both strained-silicon MOS devices, and the first epitaxial structure 140 is The second epitaxial structure 142 serves as a stress source of the first transistor element 150 and the second transistor element 152, that is, the first source/drain 120 and the second source/drain 122 respectively serve as a strain 矽 structure. And providing stress to the first transistor element 150 and the second transistor element 152, respectively. It is noted that although the first transistor element 150 and the second transistor element 152 have the same conductivity type, the first transistor element 150 and the second transistor element 152 have different functions and different stress requirements. Therefore, the preferred embodiment provides the first recess 130 and the second recess 132 of different depths or different shapes, or the first epitaxial structure 140 and the second epitaxial structure by providing different concentrations or different compositions. 142, the first transistor element 150 and the second transistor element 152 are subjected to different stresses. Briefly, the semiconductor device 100 provided by the preferred embodiment can simultaneously satisfy the stress requirements of different functional components, and at the same time enhance the electrical performance of different functional components.

In addition, the first transistor component 150 and the second transistor component 152 provided by the preferred embodiment may also have different critical dimension (CD) sizes, in addition to the requirements of different stresses due to different functions. Crystal element. For example, the critical dimension of the first transistor element 150 is less than the size of the second transistor element 152. It should be noted that the first transistor element 150 having a smaller critical dimension has a higher stress requirement, and thus all of the first epitaxial structures 140 of the first transistor element 150 have a higher first epitaxial concentration C ₁ . In contrast, the second transistor element 152 having a larger critical dimension has a lower stress requirement, and thus the second epitaxial structure 142 has a second epitaxial concentration C ₂ lower than the first epitaxial concentration C ₁ .

It should be noted that, in another embodiment provided by the present invention, the first recess 130 and the second recess 132 may be simultaneously formed, but the first epitaxial structure 140 having different epitaxial concentrations may be separately formed. The way of the second epitaxial structure 142 is to achieve different stresses for the first transistor element 150 and the second transistor element 152.

Please refer to FIG. 8. FIG. 8 is a schematic view showing a second preferred embodiment of a semiconductor component provided by the present invention. It is to be noted that the same constituent elements of the second preferred embodiment as those of the first preferred embodiment are denoted by the same reference numerals. As shown in FIG. 8, the preferred embodiment first provides a substrate 102 that includes a plurality of STIs 108. According to the preferred embodiment, the first transistor component 150 further includes a first fin structure 160. The extending direction of the first fin structure 160 is perpendicular to the extending direction of the first gate structure 110, and the first gate structure 110 covers a portion of the first fin structure 160, such that the first fin structure 160 is like the eighth As shown, the substrate 102 is disposed on both sides of the first gate structure 110. Similarly, the second transistor component 152 further includes a second fin structure 162, and the second gate structure 112 covers a portion of the second fin structure 162. The second fin structure 162 is also as shown in FIG. The substrate 102 is disposed on both sides of the second gate structure 112. As described above, the preferred embodiment also includes a plurality of sidewalls 126 disposed on sidewalls of the first gate structure 110 and the second gate structure 112, respectively. The first gate structure 110 and the second gate structure 112 also include a patterned hard mask 118 and a gate electrode 116 and a gate dielectric layer 114 defined by the patterned hard mask 118, respectively.

It can be seen that the first transistor component 150 and the second transistor component 152 provided by the preferred embodiment are respectively a multi-gate transistor component. In addition, in FIG. 8, the first transistor component 150 and the second transistor component 152 of the preferred embodiment are a dual-gate transistor component, but the first transistor component 150 is The second transistor element 152 can also be a tri-gate transistor element.

More importantly, in the preferred embodiment, the first source/drain 120 is disposed in the first fin structure 160; and the second source/drain 122 is disposed on the second fin structure 162. Inside. As previously described, the first source/drain 120 has the first epitaxial structure 140 described above; the second source/drain 122 has the second epitaxial structure 142 described above. The first epitaxial structure 140 has a first epitaxial concentration C ₁ ; the second epitaxial structure 142 has a second epitaxial concentration C ₂ , and the first epitaxial concentration C ₁ is greater than the second epitaxial concentration C ₂ . As described above, the first epitaxial concentration C ₁ is greater than 30%, and the second epitaxial concentration C ₂ is less than 30%; furthermore, the first epitaxial concentration C _{1 is} preferably greater than 45%, and the second epitaxial concentration C _{2 is} preferably less than 25%.

According to the preferred embodiment, although the first transistor element 150 and the second transistor element 152 have the same conductivity type, the first transistor element 150 and the second transistor element 152 have different functions and different stress requirements. . Therefore, in the preferred embodiment, the first transistor element 150 and the second transistor element 152 are subjected to different stresses by providing the first epitaxial structure 140 and the second epitaxial structure 142 having different concentrations. For example, when the first transistor element 150 and the second transistor element 152 are both PMOS, the gate channels of the first transistor element 150 and the second transistor element 152 respectively have different compressive stresses; and when the first transistor is When the element 150 and the second transistor element 152 are both NMOS, the gate channels of the first transistor element 150 and the second transistor element 152 respectively have different tensile stresses.

In summary, according to the semiconductor device provided by the present invention, the transistor elements of the same conductivity type may have different source/drain electrodes, such as source/drain electrodes having different shapes, different sizes, and different stress values, thus The semiconductor component provided by the invention can meet the performance requirements of various the same conductivity types but different functional type components on the integrated circuit, and the stress requirements of the same conductivity type but different critical dimension components. Moreover, the semiconductor element provided by the present invention can be successfully integrated into a planar type semiconductor element or a non-planar type semiconductor element, thereby facilitating the miniaturization of the element.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Semiconductor component

102. . . Base

104. . . First area

106. . . Second area

108. . . Shallow trench isolation

110. . . First gate structure

112. . . Second gate structure

114. . . Gate dielectric layer

116. . . Gate electrode

118. . . Patterned hard mask

120. . . First source/dip

122. . . Second source/dip

124. . . Lightly doped bungee

126. . . Side wall

128a, 128b. . . Patterned mask layer

128c, 128d. . . Sacrifice the side wall

130. . . First groove

130a. . . First oblique side wall

130b. . . Second oblique side wall

130c. . . Flat bottom

132. . . Second groove

132a. . . Side wall

132b. . . Flat bottom

140. . . First epitaxial structure

142. . . Second epitaxial structure

140a, 140b. . . Undoped epitaxial layer

142a, 142b. . . Undoped epitaxial layer

150. . . First transistor element

152. . . Second transistor component

160. . . First fin structure

162. . . Second fin structure

D ₁ . . . First depth

D ₂ . . . Second depth

1 to 7 are schematic views showing a first preferred embodiment of a semiconductor device provided by the present invention, wherein FIG. 5 and FIG. 6 are respectively schematic views of a variation of the first preferred embodiment. .

Figure 8 is a schematic view of a second preferred embodiment of a semiconductor component provided by the present invention.

100. . . Semiconductor component

102. . . Base

104. . . First area

106. . . Second area

108. . . Shallow trench isolation

110. . . First gate structure

112. . . Second gate structure

114. . . Gate dielectric layer

116. . . Gate electrode

118. . . Patterned hard mask

120. . . First source/dip

122. . . Second source/dip

124. . . Lightly doped bungee

126. . . Side wall

128b. . . Patterned mask layer

128d. . . Sacrifice the side wall

130. . . First groove

132. . . Second groove

140. . . First epitaxial structure

140a, 140b. . . Undoped epitaxial layer

142. . . Second epitaxial structure

142a, 142b. . . Undoped epitaxial layer

150. . . First transistor element

152. . . Second transistor component

Claims (20)

A semiconductor device includes: a substrate; a first gate structure and a second gate structure respectively disposed on the substrate, and the first gate structure and the second gate structure comprise the same conductivity type a first source/drain and a second source/drain, respectively disposed in the substrate on both sides of the first gate structure and the second gate structure, and the first source/ The drain includes a first epitaxial structure, the second source/and includes a second epitaxial structure, the first epitaxial structure includes a diamond shape, and one of the second epitaxial structures has a shape different from the a diamond shape; and an undoped epitaxial layer disposed on a top surface of the first epitaxial structure and a top surface of the second epitaxial structure, respectively. The semiconductor device of claim 1, wherein the first gate structure and the first source/drain constitute a first metal-oxide-semiconductor (MOS) transistor element, The second gate structure and the second source/drain constitute a second MOS transistor element. The semiconductor component of claim 2, wherein the first MOS transistor component and the second MOS transistor component are both strained-silicon transistor components. The semiconductor device according to claim 3, wherein the first source/drain and the second source/drain are respectively used as one of the first MOS transistor and the second MOS transistor. Strain the structure and provide different stresses. The semiconductor device of claim 4, further comprising a first recess and a second recess disposed in the substrate on both sides of the first gate structure and the second gate structure. The semiconductor device of claim 5, wherein the first source/drain is disposed in the first recess, and the second source/drain is disposed in the second recess. The semiconductor device of claim 6, wherein the first groove and the second groove comprise different shapes. The semiconductor component of claim 6, wherein the first recess and the second recess comprise different depths. The semiconductor device of claim 1, wherein the first epitaxial structure has a first epitaxial concentration and the second epitaxial structure has a second epitaxial concentration. The semiconductor device of claim 9, wherein the first epitaxial concentration is greater than the second epitaxial concentration. The semiconductor device of claim 10, wherein the first epitaxial concentration is greater than 30% and the second epitaxial concentration is less than 30%. The semiconductor device of claim 11, wherein the first epitaxial concentration is greater than 45% and the second epitaxial concentration is less than 25%. The semiconductor device of claim 4, further comprising a first fin structure and a second fin structure. The semiconductor device of claim 13, wherein the first gate structure covers a portion of the first fin structure, and the second gate structure covers a portion of the second fin structure. The semiconductor device of claim 13, wherein the first source/drainage system is disposed in the first fin structure, and the second source/drainage system is disposed on the second fin structure. Inside. The semiconductor device of claim 15, wherein the first epitaxial structure has a first epitaxial concentration and the second epitaxial structure has a second epitaxial concentration. The semiconductor device of claim 16, wherein the first epitaxial concentration is greater than the second epitaxial concentration. The semiconductor device of claim 1, wherein the first epitaxial structure has a first epitaxial concentration, the second epitaxial structure has a second epitaxial concentration, and the first epitaxial concentration is greater than The second epitaxial concentration. The semiconductor device of claim 18, wherein the first epitaxial concentration is greater than 30% and the second epitaxial concentration is less than 30%. The semiconductor device of claim 19, wherein the first epitaxial concentration is greater than 45% and the second epitaxial concentration is less than 25%.