CN104157655A - SONOS flash memory device and compiling method thereof - Google Patents
SONOS flash memory device and compiling method thereof Download PDFInfo
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- CN104157655A CN104157655A CN201410427471.0A CN201410427471A CN104157655A CN 104157655 A CN104157655 A CN 104157655A CN 201410427471 A CN201410427471 A CN 201410427471A CN 104157655 A CN104157655 A CN 104157655A
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Abstract
The invention discloses an SONOS flash memory device which comprises a substrate and a split grid structure located on the substrate. The split grid structure comprises a first oxidation layer, a polycrystalline silicon control grid, a silicon nitride grid and a second oxidation layer, wherein the first oxidation layer makes contact with the semiconductor substrate, the polycrystalline silicon control grid and the silicon nitride grid are located on the first oxidation layer, and the second oxidation layer isolates the polycrystalline silicon control grid from the silicon nitride grid. When the SONOS flash memory device is used for compiling, a first grid voltage higher than or equal to a threshold voltage is applied to the polycrystalline silicon control grid, a second grid voltage higher than the first grid voltage is applied to the silicon nitride grid, and a positive substrate bias voltage is applied to the semiconductor substrate, so that electrons of a channel electron layer induced in the position, below the polycrystalline silicon control grid, of the semiconductor substrate under the action of the first grid voltage are accelerated under the action of the substrate bias voltage and injected into the silicon nitride grid under the action of the second grid voltage. Thus, channel hot electron injection efficiency can be improved, current power consumption is reduced, and the size of the device is reduced.
Description
Technical field
The present invention relates to memory, relate in particular to a kind of SONOS flush memory device and Compilation Method thereof.
Background technology
Along with SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride--oxide-silicon) since structure replaces gradually floating polysilicon grid flash memory structure and becomes the main flash memory storage structure of nonvolatile storage, increasing about the research of compilation speed that how to improve SONOS structure.
One of main code generation that is used for SONOS flush memory device is channel hot electron (CHE) injection effect.Channel hot electron injects and is considered to after long-term circulation, remaining quite reliable, and reason is that it does not apply very large stress on tunnel oxide.But the shortcoming of CHE is that the injection efficiency of compiling is low.This is because near the direction of an electric field of the decanting point place raceway groove of drain terminal and be unfavorable for the collection of electronics.In traditional MOS device, transverse electric field is the decreasing function of grid voltage, and longitudinal electric field rises with the increase of grid voltage.Therefore,, for producing a large amount of hot electrons, need to add a low grid voltage and a high drain voltage to device.But, in order to inject at memory device and to collect electronics, need to add a high grid voltage and a low drain voltage.As the scheme of a compromise, the SONOS flush memory device taking CHEI as code generation must make drain and gate all apply high voltage, but has also caused so the low and current power dissipation of channel hot electron injection efficiency large.
For head it off, a kind of low-power and SONOS flush memory device at a high speed need to be proposed.
Summary of the invention
The object of the invention is to overcome the defect of prior art, provide a kind of and can solve the SONOS flush memory device of wiping saturation problem.
The present invention is achieved by the following technical solutions:
A kind of SONOS flush memory device, comprising: Semiconductor substrate, and it comprises source region and drain region, and splitting grid structure between the above source region of described Semiconductor substrate and drain region, this splitting grid structure comprises the first oxide layer contacting with described Semiconductor substrate, be positioned at polysilicon control grid and nitride gate in described the first oxide layer, and by the second oxide layer of described polysilicon control grid and nitride gate isolation, described the first oxide layer, nitride gate and the second oxide layer form ONO dielectric structure, wherein, in the time of described SONOS flush memory device compiling, by apply the primary grid voltage that is more than or equal to threshold voltage on described polysilicon control grid, on described nitride gate, apply the second grid voltage that is greater than described primary grid voltage, and in described Semiconductor substrate, apply positive substrate bias, the electronics of the channel electrons layer inducing under the effect of described primary grid voltage in the described Semiconductor substrate of described polysilicon control grid below is accelerated under the effect of described substrate bias and under the effect of described second grid voltage, inject described nitride gate.
Preferably, described polysilicon control grid is covered in described nitride gate top at least partly.
Preferably, described second grid voltage is at least the twice of described primary grid voltage.
Preferably, described SONOS flush memory device is n channel device, and described nitride gate approaches described drain region than described polysilicon control grid, in the time of the compiling of this SONOS flush memory device described in source region apply the source voltage of 0V, described drain region applies positive drain voltage.
Preferably, described primary grid voltage is 0.7～1V, and described second grid voltage is 2～3V, and described drain voltage is 2～3V, and described substrate bias is 1～1.5V.
Preferably, the thickness of described the first oxide layer is 2～3.5nm, and the thickness of described nitride gate is 50～90nm, and the thickness of described the second oxide layer is 3～5nm, and the thickness of described polysilicon control grid is 80nm～120nm.
Further, the present invention also provides a kind of Compilation Method of SONOS flush memory device, this SONOS flush memory device comprises the Semiconductor substrate wherein with source region and drain region, and splitting grid structure between the above source region of described Semiconductor substrate and drain region, this splitting grid structure comprises the first oxide layer contacting with described Semiconductor substrate, be positioned at polysilicon control grid and nitride gate in described the first oxide layer, and by the second oxide layer of described polysilicon control grid and nitride gate isolation, described the first oxide layer, nitride gate and the second oxide layer form ONO dielectric structure, this Compilation Method comprises: described polysilicon control grid is applied to the primary grid voltage that is more than or equal to threshold voltage, described nitride gate is applied to the second grid voltage that is greater than described primary grid voltage, and described Semiconductor substrate is applied to positive substrate bias, the electronics of the channel electrons layer inducing under the effect of described primary grid voltage in the described Semiconductor substrate of described polysilicon control grid below is accelerated under the effect of described substrate bias and under the effect of described second grid voltage, inject described nitride gate.
Preferably, described polysilicon control grid is covered in described nitride gate top at least partly.
Preferably, described second grid voltage is at least the twice of described primary grid voltage.
Preferably, described SONOS flush memory device is n channel device, and described nitride gate approaches described drain region than described polysilicon control grid, and described Compilation Method also comprises the source voltage that described source region is applied to 0V, and described drain region is applied to positive drain voltage; Described primary grid voltage is 0.7～1V, and described second grid voltage is 2～3V, and described drain voltage is 2～3V, and described substrate bias is 1～1.5V.
Beneficial effect of the present invention is, utilize the SONOS device of splitting bar structure to apply low-voltage to polysilicon control grid, nitride gate is applied to high voltage, can make like this raising of channel hot electron injection efficiency, and current power dissipation is reduced, can solve traditional defect that SONOS flash memory compiling injection efficiency is low and current power dissipation is large of utilizing CHE mechanism, the present invention is by applying positive bias voltage at substrate on the other hand, can reduce drain voltage, thereby avoid drain region to extend to that the depletion width of substrate is excessive to be caused drain region to contact with depletion region to cause device break-through and inefficacy.Therefore, be conducive to further dwindling of device size.
Brief description of the drawings
Fig. 1 is the structural representation of one embodiment of the invention SONOS flush memory device.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Figure 1 shows that the structural representation of the SONOS flush memory device of one embodiment of the invention, as shown in Figure 1, SONOS flush memory device is n channel device, comprise p-type Semiconductor substrate 10, source region 15a and drain region 15b and the splitting grid structure between source-drain area in Semiconductor substrate of the N-shaped doping in p-type Semiconductor substrate 10.The second oxide layer 13 that splitting grid structure comprises the first oxide layer 11 of contacting with Semiconductor substrate 10, be positioned at polysilicon control grid 14 in the first oxide layer 11 and nitride gate 12 and polysilicon control grid 14 and nitride gate 12 are isolated.Wherein, polysilicon control grid 14 is than the more close source region 15a of nitride gate 12.The first oxide layer 11 as barrier oxide layer, forms ONO dielectric structure as charge storage layer, the second oxide layer 13 as tunneling oxide layer, nitride gate 12 thus.The material of the first oxide layer 11 and the second oxide layer 13 is silicon dioxide.As shown in the figure, in the present embodiment, polysilicon control grid 14 is covered at least partly nitride gate 12 tops and has broken line shape, and polysilicon control grid 14 also can not cover nitride gate 12 in other embodiments.Wherein, the thickness of the first oxide layer 11 is 2～3.5nm, and nitride gate 12 thickness are 50～90nm, and the thickness of the second oxide layer 13 is 3～5nm, and the thickness of polysilicon control grid 14 is 80nm～120nm.As preferred embodiment, the length of the polysilicon gate of splitting grid structure is 10nm, and thickness is that the length of 90nm, nitride gate is 40nm, and highly, for the thickness of 70nm, the first oxide layer is 2.5nm, the thickness of the second oxide layer is 3nm.Splitting grid structure can adopt conventional CMOS technique to complete, and there is no too large change, can produce in general semiconductor manufacturing company.
To the compilation process of SONOS flush memory device of the present invention be illustrated below.In the time that SONOS flush memory device compiles, on polysilicon control grid 14, apply the primary grid voltage Vg that equals greatly threshold voltage
si, on nitride gate 12, apply the second grid voltage Vg that is greater than primary grid voltage
siN, on p-type substrate 10, apply a positive substrate bias Vb, apply the source voltage V of 0V at source region 15a
s, apply positive drain voltage Vd in drain region.Preferably, primary grid voltage Vg
siapproach threshold voltage, if threshold voltage is 0.7V, primary grid voltage is 0.7～1V; Second grid voltage Vg
siNbe at least primary grid voltage Vg
sitwice, be about 2～3V, substrate bias is 1～1.5V.At primary grid voltage Vg
sieffect under induce thin channel electrons layer in the region of substrate below polysilicon control grid 14, at second grid voltage Vg
siNeffect under induce compared with thick-channel electronic shell in substrate region below nitride gate 12.Substrate bias Vb can accelerate polysilicon control grid 14 belows compared with the electronics e of thin channel electronic shell, makes it obtain enough energy and under the effect of second grid voltage, inject nitride gate 12 to complete compiling.Owing to having applied positive substrate bias Vb on substrate, therefore drain voltage Vd can be less, as 2～3V.Thus, can avoid the excessive drain region depletion width that causes of drain voltage excessive and then cause device break-through and inefficacy, can further dwindle SONOS flush memory device size to 50nm or following.
In sum, SONOS flush memory device of the present invention is by arranging splitting grid structure, and on the polysilicon control grid of splitting grid structure and nitride gate, apply less and larger voltage respectively in when compiling, on substrate, apply positive bias voltage, can not only make channel hot electron injection efficiency improve, current power dissipation reduces, overcome traditional defect that SONOS flash memory compiling injection efficiency is low and current power dissipation is large of utilizing CHE mechanism, thereby more utilizing back of the body gate bias assist mechanism to reduce drain voltage avoids drain region to extend to that the depletion width of substrate is excessive to be caused drain region to contact with depletion region to cause device break-through and inefficacy, be conducive to further dwindling of device size.
Although the present invention discloses as above with preferred embodiment; so described many embodiment only give an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. a SONOS flush memory device, is characterized in that, comprising:
Semiconductor substrate, it comprises source region and drain region; And
Splitting grid structure between the above source region of described Semiconductor substrate and drain region, this splitting grid structure comprises the first oxide layer contacting with described Semiconductor substrate, be positioned at polysilicon control grid and nitride gate in described the first oxide layer, and by the second oxide layer of described polysilicon control grid and nitride gate isolation; Described the first oxide layer, nitride gate and the second oxide layer form ONO dielectric structure;
Wherein, in the time of described SONOS flush memory device compiling, by apply the primary grid voltage that is more than or equal to threshold voltage on described polysilicon control grid, on described nitride gate, apply the second grid voltage that is greater than described primary grid voltage, and in described Semiconductor substrate, apply positive substrate bias, the electronics of the channel electrons layer inducing under the effect of described primary grid voltage in the described Semiconductor substrate of described polysilicon control grid below is accelerated under the effect of described substrate bias and under the effect of described second grid voltage, inject described nitride gate.
2. SONOS flush memory device according to claim 1, is characterized in that, described polysilicon control grid is covered in described nitride gate top at least partly.
3. SONOS flush memory device according to claim 1, is characterized in that, described second grid voltage is at least the twice of described primary grid voltage.
4. SONOS flush memory device according to claim 3, it is characterized in that, described SONOS flush memory device is n channel device, described nitride gate approaches described drain region than described polysilicon control grid, described in the time of this SONOS flush memory device compiling, source region applies the source voltage of 0V, and described drain region applies positive drain voltage.
5. SONOS flush memory device according to claim 4, is characterized in that, described primary grid voltage is 0.7～1V, and second grid voltage is 2～3V, and described drain voltage is 2～3V, and described substrate bias is 1～1.5V.
6. SONOS flush memory device according to claim 1 and 2, it is characterized in that, the thickness of described the first oxide layer is 2～3.5nm, and the thickness of described nitride gate is 50～90nm, the thickness of described the second oxide layer is 3～5nm, and the thickness of described polysilicon control grid is 80nm～120nm.
7. the Compilation Method of a SONOS flush memory device, this SONOS flush memory device comprises the Semiconductor substrate wherein with source region and drain region, and splitting grid structure between the above source region of described Semiconductor substrate and drain region, this splitting grid structure comprises the first oxide layer contacting with described Semiconductor substrate, be positioned at polysilicon control grid and nitride gate in described the first oxide layer, and by the second oxide layer of described polysilicon control grid and nitride gate isolation; Described the first oxide layer, nitride gate and the second oxide layer form ONO dielectric structure, it is characterized in that, this Compilation Method comprises:
Described polysilicon control grid is applied and be more than or equal to the primary grid voltage of threshold voltage, described nitride gate is applied and is greater than the second grid voltage of described primary grid voltage and described Semiconductor substrate is applied to positive substrate bias, the electronics of the channel electrons layer inducing under the effect of described primary grid voltage in the described Semiconductor substrate of described polysilicon control grid below is accelerated under the effect of described substrate bias and under the effect of described second grid voltage, inject described nitride gate.
8. Compilation Method according to claim 7, is characterized in that, described polysilicon control grid is covered in described nitride gate top at least partly.
9. Compilation Method according to claim 7, is characterized in that, described second grid voltage is at least the twice of described primary grid voltage.
10. Compilation Method according to claim 9, it is characterized in that, described SONOS flush memory device is n channel device, described nitride gate approaches described drain region than described polysilicon control grid, described Compilation Method also comprises the source voltage that described source region is applied to 0V, and described drain region is applied to positive drain voltage; Described primary grid voltage is 0.7～1V, and described second grid voltage is 2～3V, and described drain voltage is 2～3V, and described substrate bias is 1～1.5V.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934435A (en) * | 2015-04-22 | 2015-09-23 | 上海华力微电子有限公司 | SONOS double-grid flash memory device and programming and erasing methods thereof |
| CN108376682A (en) * | 2018-01-23 | 2018-08-07 | 上海华力微电子有限公司 | Flash memory |
| CN109346528A (en) * | 2018-09-27 | 2019-02-15 | 上海华力微电子有限公司 | Flash memory structure and corresponding programming, erasing and read method |
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| CN100435354C (en) * | 2001-07-27 | 2008-11-19 | 株式会社瑞萨科技 | Semiconductor device |
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| CN100435354C (en) * | 2001-07-27 | 2008-11-19 | 株式会社瑞萨科技 | Semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104934435A (en) * | 2015-04-22 | 2015-09-23 | 上海华力微电子有限公司 | SONOS double-grid flash memory device and programming and erasing methods thereof |
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| CN109346528A (en) * | 2018-09-27 | 2019-02-15 | 上海华力微电子有限公司 | Flash memory structure and corresponding programming, erasing and read method |
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