CN104392965B - A kind of Compilation Method of SONOS flush memory devices - Google Patents
A kind of Compilation Method of SONOS flush memory devices Download PDFInfo
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- CN104392965B CN104392965B CN201410654584.4A CN201410654584A CN104392965B CN 104392965 B CN104392965 B CN 104392965B CN 201410654584 A CN201410654584 A CN 201410654584A CN 104392965 B CN104392965 B CN 104392965B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The present invention provides a kind of Compilation Method of SONOS flush memory devices, when being compiled operation, the magnitude of voltage that first Si-gate applies is equal with the threshold voltage value of flush memory device, the magnitude of voltage that second Si-gate applies is more than the threshold voltage value of flush memory device, it is 4V~6V that drain terminal, which applies voltage range, and source applies 0V voltages.The Compilation Method of SONOS flush memory devices provided by the invention, thermionic motion is assisted by adjusting the voltage of grid and drain terminal, there is provided the enough energy for crossing gate oxide is completed to compile, and improves the compiling efficiency of flash memory, compiling current power dissipation is reduced, improves the reliability of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and its manufacturing field, more particularly to a kind of compiling of SONOS flush memory devices
Method.
Background technology
With the miniaturization of semiconductor storage unit, miniaturization, the storage of the Si-gate of conventional multi-crystalline silicon second is because laminated thickness
It is excessive, demand for development that is too high and being difficult in adapt to future memory is required to tunnel oxide insulating properties.Recently, based on insulating properties
SONOS (Polysilicon-Oxide-Nitride-Oxide-Silicon, the silicon-oxide-nitride of silicon nitride that can be excellent
Thing-oxide-silicon) nonvolatile semiconductor memory member, deposited with it relative to the stronger electric charge of conventional multi-crystalline silicon the second Si-gate memory
Energy storage power, it is easy to accomplish the characteristics such as miniaturization and technique are simple and be taken seriously again.
SONOS, be the English acronym of silicon-oxide-nitride-oxide-silicon, be a kind of and flash memory contact compared with
For close nonvolatile memory.The flash memory main distinction of it and main flow is that it has used silicon nitride (Si3N4), without
It is polysilicon, to serve as storage material.Its branch is SHINOS (silicon-high dielectric-Nitride Oxide-silicon).
SONOS allows the compiling voltage lower than polysilicon flash memory and Geng Gao compiling-erasing cycle-index, is more active at present
Research, exploitation focus.
However, there are the following problems for existing flash memory device structure：In order to ensure high channel hot electron generation rate, it is necessary to
In the voltage that drain terminal is increased, meanwhile, in order to ensure high thermoelectron injection efficiency, it is necessary in grid high voltage.Transverse electric field
Reduced with the rise of grid voltage, likewise, longitudinal electric field increases with increasing for grid voltage.Therefore drain terminal and grid must be made
Pole all high voltages, this results in the low and current power dissipation of channel hot electron injection efficiency it is big the problem of.
The content of the invention
It is an object of the invention to provide a kind of Compilation Method of SONOS flush memory devices, thermionic injection efficiency is improved,
The power consumption of electric current is reduced simultaneously, so as to improve the reliability of flush memory device.
To solve the above problems, the present invention provides a kind of Compilation Method of SONOS flush memory devices, flush memory device includes：Half
Conductor substrate, thereon with spaced source and drain terminal, is provided with above gap between the source and drain terminal
One Si-gate and the second Si-gate, the silicon nitride layer for being used for storing electric charge is provided between second Si-gate and the substrate；It is described
The Compilation Method of SONOS flush memory devices includes：
When being compiled operation, the threshold voltage value phase of magnitude of voltage and the flush memory device that first Si-gate applies
Deng the magnitude of voltage that second Si-gate applies is more than the threshold voltage value of the flush memory device, and the drain terminal applies voltage range
For 4V~6V, the source applies 0V voltages.
Preferably, when being compiled to SONOS flush memory devices, magnitude of voltage and the flash memories that first Si-gate applies
The threshold voltage value of part is equal, and the voltage that second Si-gate applies is 8V, and it is 5V that the drain terminal, which applies voltage, and the source is applied
Add 0V voltages.
Preferably, when being compiled to SONOS flush memory devices, magnitude of voltage and the flash memories that first Si-gate applies
The threshold voltage value of part is equal, and the voltage that second Si-gate applies is twice of the threshold voltage value of the flush memory device, institute
It is 4V to state drain terminal to apply voltage, and the source applies 0V voltages.
Preferably, the lower section of the silicon nitride layer is provided with gate oxide.
Preferably, the material of the gate oxide is silica, and thickness is 2nm~3nm.
Preferably, the gap between first Si-gate and the silicon nitride layer is filled with oxide layer.
Preferably, the material of the oxide layer is silica, and length is 2nm~4nm.
Preferably, the material of first Si-gate is polysilicon, and its height is 40~60nm, and length is 5~15nm.
Preferably, the material of second Si-gate is polysilicon, and its height is 60~80nm, and length is 30~50nm.
It can be seen from the above technical proposal that in the Compilation Method of SONOS flush memory devices provided by the invention, pass through adjustment
The voltage of grid and drain terminal assists thermionic motion, there is provided and the enough energy for crossing gate oxide is completed to compile,
The compiling efficiency of flash memory is improved, reduces compiling current power dissipation, improves the reliability of device.
Brief description of the drawings
Fig. 1 is the principle schematic of the Compilation Method of SONOS flush memory devices of the present invention.
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.Secondly, the present invention has carried out detailed statement using schematic diagram, real the present invention is described in detail
During example, for convenience of description, schematic diagram, should not be in this, as limitation of the invention not according to general proportion partial enlargement.
Above and other technical characteristic and beneficial effect, by conjunction with the embodiments and accompanying drawing 1 to the present invention SONOS flash memories
The Compilation Method of part is described in detail.Fig. 1 is the principle schematic of the Compilation Method of SONOS flush memory devices of the present invention.
Referring to Fig. 1, in the present embodiment, the present invention provides a kind of Compilation Method of SONOS flush memory devices, flush memory device
Including：Semiconductor substrate 10, thereon with spaced source 20 and drain terminal 30, the gap between source 20 and drain terminal 30
Top is provided with the first Si-gate 40 and the second Si-gate 50, and the nitridation for being used for storing electric charge is provided between the second Si-gate 50 and substrate 10
Silicon layer 60；When being compiled operation, the magnitude of voltage that the first Si-gate 40 applies is equal with the threshold voltage value of flush memory device, and second
The magnitude of voltage that Si-gate 50 applies is more than the threshold voltage value of flush memory device, and it is 4V~6V that drain terminal 30, which applies voltage range, source 20
Apply 0V voltages.
Specifically, the lower section of silicon nitride layer 60 is provided with gate oxide, the material of gate oxide is silica, and thickness is
2nm~3nm.In addition, the gap between the first Si-gate 40 and silicon nitride layer 60 is filled with oxide layer, the material of oxide layer is dioxy
SiClx, length are 2nm~4nm.The material of first Si-gate 40 is preferably polysilicon, and its height is 40~60nm, and length is 5~
15nm；The material of second Si-gate 50 is preferably polysilicon, and its height is 60~80nm, and length is 30~50nm.
Embodiment one
The material of first Si-gate 40 is polysilicon, and its height is 50nm, length 10nm；The material of second Si-gate 50 is more
Crystal silicon, its height are 70nm, length 40nm；The height of silicon nitride layer 60 is 50nm, length 40nm；The material of gate oxide
For silica, its thickness is 2.5nm.
When being compiled to SONOS flush memory devices, magnitude of voltage and the threshold voltage of flush memory device that the first Si-gate 40 applies
It is worth equal, the voltage that the second Si-gate 50 applies be 8V, and it is 5V that drain terminal 30, which applies voltage, the application 0V voltages of source 20.
Embodiment two
The material of first Si-gate 40 is polysilicon, and its height is 40nm, length 10nm；The material of second Si-gate 50 is more
Crystal silicon, its height are 60nm, length 40nm；The height of silicon nitride layer 60 is 40nm, length 40nm；The material of gate oxide
For silica, its thickness is 2nm.
When being compiled to SONOS flush memory devices, magnitude of voltage and the threshold voltage of flush memory device that the first Si-gate 40 applies
It is worth equal, the voltage that the second Si-gate 50 applies is twice of threshold voltage value of flush memory device, and it is 4V that drain terminal 30, which applies voltage, source
End 20 applies 0V voltages.
The Fundamentals of Compiling of the present invention：The magnitude of voltage that first Si-gate 40 applies is equal with the threshold voltage value of flush memory device,
Its lower substrate area induces relatively thin channel electrons layer；Threshold value electricity of the magnitude of voltage that second Si-gate 50 applies much larger than flush memory device
Pressure value, the high voltage are coupled to silicon nitride layer 60 and induced in its lower channel compared with thick-channel electronic shell.Drain terminal 30 applies voltage
Accelerate the electronics of relatively thin channel electrons layer, produce the thermoelectron with enough energy and in the presence of the high voltage of the second Si-gate 50
Inject silicon nitride layer 60 and complete compiling.
In summary, in the Compilation Method of SONOS flush memory devices provided by the invention, by adjusting grid and drain terminal
Voltage assists thermionic motion, there is provided the enough energy for crossing gate oxide is completed to compile, and improves the compiling of flash memory
Efficiency, compiling current power dissipation is reduced, improve the reliability of device.
Only the preferred embodiments of the present invention above, embodiment are simultaneously not used to the scope of patent protection of the limitation present invention,
Therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made, similarly should be included in the present invention's
In protection domain.
Claims (9)
1. a kind of Compilation Method of SONOS flush memory devices, the flash memory include：Semiconductor substrate, thereon with spaced
Source and drain terminal, the first Si-gate and the second Si-gate, second silicon are provided with above gap between the source and drain terminal
The silicon nitride layer for being used for storing electric charge is provided between grid and the substrate；Characterized in that, the height of first Si-gate is less than
The height of second Si-gate and the silicon nitride layer；
The Compilation Method of the SONOS flush memory devices includes：
When being compiled operation, the magnitude of voltage that first Si-gate applies is equal with the threshold voltage value of the flush memory device,
One layer of channel electrons are induced with the substrate area under first Si-gate；The magnitude of voltage that second Si-gate applies is more than institute
The threshold voltage value of flush memory device is stated, the voltage that second Si-gate applies is coupled to the silicon nitride layer and in its lower channel sense
It should go out compared with thick-channel electronic shell；It is 4V~6V that the drain terminal, which applies voltage range, and the source applies 0V voltages, is had to produce
The thermoelectron of enough energy simultaneously injects the silicon nitride layer completion compiling in the presence of the voltage that second Si-gate applies.
2. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that carried out to SONOS flush memory devices
During compiling, the magnitude of voltage that first Si-gate applies is equal with the threshold voltage value of the flush memory device, and second Si-gate is applied
The voltage added is 8V, and it is 5V that the drain terminal, which applies voltage, and the source applies 0V voltages.
3. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that carried out to SONOS flush memory devices
During compiling, the magnitude of voltage that first Si-gate applies is equal with the threshold voltage value of the flush memory device, and second Si-gate is applied
The voltage added is twice of the threshold voltage value of the flush memory device, and it is 4V that the drain terminal, which applies voltage, and the source applies 0V
Voltage.
4. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that the lower section of the silicon nitride layer
Provided with gate oxide.
5. the Compilation Method of SONOS flush memory devices as claimed in claim 4, it is characterised in that the material of the gate oxide
For silica, thickness is 2nm~3nm.
6. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that first Si-gate with it is described
Gap between silicon nitride layer is filled with oxide layer.
7. the Compilation Method of SONOS flush memory devices as claimed in claim 6, it is characterised in that the material of the oxide layer is
Silica, length are 2nm~4nm.
8. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that the material of first Si-gate
For polysilicon, its height is 40~60nm, and length is 5~15nm.
9. the Compilation Method of SONOS flush memory devices as claimed in claim 1, it is characterised in that the material of second Si-gate
For polysilicon, its height is 60~80nm, and length is 30~50nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410654584.4A CN104392965B (en) | 2014-11-17 | 2014-11-17 | A kind of Compilation Method of SONOS flush memory devices |
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| CN201410654584.4A CN104392965B (en) | 2014-11-17 | 2014-11-17 | A kind of Compilation Method of SONOS flush memory devices |
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| CN104392965B true CN104392965B (en) | 2018-01-02 |
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW546840B (en) * | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
| CN101958325B (en) * | 2009-07-16 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory unit and formation method thereof |
| CN101958323A (en) * | 2009-07-16 | 2011-01-26 | 中芯国际集成电路制造(上海)有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory unit and formation method thereof |
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