CN104851887B - A kind of SONOS double grids flush memory device and its Compilation Method - Google Patents
A kind of SONOS double grids flush memory device and its Compilation Method Download PDFInfo
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Abstract
The invention discloses a kind of SONOS double grids flush memory device, including the P type substrate with N-type source and drain both ends and respectively side by side positioned at the first polysilicon gate and the first control gate, the second polysilicon gate and the second control gate of both sides above and below substrate, first, second silicon nitride layer is respectively equipped between first, second control gate and substrate；When compiling, by first, second polysilicon gate is connected, apply the grid voltage equal to device threshold voltage, by first, second control gate is connected, apply the identical control gate voltage higher than device threshold voltage, positive voltage is applied to drain terminal, 0V voltages are applied to source, with first, its lower substrate area of second polysilicon gate induces relatively thin channel electrons layer, first, its lower substrate area of second control gate is induced compared with thick-channel electronic shell, under the acceleration of drain terminal positive voltage, the electronics of relatively thin channel electrons layer is accelerated to produce thermoelectron, and inject first under the action of high voltage of control gate, second silicon nitride layer completes compiling.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of SONOS double grids flush memory device and its compiling side
Method.
Background technology
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride-oxide-silicon)
It is that a kind of and flash memory contacts more close nonvolatile memory.The main distinction of it and main flow flash memory is, it uses
Silicon nitride rather than polysilicon serve as storage material.A SONOS branch be SHINOS (silicon-high dielectric-nitride-
Oxide-silicon).SONOS allows the program voltage lower than polysilicon flash memory and Geng Gao programming-erasing cycle-index, is one
Individual more active research, exploitation focus.SONOS flash memories have the advantage in terms of data preservation than floating gate flash memory, can use
Thinner oxide layer simultaneously preserves information more long.
A kind of code generation of Publication No. US5300803A U.S. Patent Publication is SSI (Source Side
Injection, source injection) nonvolatile memory structure.It is this effectively to be carried using the floating gate flash memory that SSI is code generation
The high injection efficiency of compiling, reduces power consumption.This flush memory device that the patent proposes is originally to solve code generation
For the inefficient note of CHEI (channel hot electron injection, channel hot electron injection) floating gate flash memory device
Enter and high power consumption and caused new structure.
Referring to Fig. 1, Fig. 1 is the existing principle schematic by the use of SSI as the floating gate flash memory of code generation.From Fig. 1
In the figure of double-head arrow upper section it can be seen that, it is original using CHEI as the floating gate flash memory structure of code generation device in order to
Ensure high channel hot electron generation rate, it is necessary in the voltage that drain terminal is increased.Meanwhile in order to ensure that high thermoelectron injects effect
Rate, it is necessary in grid high voltage.Transverse electric field reduces with the rise of grid voltage, likewise, longitudinal electric field is with grid
Pressure increases and increased.So the original device using CHEI as the floating gate flash memory structure of code generation must make drain terminal and grid
All high voltages, this results in the low and current power dissipation of channel hot electron injection efficiency is big.Thus gate high-voltage and leakage
End high voltage turns into conflict.
Therefore patented invention one kind divides row flash memory in grating device, as shown in the figure of Fig. 1 double-head arrow section below, positioned at a left side
The grid on side is control gate, and the grid on right side is floating boom, and floating boom and control gate are spatially staggered.Floating boom high voltage,
Control gate adds low-voltage, and drain terminal adds 5v high voltage.The injection efficiency of channel hot electron can so improved, and makes electric current
Lower power consumption.
The problem of dividing row grid floating gate flash memory structure to exist disclosed in the patent be：Because voltage ratio is higher added by drain terminal
(5v), cause drain terminal extend to substrate depletion width it is bigger, source is easy to high-tension with virtual depletion region
In the case of touch together, cause device break-through and failure.This defect is easy to lead when device size is reduced to sub- 100nm
Device break-through and failure are caused, such floating gate flash memory has no idea to carry out the upgrading of technology node and critical size contracting in technique
It is small, therefore the structure of the floating gate flash memory device must be changed, upgrading and the critical size of technology node can be carried out in technique
Reduce.
Meanwhile we flash memory size diminution during can run into threshold voltage shift the problem of.Such as document " Modeling
of Vth Shift in NAND Flash-Memory Cell Device Considering Crosstalk and
Pointed out in Short-Channel Effects ", it is short as the critical size of flash memory gradually decreases to sub- below 100nm scope
Channelling effect (Short Channel Effect) also gradually displays, and has had influence on the electrology characteristic of memory device, has made it
Threshold voltage causes possible readout error than having been drifted about during long raceway groove.
The double grids MOSFET that previous literature is mentioned is to be imitated during transistor size constantly reduces in order to resist short channel
A kind of device architecture answered and developed, when channel dimensions taper to below 100nm because its grid-control area is big, Electrostatic Control
Ability is strong, can effectively eliminate the short-channel effect caused by size is small.
And for example document " Double-Gate Silicon-on-Insulator Transistor with Volume
Inversion:A New Device with Greatly Enhanced Performance " are described, double grids MOSFET performance
Brilliance, very big sub-threshold slope, very big mutual conductance and drain terminal electric current can be obtained.It is known that due to short-channel effect,
When MOSFET sizes shorten, sub-threshold slope can diminish, and cause device to close continuous, leakage current is larger.Utilize double-gate structure
Similar short-channel effect, including hot carrier's effect, threshold voltage shift effect, DIBL (drain induced barrier reduction) can effectively be suppressed
Effect etc..To sum up, double grids MOSFET is most strong candidate's device architecture that following MOSFET critical sizes enter sub- 20nm
One of.
The content of the invention
It is an object of the invention to overcome drawbacks described above existing for prior art, there is provided one kind utilizes source injection compiling machine
The SONOS double grids flush memory device and its Compilation Method of system, SONOS device size can be effectively reduced, improve SONOS flash memories
Storage density, reduce current power dissipation of the SONOS flash memories in programming, so as to lift efficiency during SONOS flash memory programmings.
To achieve the above object, technical scheme is as follows：
A kind of SONOS double grids flush memory device, including：
P-type semiconductor substrate, it includes the source and drain terminal of the n-type doping positioned at both ends；And
Respectively side by side the substrate between the source and drain terminal up and down both sides and formed divide the first of row grid
Polysilicon gate and the first control gate, the second polysilicon gate and the second control gate, first, second control gate and the substrate it
Between be respectively provided with storage electric charge first, second silicon nitride layer, first polysilicon gate, the first control gate, the first nitrogen
SiClx layer and substrate is mutual and second polysilicon gate, the second control gate, the second silicon nitride layer and substrate mutually it
Between there is insulating barrier respectively；
Wherein, when the SONOS double grids flush memory device compiles, by the way that first, second polysilicon gate is connected, and
All apply the polysilicon gate pole tension equal to device threshold voltage, first, second control gate is connected, and all apply and be higher than
The identical control gate voltage of device threshold voltage, meanwhile, positive voltage is applied to the drain terminal, applies 0V electricity to the source
Pressure, the first relatively thin channel electrons layer is induced with its lower substrate area in first, second polysilicon gate, described
Its lower substrate area of first, second control gate induces the second thicker channel electrons layer of relatively described first channel electrons layer,
Under the acceleration of drain terminal positive voltage, the electronics of the first channel electrons layer is accelerated to produce thermoelectron, and described the
First, the lower injection of voltage effect first, second silicon nitride layer of the second control gate completes compiling.
Preferably, first polysilicon gate and the second polysilicon gate, first control gate and the second control gate, described
First silicon nitride layer and the second silicon nitride layer and each insulating barrier substrate between the source and drain terminal respectively
Upper and lower both sides physical dimension is symmetrical arranged.
Preferably, the thickness of first, second polysilicon gate is 85~115nm, the thickness of first, second control gate
Spend for 35~55nm, the thickness of first, second silicon nitride layer is 35~45nm；The insulating barrier is in first polysilicon
Between grid and first control gate, the first silicon nitride layer and second polysilicon gate and second control gate, second
Width between silicon nitride layer is 2.5~4.5nm, between first polysilicon gate, the first silicon nitride layer and the substrate
And the thickness between second polysilicon gate, the second silicon nitride layer and the substrate is 2.5~4.5nm, described first
Thickness between control gate and the first silicon nitride layer and between second control gate and the second silicon nitride layer is 10~14nm；
The thickness of the substrate is 18~28nm, and the length of the raceway groove is not more than 48nm, and the extended length of the source and drain is respectively
10~14nm.
Preferably, first, second polysilicon gate, the material of first, second control gate are polysilicon, described first,
The material of second silicon nitride layer is Si3N4, the material of the insulating barrier is silica.
Preferably, when the SONOS double grids flush memory device compiles, first, second polysilicon gate is connected, and all
Apply 4~5V identical polysilicon gate pole tension, first, second control gate is connected, and all apply the identical of 9~12V
Control gate voltage, meanwhile, apply 5~6V voltage to the drain terminal, 0V voltages are applied to the source.
A kind of Compilation Method of SONOS double grids flush memory device, the SONOS double grids flush memory device include：P-type semiconductor serves as a contrast
Bottom, it includes the source and drain terminal of the n-type doping positioned at both ends；And distinguish the institute between the source and drain terminal side by side
Stating substrate, both sides and formation divide the first polysilicon gate of row grid and the first control gate, the second polysilicon gate and second to control up and down
Grid, first, second silicon nitride layer of storage electric charge is respectively provided between first, second control gate and the substrate,
First polysilicon gate, the first control gate, the first silicon nitride layer and substrate is mutual and second polysilicon gate,
Two control gates, the second silicon nitride layer and substrate have insulating barrier respectively between each other；
The Compilation Method includes：The code generation injected using source, first, second polysilicon gate is connected, and
All apply the polysilicon gate pole tension equal to device threshold voltage, first, second control gate is connected, and all apply and be higher than
The identical control gate voltage of device threshold voltage, meanwhile, positive voltage is applied to the drain terminal, applies 0V electricity to the source
Pressure, the first relatively thin channel electrons layer is induced with its lower substrate area in first, second polysilicon gate, described
Its lower substrate area of first, second control gate induces the second thicker channel electrons layer of relatively described first channel electrons layer,
Under the acceleration of drain terminal positive voltage, the electronics of the first channel electrons layer is accelerated to produce thermoelectron, and described the
First, the lower injection of voltage effect first, second silicon nitride layer of the second control gate completes compiling.
Preferably, first polysilicon gate and the second polysilicon gate, first control gate and the second control gate, described
First silicon nitride layer and the second silicon nitride layer and each insulating barrier substrate between the source and drain terminal respectively
Upper and lower both sides physical dimension is symmetrical arranged.
Preferably, the thickness of first, second polysilicon gate is 85~115nm, the thickness of first, second control gate
Spend for 35~55nm, the thickness of first, second silicon nitride layer is 35~45nm；The insulating barrier is in first polysilicon
Between grid and first control gate, the first silicon nitride layer and second polysilicon gate and second control gate, second
Width between silicon nitride layer is 2.5~4.5nm, between first polysilicon gate, the first silicon nitride layer and the substrate
And the thickness between second polysilicon gate, the second silicon nitride layer and the substrate is 2.5~4.5nm, described first
Thickness between control gate and the first silicon nitride layer and between second control gate and the second silicon nitride layer is 10~14nm；
The thickness of the substrate is 18~28nm, and the length of the raceway groove is not more than 48nm, and the extended length of the source and drain is respectively
10~14nm.
Preferably, first, second polysilicon gate, the material of first, second control gate are polysilicon, described first,
The material of second silicon nitride layer is Si3N4, the material of the insulating barrier is silica.
Preferably, when the SONOS double grids flush memory device compiles, first, second polysilicon gate is connected, and all
Apply 4~5V identical polysilicon gate pole tension, first, second control gate is connected, and all apply the identical of 9~12V
Control gate voltage, meanwhile, apply 5~6V voltage to the drain terminal, 0V voltages are applied to the source.
The beneficial effects of the present invention are：The SONOS double grid flush memory devices of the present invention make use of double-gate structure, can be effective
SONOS size is reduced, so as to improve the integrated level of device and unit area storage density；Can be in reduction SONOS critical sizes
While, solve the problems, such as the short-channel effects such as thing followed threshold voltage shift；Also, the compiling injected by using source
Mechanism, it can solve the problem that the problems such as SONOS programming efficiencies are poor, program current power consumption is big.
Brief description of the drawings
Fig. 1 is the existing principle schematic by the use of SSI as the floating gate flash memory of code generation；
Fig. 2 is a kind of structural representation of SONOS double grids flush memory device of a preferred embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special that structure in accompanying drawing is not drawn according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should avoid being understood in this, as limitation of the invention.
In embodiment of the invention below, referring to Fig. 2, Fig. 2 is one kind of a preferred embodiment of the present invention
The structural representation of SONOS double grid flush memory devices.As shown in Fig. 2 the SONOS double grid flush memory devices of the present invention include：P-type is partly led
Body substrate 1, can be cylindrical structure, it includes the source 2 and drain terminal 3 of the n-type doping positioned at both ends, in source 2 and drain terminal 3
Between raceway groove 4；And including both sides and the formation point about 1 of the substrate between the source 2 and drain terminal 3 side by side respectively
The first polysilicon gate 5 and the first control gate 7, the second polysilicon gate 6 and the second control gate 8 of row grid, first, second control
First, second silicon nitride layer 9,10 of storage electric charge, the polysilicon are respectively provided between grid 7,8 and the substrate 1 processed
There is insulating barrier 11 respectively between grid, control gate, silicon nitride layer and substrate.Wherein, the polysilicon gate 5,6 is close to the source
2 sides are set, and the control gate 7,8 and silicon nitride layer 9,10 are set close to the side of drain terminal 3.
As a preferred embodiment, first and second polysilicon gate 5 and 6, the and of the first and second control gate 7
8th, first and second silicon nitride layer 9 and 10 and each insulating barrier 11 institute between the source 2 and drain terminal 3 respectively
State substrate about 1 both sides physical dimension be symmetrical arranged.Still optionally further, first, second polysilicon gate 5,6 85~
There is symmetrically the same thickness H between 115nm1；First, second control gate 7,8 has symmetrical phase between 35~55nm
Same thickness H2；First, second silicon nitride layer 9,10 has symmetrically the same thickness H between 35~45nm3；It is described exhausted
Width H of the edge layer 11 between the polysilicon gate and the control gate, silicon nitride layer4For 2.5~4.5nm, in the polycrystalline
Thickness H between Si-gate, silicon nitride layer and the substrate5For 2.5~4.5nm, between the control gate and silicon nitride layer
Thickness H6For 10~14nm；The thickness H of the substrate (silicon fiml)7For 18~28nm, the length H of the raceway groove8No more than 48nm,
The extended length H of the source and drain9Respectively 10~14nm.For example, as an example, each several part of device can be processed as：
The thickness H of first, second polysilicon gate1For 90nm, the thickness H of first, second control gate2For 40nm, first, second silicon nitride
The thickness H of layer3For 40nm；The width H of insulating barrier between polysilicon gate and control gate or silicon nitride layer4For 4nm, polysilicon gate or
The thickness H of insulating barrier between silicon nitride layer and substrate5For 3nm, the thickness H of insulating barrier between control gate and silicon nitride layer6For
12nm；The thickness H of substrate silicon fiml7For 20nm, the channel length H of device8The length H to extend for 45nm, source, leakage9All it is 12nm.
As a preferred embodiment, the polysilicon gate 5 and 6, the material of control gate 7 and 8 are all polysilicon, the nitridation
The material of silicon layer 9 and 10 is Si3N4, the material of the insulating barrier 11 is silica.
The double-gate structure of the invention described above device can effectively eliminate the threshold voltage drift that SONOS critical sizes shorten and brought
Shifting problem.And the manufacturing process of device of the present invention is simultaneously uncomplicated, can be produced in general Semiconductor Manufacturing Company.
Below in conjunction with Fig. 2, the Compilation Method of the present invention is described further.As shown in Figure 2, it is illustrated that black in channel region
Color round dot represents electronics.When the SONOS double grid flush memory devices to the invention described above are compiled, the Compilation Method includes：Profit
The code generation of (Source Side Injection, SSI) is injected with source, first, second polysilicon gate 5,6 is connected
It is connected together, adds same voltage, first, second control gate 7,8 is also linked together, and adds same voltage；Institute
State first, second polysilicon gate 5,6 plus the low-voltage equal to device threshold voltage, first, second control gate 7,8 plus remote height
In the high voltage of device threshold voltage, such as the high voltage for being about twice in device threshold voltage can be added；Meanwhile to the drain terminal 3
Apply high positive voltage, 0V voltages are applied to the source 2.The present invention Fundamentals of Compiling be：First, second polysilicon gate 5,6
Added voltage is just equal to threshold voltage, can induce the first relatively thin channel electrons layer 12 in its lower substrate area
(exemplarily being represented in figure with single layer electronic layer)；Voltage added by first, second control gate 7,8 is far above device threshold electricity
Pressure, the second thicker channel electrons layer 13 of relative first channel electrons layer 12 (example in figure can be induced in its lower substrate area
Represented with double-layer electric sublayer to property)；High positive voltage added by drain terminal 3 can accelerate the electronics of the first channel electrons layer 12, produce
Thermoelectron with enough energy, and under the action of high voltage of first, second control gate 7,8, inject first, second nitrogen
SiClx layer 9,10 completes compiling (hollow arrow is signified in such as figure).
As an optional embodiment, when being compiled to the SONOS double grids flush memory device, by described first,
Two polysilicon gates 5,6 are connected, and the identical polysilicon gate pole tension equal to device threshold voltage for all applying 4~5V is (different
Device can have different threshold voltages), first, second control gate 7,8 is connected, and all apply being far above for 9~12V
The identical control gate voltage of device threshold voltage, meanwhile, to 5~6V of the drain terminal 3 application high voltage, to the source 2
Apply 0V voltages.For example, as an example, in programming, polysilicon gate, control gate all use identical polysilicon as material
Material, and first, second polysilicon gate is connected, first, second control gate is connected；Then, to first, second polysilicon
Grid all add threshold voltage 4V, and 9V high voltage is all added to first, second control gate, and drain terminal adds 5V high voltage, and source adds
0V.So, you can the first relatively thin channel electrons layer is induced in substrate area of first, second polysilicon gate under it,
First, substrate area of second control gate under it induces the second thicker channel electrons layer；5V high voltages added by drain terminal can add
The the first channel electrons layer electronics induced under fast first, second polysilicon gate, thermoelectron of the generation with enough energy, and
Under the 9V action of high voltage of first, second control gate, inject first, second silicon nitride layer and complete compiling.
In summary, SONOS double grid flush memory devices of the invention make use of double-gate structure, can have SONOS size
Effect narrow down to sub- 50nm, so as to improve integrated level and unit area storage density, can while SONOS critical sizes are reduced,
Solve the problems, such as the short-channel effects such as thing followed threshold voltage shift；Also, the code generation injected by using source, energy
Enough solves the problems such as SONOS programming efficiencies are poor, program current power consumption is big.
Above-described is only the preferred embodiments of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
- A kind of 1. SONOS double grids flush memory device, it is characterised in that including：P-type semiconductor substrate, it includes the source and drain terminal of the n-type doping positioned at both ends；AndBoth sides and formation divide the first polycrystalline of row grid above and below the substrate between the source and drain terminal side by side respectively Si-gate and the first control gate, the second polysilicon gate and the second control gate, divide between first, second control gate and the substrate First, second silicon nitride layer for storing electric charge, first polysilicon gate, the first control gate, the first silicon nitride She You be used for Layer and substrate is mutual and the second polysilicon gate, the second control gate, the second silicon nitride layer and the substrate divide between each other Ju You not insulating barrier；Wherein, when the SONOS double grids flush memory device compiles, by the way that first, second polysilicon gate is connected, and all apply Add the polysilicon gate pole tension equal to device threshold voltage, first, second control gate is connected, and all apply and be higher than device The identical control gate voltage of threshold voltage, meanwhile, positive voltage is applied to the drain terminal, 0V voltages are applied to the source, with In first, second polysilicon gate, its lower substrate area induces the first relatively thin channel electrons layer, described first, Its lower substrate area of second control gate induces the second thicker channel electrons layer of relatively described first channel electrons layer, in drain terminal Under the acceleration of positive voltage, the electronics of the first channel electrons layer is accelerated to produce thermoelectron, and described first, second The lower injection of voltage effect first, second silicon nitride layer of control gate completes compiling.
- 2. SONOS double grids flush memory device according to claim 1, it is characterised in that first polysilicon gate and second Polysilicon gate, first control gate and the second control gate, first silicon nitride layer and the second silicon nitride layer and each described Both sides physical dimension is symmetrical arranged insulating barrier above and below the substrate between the source and drain terminal respectively.
- 3. SONOS double grids flush memory device according to claim 1, it is characterised in that first, second polysilicon gate Thickness is 85~115nm, and the thickness of first, second control gate is 35~55nm, the thickness of first, second silicon nitride layer Spend for 35~45nm；The insulating barrier between first polysilicon gate and first control gate, the first silicon nitride layer with And the width between second polysilicon gate and second control gate, the second silicon nitride layer is 2.5~4.5nm, described Between first polysilicon gate, the first silicon nitride layer and the substrate and second polysilicon gate, the second silicon nitride layer and institute It is 2.5~4.5nm to state the thickness between substrate, and between first control gate and the first silicon nitride layer and described second controls Thickness between grid processed and the second silicon nitride layer is 10~14nm；The thickness of the substrate is 18~28nm, the length of the raceway groove Degree is not more than 48nm, and the extended length of the source and drain is respectively 10~14nm.
- 4. the SONOS double grid flush memory devices according to claims 1 to 3 any one, it is characterised in that described first, Two polysilicon gates, the material of first, second control gate are polysilicon, and the material of first, second silicon nitride layer is Si3N4, institute The material for stating insulating barrier is silica.
- 5. SONOS double grids flush memory device according to claim 1, it is characterised in that when the SONOS double grids flush memory device During compiling, first, second polysilicon gate is connected, and all applies 4~5V identical polysilicon gate pole tension, by described the First, the second control gate is connected, and all applies 9~12V identical control gate voltage, meanwhile, 5~6V's is applied to the drain terminal Voltage, 0V voltages are applied to the source.
- 6. a kind of Compilation Method of SONOS double grids flush memory device, it is characterised in that the SONOS double grids flush memory device includes：P Type Semiconductor substrate, it includes the source and drain terminal of the n-type doping positioned at both ends；And it is located at the source and leakage side by side respectively Both sides and formation divide the first polysilicon gate and the first control gate, the second polysilicon gate of row grid above and below the substrate between end With the second control gate, the first, second of storage electric charge is respectively provided between first, second control gate and the substrate Silicon nitride layer, first polysilicon gate, the first control gate, the first silicon nitride layer and substrate are mutual and described more than second Crystal silicon grid, the second control gate, the second silicon nitride layer and substrate have insulating barrier respectively between each other；The Compilation Method includes：The code generation injected using source, first, second polysilicon gate is connected, and all applies Add the polysilicon gate pole tension equal to device threshold voltage, first, second control gate is connected, and all apply and be higher than device The identical control gate voltage of threshold voltage, meanwhile, positive voltage is applied to the drain terminal, 0V voltages are applied to the source, with In first, second polysilicon gate, its lower substrate area induces the first relatively thin channel electrons layer, described first, Its lower substrate area of second control gate induces the second thicker channel electrons layer of relatively described first channel electrons layer, in drain terminal Under the acceleration of positive voltage, the electronics of the first channel electrons layer is accelerated to produce thermoelectron, and described first, second The lower injection of voltage effect first, second silicon nitride layer of control gate completes compiling.
- 7. Compilation Method according to claim 6, it is characterised in that first polysilicon gate and the second polysilicon gate, First control gate and the second control gate, first silicon nitride layer and the second silicon nitride layer and each insulating barrier difference Both sides physical dimension is symmetrical arranged above and below the substrate between the source and drain terminal.
- 8. Compilation Method according to claim 6, it is characterised in that the thickness of first, second polysilicon gate is 85 ~115nm, the thickness of first, second control gate are 35~55nm, the thickness of first, second silicon nitride layer for 35~ 45nm；The insulating barrier is between first polysilicon gate and first control gate, the first silicon nitride layer and described Width between two polysilicon gates and second control gate, the second silicon nitride layer is 2.5~4.5nm, in first polycrystalline Between Si-gate, the first silicon nitride layer and the substrate and second polysilicon gate, the second silicon nitride layer and the substrate it Between thickness be 2.5~4.5nm, between first control gate and the first silicon nitride layer and second control gate and Thickness between nitride silicon layer is 10~14nm；The thickness of the substrate is 18~28nm, and the length of the raceway groove is not more than 48nm, the extended length of the source and drain is respectively 10~14nm.
- 9. according to the Compilation Method described in claim 6~8 any one, it is characterised in that first, second polysilicon Grid, the material of first, second control gate are polysilicon, and the material of first, second silicon nitride layer is Si3N4, the insulating barrier Material be silica.
- 10. Compilation Method according to claim 6, it is characterised in that when the SONOS double grids flush memory device compiles, First, second polysilicon gate is connected, and all applies 4~5V identical polysilicon gate pole tension, by described first, second Control gate is connected, and all applies 9~12V identical control gate voltage, meanwhile, apply 5~6V voltage to the drain terminal, it is right The source applies 0V voltages.
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| TW201250694A (en) * | 2011-06-14 | 2012-12-16 | Univ Nat Chiao Tung | Nonvolatile semiconductor memory device |
| CN104332471A (en) * | 2014-11-17 | 2015-02-04 | 上海华力微电子有限公司 | SONOS (silicon oxide nitride oxide silicon) flash memory device and compiling method thereof |
| CN104377248A (en) * | 2014-11-17 | 2015-02-25 | 上海华力微电子有限公司 | Floating gate flash memory device and programming method thereof |
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