CN112002694B - SONOS memory and manufacturing method thereof - Google Patents

SONOS memory and manufacturing method thereof Download PDF

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CN112002694B
CN112002694B CN202011159566.0A CN202011159566A CN112002694B CN 112002694 B CN112002694 B CN 112002694B CN 202011159566 A CN202011159566 A CN 202011159566A CN 112002694 B CN112002694 B CN 112002694B
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oxide layer
substrate
control gate
layer
sonos memory
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CN112002694A (en
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葛成海
李庆民
林滔天
祝进专
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Jingxincheng Beijing Technology Co Ltd
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Jingxincheng Beijing Technology Co Ltd
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract

The invention provides a SONOS memory and a manufacturing method thereof, wherein the manufacturing method of the SONOS memory comprises the following steps: firstly, providing a substrate, and forming a control gate on the substrate; secondly, etching the substrate on one side of the control gate to form an L-shaped groove; then, forming an ONO medium layer on the L-shaped groove, wherein the ONO medium layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer, and the first oxide layer and the silicon nitride layer are both L-shaped structures; and finally, forming a source electrode and a drain electrode on the control gate and the substrate on the two sides of the ONO dielectric layer through a source-drain ion implantation process. The SONOS memory manufactured by the method has higher charge storage capacity, lower operation voltage and capability of reducing the possibility that the source electrode and the drain electrode are broken down.

Description

SONOS memory and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to an SONOS memory and a manufacturing method thereof.
Background
Non-volatile Memory (NVM) includes mask programmable read only Memory (MROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Flash Memory (Flash).
The flash memory with the Floating gate structure adopts polysilicon to store charges, and the Floating Gate (FG) has a higher capacitive coupling coefficient relative to the Control Gate (CG), so that the thickness of the stack of the Floating gate and the Control gate is too large, and the integration of the flash memory with the Floating gate structure and the CMOS device becomes more and more difficult as the size of the semiconductor memory is reduced.
The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, Silicon/Silicon dioxide/Silicon Nitride/Silicon dioxide/Silicon) memory does not have a capacitive coupling mechanism, the thickness of the Silicon Nitride is not limited, the lamination height is only half of that of a flash memory with a floating gate structure, and the technical bottleneck of the floating gate is overcome. The SONOS memory is perfectly compatible with a standard CMOS process compared with a flash memory with a floating gate structure.
However, the SONOS memory is prone to source-drain breakdown, and with the further development of electronic products, it is desirable that the memory device of the electronic product has smaller size and higher performance. Therefore, it is desirable to design a new SONOS memory device with smaller feature size, lower operating voltage and stronger charge storage capability, and reduce the possibility of source-drain breakdown.
Disclosure of Invention
The invention aims to provide a SONOS memory and a manufacturing method thereof, which are used for improving the charge storage capacity of the SONOS memory, reducing the operating voltage and reducing the possibility of breakdown of a source electrode and a drain electrode.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a SONOS memory device, including:
providing a substrate, and forming a control gate on the substrate;
etching the substrate on one side of the control gate to form an L-shaped groove, wherein the L-shaped groove comprises a groove bottom wall and a groove side wall, and one end, close to the control gate, of the groove bottom wall is connected with the bottom end of the groove side wall;
forming an ONO dielectric layer on the L-shaped groove, wherein the ONO dielectric layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer, the first oxide layer and the silicon nitride layer are both of L-shaped structures, the first oxide layer covers the side wall of the control gate, the side wall of the groove and part of the bottom wall of the groove, the silicon nitride layer covers the first oxide layer, and the second oxide layer covers the silicon nitride layer; and the number of the first and second groups,
and forming a source electrode and a drain electrode on the substrate on two sides of the control gate and the ONO dielectric layer by a source-drain ion implantation process.
Optionally, in the method for manufacturing a SONOS memory, before forming the ONO dielectric layer, the method further includes: and carrying out a light doping ion implantation process on the bottom wall of the groove to form a light doping area.
Optionally, in the manufacturing method of the SONOS memory, a depth of the lightly doped region is greater than an ion implantation depth of the drain.
Optionally, in the method for manufacturing a SONOS memory, a depth of the L-shaped trench is greater than an ion implantation depth of the source.
Optionally, in the method for manufacturing a SONOS memory, a specific process of forming the L-shaped trench includes:
forming a layer of photoresist on the substrate and the control gate;
patterning the photoresist by adopting an exposure and development technology to define an L-shaped groove region, wherein the L-shaped groove region is positioned on one side of the control grid;
etching the substrate of the L-shaped groove region by adopting a dry etching process to form the L-shaped groove;
and removing the photoresist.
Optionally, in the manufacturing method of the SONOS memory, a gate oxide layer is further included between the substrate and the control gate.
Optionally, in the method for manufacturing the SONOS memory, a method for forming the first oxide layer includes an in-situ water vapor method.
Optionally, in the method for manufacturing the SONOS memory, the first oxide layer has a thickness of 15A-25A, and the silicon nitride layer has a thickness of 60A-80A.
Optionally, in the method for manufacturing the SONOS memory, a cross-sectional shape of the second oxide layer is a rectangle.
In order to achieve the above objects and other related objects, the present invention further provides a SONOS memory device, which is manufactured by the above manufacturing method of the SONOS memory device.
In summary, the invention provides a method for manufacturing a SONOS memory, which increases an effective channel between a source and a drain by forming an L-shaped trench on the substrate on one side of a control gate, so as to reduce the possibility that the source and the drain are broken down. And an ONO dielectric layer is formed in the L-shaped groove, and the silicon nitride layer is in an L-shaped structure, because the moving direction of hot carriers is horizontal, the hot carriers can easily enter the L-shaped silicon nitride layer, namely, more electrons are stored in the silicon nitride layer, the storage capability of the silicon nitride layer is enhanced, and the required operating voltage is lower.
Drawings
FIG. 1 is a schematic diagram of a floating gate flash memory;
FIG. 2 is a schematic structural diagram of a SONOS memory;
FIG. 3 is a flow chart of a method of fabricating a SONOS memory device according to an embodiment of the invention;
FIGS. 4-7 are schematic structural diagrams illustrating steps of a method for fabricating a SONOS memory according to an embodiment of the invention;
FIG. 8 is a top view of a SONOS memory device according to an embodiment of the present invention;
FIGS. 9-12 are schematic diagrams of the potential of a SONOS memory according to an embodiment of the present invention during programming, erasing, and reading;
wherein the content of the first and second substances,
in fig. 1:
110-substrate, 120-floating gate, 130-control gate, 111-source, 112-drain;
in fig. 2:
210-substrate, 220-gate oxide, 230-control gate, 211-source, 212-drain;
in fig. 3-12:
311-deep N well region, 312-P well, 313-N well, 3141-trench sidewall, 3142-trench bottom wall, 315-lightly doped region, 316-drain, 317-P + region, 318-source, 320-oxide layer, 321-gate oxide layer, 330-polysilicon layer, 331-control gate, 341-first oxide layer, 342-silicon nitride layer, 343-second oxide layer.
Detailed Description
Referring to fig. 1, a conventional flash memory with a Floating gate structure includes a substrate 110, a Floating Gate (FG) 120 and a Control Gate (CG) 130, the Floating gate 120 and the Control gate 130 are made of polysilicon, a source 111 and a drain 112 are formed in the substrate 110 at two sides of the Floating gate 120, a silicon oxide layer (not shown) is formed between the substrate 110 and the Floating gate 120, and a silicon oxide layer is also formed between the Floating gate 120 and the Control gate 130. The flash memory with the floating gate structure adopts polysilicon to store charges, and the floating gate 120 has a higher capacitive coupling coefficient relative to the control gate 130, so that the stack thickness of the floating gate 120 and the control gate 130 is too large, and the integration with the CMOS memory is more and more difficult along with the reduction of the size of the semiconductor memory.
Referring to fig. 2, the conventional SONOS memory structure includes a substrate 210, a gate oxide layer 220 over the substrate 210, and a control gate 230 over the gate oxide layer 220, wherein a source (S) 211 and a drain (D) 212 are formed in the substrate 210 at two sides of the control gate 230. Compared with the traditional flash memory with a floating gate structure, the SONOS memory has no capacitive coupling mechanism, has no limit on the thickness of silicon nitride, has the lamination height of only half of that of the flash memory with the floating gate structure, can overcome the technical bottleneck of the floating gate, has stronger charge storage capacity and lower operating voltage and power compared with the flash memory with the floating gate structure, and can be perfectly compatible with the standard CMOS process.
However, the SONOS memory in fig. 2 is prone to source-drain breakdown, and with the further development of electronic products, the memory device size of the electronic products is desired to be smaller and the performance of the electronic products to be higher.
In order to improve the charge storage capability of the SONOS memory, reduce the operating voltage, and reduce the possibility that the source and drain are broken down, the present invention provides a method for manufacturing the SONOS memory, and referring to fig. 3, the method includes:
the method comprises the following steps: providing a substrate, and forming a control gate on the substrate;
step two: etching the substrate on one side of the control gate to form an L-shaped groove, wherein the L-shaped groove comprises a groove bottom wall and a groove side wall, and one end, close to the control gate, of the groove bottom wall is connected with the bottom end of the groove side wall;
step three: forming an ONO dielectric layer on the L-shaped groove, wherein the ONO dielectric layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer, the first oxide layer and the silicon nitride layer are both of L-shaped structures, the first oxide layer covers the side wall of the control gate, the side wall of the groove and part of the bottom wall of the groove, the silicon nitride layer covers the first oxide layer, and the second oxide layer covers the silicon nitride layer; and the number of the first and second groups,
step four: and forming a source electrode and a drain electrode on the substrate on two sides of the control gate and the ONO dielectric layer by a source-drain ion implantation process.
The SONOS memory device and the method for fabricating the same according to the embodiments of the present invention will be described in further detail with reference to fig. 4-12 and the following embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 4, a substrate is provided, which may be one of an undoped single crystal silicon substrate, an impurity-doped single crystal silicon substrate, a silicon-on-insulator (SOI) substrate, and the like. Various doped regions and other suitable features (not shown), etc., may also be formed in the substrate. For example, in the substrate shown in fig. 4, a deep N-well region (DNW)311, a P-well (PW)312, an N-well (NW)313, and a shallow trench isolation region (not shown) are formed. The specific forming process of the deep N-well region 311, the P-well 312, and the N-well 313 may include: firstly, defining a shallow trench isolation region by a photoetching technology, forming an isolation trench by an etching process, and then filling a medium in the isolation trench by a chemical vapor deposition process to form a shallow trench isolation structure; then, implanting N-type doped ions, such As phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, into the substrate by an ion implantation process to form the deep N-well region 311; next, defining a P-well region by using a photolithography technique, and implanting P-type doped ions, such as boron (B) ions, boron fluoride (BF2+), gallium (Ga) ions, and indium (In) ions, into the substrate by using an ion implantation process to form a P-well 312; and then, defining an N-well region by using a photoetching technology, and injecting N-type doped ions into the substrate by ion injection to form an N-well 313, wherein the N-well 313 is positioned at the inner side of the shallow trench isolation structure and is adjacent to the P-well 312. The photolithography technique is a key technique for manufacturing transistors and their connections, and generally refers to irradiating a photoresist on a Wafer (Wafer) with a light beam through a mask in a semiconductor manufacturing process; irradiating the photoresist on the wafer by electron beam and ion beam through the mask and the reticle (Stencil); or directly irradiating the photoresist on the wafer without the mask or the pattern gauge (direct writing) to make the photoresist generate chemical actions such as polarity change, main chain scission, main chain cross-linking and the like, and transferring the specific pattern of the mask, the pattern gauge or the direct writing onto the wafer after developing.
Referring to fig. 5, an oxide layer 320 is formed on the substrate, i.e., the oxide layer 320 is formed over the P-well 312 and the N-well 313. The oxide layer 320 may be formed using deposition or epitaxial growth techniques known in the art, including but not limited to thermal oxidation or Chemical Vapor Deposition (CVD). The oxide layer 320 is formed, for example, using a thermal furnace process. The material of the oxide layer 320 is preferably silicon oxide, and the thickness of the oxide layer 320 is preferably 150A-250A.
Continuing with fig. 5, a polysilicon (poly) layer 330 is formed over the oxide layer 320, and the polysilicon layer 330 may be formed using deposition or epitaxial growth techniques known in the art, including but not limited to Chemical Vapor Deposition (CVD). The polysilicon layer 330 is formed, for example, using a low pressure chemical vapor deposition method. The thickness of the polycrystalline silicon layer 330 is preferably 1500A-2500A.
Referring to fig. 6, a gate region is defined by photolithography, and the polysilicon layer 330 and the oxide layer 320 of the gate region are etched to form a control gate 331 and a gate oxide layer 321. The gate oxide 321 is disposed between the substrate and the control gate 331 so that they are electrically isolated from each other, i.e., the gate oxide 321 serves to block stored charges from entering the control gate 331.
After the control gate 331 and the gate oxide 321 are formed, a layer of photoresist is formed on the substrate and the control gate 331; patterning the photoresist by adopting an exposure and development technology to define an L-shaped groove region, wherein the L-shaped groove region is positioned on one side of the control gate 331; etching the substrate of the L-shaped groove area to form an L-shaped groove, wherein the etching is preferably dry etching; and finally removing the photoresist. The L-shaped trench includes a trench bottom wall 3142 and a trench sidewall 3141, and one end of the trench bottom wall 3142 close to the control gate 331 is connected to a bottom end of the trench sidewall 3141. The groove bottom wall 3142 may be obliquely disposed on one end of the groove bottom wall 3142, and it is further preferable that the groove bottom wall 3142 is vertically disposed on one end of the groove bottom wall 3142. The following embodiments are described in detail with the groove bottom wall 3142 disposed vertically on one end of the groove bottom wall 3142.
Referring to fig. 7 and 8, after forming the L-shaped trench, a lightly doped region 315 is formed on the substrate at the L-shaped trench (trench bottom wall 3142) by a lightly doped ion implantation process, the lightly doped region 315 is located above the P-well 312, and ions implanted by the lightly doped ion implantation process are N-type doped ions, that is, the lightly doped region 315 is an N-type lightly doped region (NLDD). The depth of the lightly doped region 315 is greater than the ion implantation depth of the drain. The concentration of the lightly doped region 315 affects the injection effect of hot carriers, and thus affects the operating voltages for programming, erasing, and reading. Thus, a controllable adjustment of the SONOS memory operating voltage can be achieved by varying the concentration of the lightly doped region 315. For example, the increased concentration of the lightly doped region 315 improves the hot carrier injection effect and reduces the operating voltage for programming, erasing, and reading. When a carrier (e.g., an electron or a hole) obtains a large energy from the outside, it becomes a hot carrier. For example, under the action of a strong electric field, the carriers drift along the direction of the electric field continuously and accelerate continuously, so that great kinetic energy can be obtained, and the carriers can become hot carriers.
Continuing to refer to fig. 7, an ONO dielectric layer is formed on the L-shaped trench, and the ONO dielectric layer sequentially includes, from inside to outside, a first oxide layer 341, a silicon nitride layer 342, and a second oxide layer 343, where the first oxide layer 341 and the silicon nitride layer 342 are both L-shaped structures, the second oxide layer 343 is a rectangular structure, the first oxide layer 341 covers the sidewall of the control gate 331, the trench sidewall 3141, and a partial region of the trench bottom wall 3142, the silicon nitride layer 342 covers the first oxide layer 341, and the second oxide layer 343 covers the silicon nitride layer 342.
The process of forming the ONO dielectric layer on the L-shaped groove comprises the following steps: and generating an ONO film on the L-shaped groove, and etching the ONO film to form the ONO dielectric layer. The specific process comprises the following steps: firstly, forming a first oxide film on the L-shaped trench, wherein the first oxide film covers the side wall of the control gate 331, the trench side wall 3141 and the trench bottom wall 3142, and etching the first oxide film by using a dry etching method to form a first oxide layer 341; then, a nitride film is formed on the first oxide layer 341, and a nitride layer 342 is formed by dry etching; finally, a second oxide film is formed on the nitride layer 342, and a second oxide layer 343 is formed by dry etching. The method for forming the first oxide film is preferably an in-situ steam method. The method of forming the nitride film and the second oxide film may utilize deposition or epitaxial growth techniques known in the art. The nitride film and the second oxide film are formed, for example, by a chemical vapor deposition method.
The material of the first oxide layer 341 is preferably silicon oxide, and the surface uniformity of the silicon oxide can be improved by using an in-situ water vapor method. The first oxide layer 341 is used to block stored charge from returning to the substrate. Therefore, a controllable adjustment of the operating voltage of the SONOS memory device can be achieved by the thickness of the first oxide layer 341. As the thickness of the first oxide layer 341 increases, the operating voltage of the SONOS memory device increases because: when the SONOS memory device is programmed, the first oxide layer 341 is too thick, so that hot carriers are not easy to enter the silicon nitride layer 342, and the SONOS memory device needs to use a larger operation voltage to enable the hot carriers to enter the silicon nitride layer 342. If the thickness of the first oxide layer 341 is too thin, the stored charges cannot be well blocked from returning to the substrate, and the storage of the SONOS memory is unstable. Therefore, the thickness of the first oxide layer 341 is preferably 15A-25A, and the SONOS memory has a low operating voltage and is stable in storage in this interval. Therefore, the present invention can improve the storage stability by changing the thickness of the first oxide layer 341, thereby improving the storage performance of the SONOS memory.
The thickness of the silicon nitride layer 342 is preferably 60A-80A. The silicon nitride layer 342 is used for storing charges, and the Si/N atomic percentage of the silicon nitride layer for storing charges can be changed through a process so as to change an energy band structure, so that the quantity and the stability of trapped charges are improved. The silicon nitride layer 342 includes a horizontal portion parallel to the trench bottom wall 3142 and a vertical portion parallel to the trench sidewall 3141, and the bottom end of the vertical portion of the silicon nitride layer is connected to an end of the horizontal portion of the silicon nitride layer close to the control gate 331. Electrons or holes stored in the silicon nitride layer cannot return to the substrate due to the high barrier and a certain thickness of the first oxide layer 341, thereby maintaining a good storage charge retention capability. The first oxide layer 341 includes a first oxide layer horizontal portion parallel to the trench bottom wall 3142 and a first oxide layer vertical portion parallel to the trench sidewall 3141, and a bottom end of the first oxide layer vertical portion is connected to an end of the first oxide layer horizontal portion close to the control gate 331. The first oxide layer horizontal portion is located between the silicon nitride layer horizontal portion and the trench bottom wall 3142, and the first oxide layer vertical portion is located between the trench sidewall 3141 (or the sidewall of the control gate 331) and the silicon nitride layer vertical portion.
Continuing with fig. 7, source 318 and drain 316 are formed on the substrate on either side of the control gate 331 and ONO dielectric layer by a source-drain ion implantation process. The first oxide layer 341 covers the sidewalls of the control gate 331, the trench sidewalls 3141, and a portion of the trench bottom wall 3142, wherein the portion of the trench bottom wall 3142 includes a portion of the trench bottom wall where the lightly doped region 315 is located, so as to provide a space for forming a drain on the exposed lightly doped region 315. In addition, when the source-drain ion implantation process is performed, an N + region is formed on the N well 313, and the N + region, the N well 313 and the deep N well region 311 (DNW) are connected to isolate the whole SONOS memory, so that the influence of an external potential is prevented. The depth of the L-shaped trench needs to be greater than the ion implantation depth of the source 318, so that the moving direction (i.e., the current direction) of the hot carriers formed under the action of the operating voltage can be perpendicular to the first oxide layer vertical portion and the silicon nitride layer vertical portion, so that the hot carriers can more easily tunnel through the first oxide layer 341 into the silicon nitride layer, which is helpful for increasing the storage capacity of the silicon nitride layer and reducing the operating voltage.
The portion under the control gate 331 and disposed between the source 318 and drain 316 is referred to as the channel, which provides a current path between the source 318 and drain 316. The source 318 and the drain 316 are doped with ions of the corresponding conductivity type, such as N-type dopant ions. The control gate 331 is used to control the flow of current between the source 318 and the drain 316. The source 318 is located at the substrate where the top end of the trench sidewall 3141 is located, and the drain 316 is located at the trench bottom wall 3142, that is, there is a height difference between the source 318 and the drain 316, and the effective channel between the source 318 and the drain 316 is not linear, so that the effective channel between the source 318 and the drain 316 is increased, which is beneficial to overcoming the short channel effect, reducing the possibility of breakdown of the source and the drain, and facilitating the realization of smaller feature size. Also, the effective channel length between the source 318 and the drain 316 may be increased by increasing the depth of the L-shaped trench. As such, even though the absolute distance between the source 318 and the drain 316 is reduced as the size of the SONOS memory device is reduced, the short channel effect of the SONOS memory device can still be effectively improved due to the non-linear effective conductive channel formed.
After the source 318 and the drain 316 are formed, a P + region 317 is formed on the side of the source 318 away from the control gate 331 by using P-doped ion implantation.
In fig. 8, a top view of the SONOS memory is shown, with the portion of the control gate 331 extending beyond the N-well 313 for wiring. The memory shown in fig. 8 is a single structure, i.e., only one control gate and source and drain. The memory can also be a double structure, namely two control gates are formed on the P well, and other structures around the two control gates are symmetrically distributed. For example, a first P + region, a first source, a first control gate, a first ONO dielectric layer, a drain, a second ONO dielectric layer, a second control gate, a second source, and a second P + region are sequentially formed from one side of the P well. Two control gates share a drain, and the region between the two control gates forms a trench. Because the first source electrode, the drain electrode and the second source electrode and the drain electrode are not in the same horizontal plane, the effective channel length between the two groups of source electrodes and the two groups of drain electrodes is increased, and the possibility of breakdown of the source electrodes and the drain electrodes can be effectively reduced. Since the ONO dielectric layer has L-shaped silicon nitride, the operation voltage can be reduced, and the storage capacity can be improved.
Referring to fig. 9, programming, erasing and reading of the SONOS memory device are performed by applying certain voltages to the P + region 317, the source 318, the drain 316 and the control gate 331. One end of the P + region 317 connected to a voltage is referred to as a terminal B, one end of the source 318 connected to a voltage is referred to as a terminal S, one end of the control gate 331 connected to a voltage is referred to as a terminal G, and one end of the drain 316 connected to a voltage is referred to as a terminal D. The state of the stored electrons in the ONO dielectric layer is changed by applying voltage, so that the working condition of the SONOS memory is determined.
For example, referring to fig. 10, in a specific programming operation, the S terminal, B terminal voltage +0V (i.e., Vs =0V, Vb = 0V), and the D terminal voltage PHV (i.e., Vd = PHV), which is a positive high voltage, are 1-3V (i.e., Vg = 1-3V), and under the voltage of the S and D terminals, a part of electrons enter the silicon nitride layer 342 through a hot electron injection (hot electron injection) mechanism and are stored in the silicon nitride layer 342. Since the L-shaped silicon nitride layer is formed on the L-shaped trench, hot carriers are mainly stored in the vertical portion of the silicon nitride layer, and since the direction of current flow is horizontal, the hot carriers can enter the vertical portion of the silicon nitride layer more easily, the storage capacity of the silicon nitride layer is enhanced, more electrons are stored, and the required gate voltage (i.e., G-terminal voltage) is lower, for example, the gate voltage is Vdd (i.e., the operating voltage inside the SONOS memory). While the hot carriers of the conventional SONOS memory are stored in the silicon nitride layer in the horizontal direction, the gate voltage required to store the hot carriers in the silicon nitride layer is high. Therefore, the SONOS memory provided by the invention has lower operating voltage when being programmed.
Referring to FIG. 11, in a specific erase operation, the voltages at terminal S, terminal B, and terminal G, PHV, and terminal D, PHV-2V, are applied to the terminal B, electrons in the silicon nitride layer are pulled into the substrate by FN (flow-Nordheim tunneling) to be erased. According to the invention, the voltage required by electron tunneling can be reduced by adopting the thinner first oxide layer.
Referring to FIG. 12, in one particular read operation, the D and G terminals are Vdd and the S and B terminals are 0V. The electronic state in the silicon nitride layer can affect the starting voltage of the SONOS memory, electrons are stored in the silicon nitride in the programming state, the starting voltage of the SONOS memory is increased, and the read current is smaller than 1. In the erasing state, the number of stored electrons in the silicon nitride is reduced relative to the programming state, the turn-on voltage of the SONOS memory is reduced, and the read current is larger than 0.
In summary, the invention provides a method for manufacturing a SONOS memory, which increases an effective channel between a source and a drain by forming an L-shaped trench on a substrate on one side of a control gate, so as to reduce the possibility that the source and the drain are broken down. And an ONO dielectric layer is formed in the L-shaped groove, and the silicon nitride layer is L-shaped, and the current direction is horizontal, so that the ONO dielectric layer is easy to enter the silicon nitride layer in the vertical direction, namely, heat-carrying ions are mainly stored in the silicon nitride layer in the vertical direction, more electrons are stored, the storage capability is enhanced, and the required operating voltage is lower.
In addition, it should be noted that the terms "first", "second", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for representing a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims (7)

1. A method for manufacturing a SONOS memory is characterized by comprising the following steps:
providing a substrate, and forming a control gate on the substrate;
etching the substrate on one side of the control gate to form an L-shaped groove, wherein the L-shaped groove comprises a groove bottom wall and a groove side wall, and one end, close to the control gate, of the groove bottom wall is connected with the bottom end of the groove side wall;
forming an ONO dielectric layer on the L-shaped groove, wherein the ONO dielectric layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer, the first oxide layer and the silicon nitride layer are both of L-shaped structures, the second oxide layer is of a rectangular structure, the first oxide layer covers the side wall of the control gate, the side wall of the groove and part of the area of the bottom wall of the groove, the silicon nitride layer covers the first oxide layer, and the second oxide layer covers the silicon nitride layer; and the number of the first and second groups,
forming a source electrode and a drain electrode on the control gate and the substrate on two sides of the ONO dielectric layer through a source-drain ion implantation process;
before the ONO dielectric layer is formed, the method further comprises the following steps: and carrying out a light doping ion implantation process on the bottom wall of the groove to form a light doping area, wherein the depth of the light doping area is greater than the ion implantation depth of the drain electrode.
2. The method of claim 1, wherein a depth of the L-shaped trench is greater than an ion implantation depth of the source.
3. The method of fabricating the SONOS memory device of claim 1, wherein the specific process of forming the L-shaped trench comprises:
forming a layer of photoresist on the substrate and the control gate;
patterning the photoresist by adopting an exposure and development technology to define an L-shaped groove region, wherein the L-shaped groove region is positioned on one side of the control grid;
etching the substrate of the L-shaped groove region by adopting a dry etching process to form the L-shaped groove;
and removing the photoresist.
4. The method of fabricating the SONOS memory device of claim 1, further comprising a gate oxide layer between the substrate and the control gate.
5. The method of fabricating the SONOS memory device of claim 1, wherein the first oxide layer is formed by an in-situ water vapor method.
6. The method of manufacturing a SONOS memory device of claim 1, wherein the first oxide layer has a thickness of 15A-25A, and the silicon nitride layer has a thickness of 60A-80A.
7. A SONOS memory device, characterized in that it is produced by the method of manufacturing a SONOS memory device according to any one of claims 1 to 6.
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