CN103915442A - Flash memorizer - Google Patents
Flash memorizer Download PDFInfo
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- CN103915442A CN103915442A CN201410138977.XA CN201410138977A CN103915442A CN 103915442 A CN103915442 A CN 103915442A CN 201410138977 A CN201410138977 A CN 201410138977A CN 103915442 A CN103915442 A CN 103915442A
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Abstract
The invention discloses a flash memorizer. The flash memorizer comprises a cylindrical body structure serving as a substrate, wherein the body structure is of an N type silicon structure and comprises a middle portion and two end portions on the two sides of the middle portion, a grid electrode is wrapped on the middle portion in a surrounding mode to form a surrounding grid. The two end portions serve as a source electrode and a drain electrode and respectively comprise a layer of P type doped area. The portion, surrounded by the corresponding P type doped area, of each end portion is led out through a contact line and used for exerting a substrate voltage. A smaller grid length can be obtained, the voltages used for controlling the grid and a floating grid can well control a groove, the percentage of the portion, occupied by a source and drain depletion region through extension, of the total size of the depletion region can be lowered, the short-channel effect can be restrained, threshold voltage drift can be resisted, and reading mistakes of the flash can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of flash memories.
Background technology
For NOR flash memory mnemon, most important what limit that its size continues reduction is the long shortenings of grid.This is mainly to require drain terminal to have certain voltage because channel hot electron (CHE) injects compile mode, and this voltage has a great impact penetrating of source drain terminal, inapplicable for short channel device channel hot electron (CHE) mode.Another one problem is to compare with AND data storage device with NAND, and this has limited the compiling rate of NOR flash memory.According to document " G.Servalli, et al., IEDM Tech.Dig., 35_1,2005 " prediction, the physics limit that the grid length of conventional flash memory structure is dwindled is 130nm.
Existing flash memory cell generally uses the floating boom transistor (Floating Gate Transistor) of polysilicon as information storage medium, its information storage principle be by hot electron inject or FN tunneling effect make electronics as the carrier storage of information the polysilicon at floating boom.When electronic injection and be stored in interval scale information " 0 " in floating boom, when electronics is wiped free of interval scale information " 1 " from floating boom.The transistorized flash memory technology of floating boom exists inherent shortcoming, and 100 nm technology node are following because excessively thin dielectric layer can cause electric leakage, cause the mutual interference of data phase, and occur the problem of chip failure result.The following device of sub-100 nm technology node can produce comparatively serious short-channel effect (Short Channel Effect) in addition, has had influence on the electrology characteristic of memory device, while making its threshold voltage than long raceway groove, drifts about to some extent, causes possible readout error.
Summary of the invention
The object of the invention is to, a kind of flash memories is provided, to reduce the impact of short-channel effect on device electrology characteristic.
For solving the problems of the technologies described above, the invention provides a kind of flash memories, comprising: a columned agent structure as substrate, described agent structure is N-type silicon structure, comprise mid portion and be positioned at two ends of mid portion both sides, be enclosed with grid around mid portion, form and enclose grid; Described two ends, as source electrode and drain electrode, include one deck P type doped region; Described end by P type doped region around part draw by contact wire, for applying underlayer voltage.
Optionally, for described flash memories, the radius of described agent structure is 0.05 μ m～0.5 μ m, and the length of mid portion is 0.1 μ m～2 μ m.
Optionally, for described flash memories, described mid portion is N-type doped region, described end by P type doped region around part be N-type heavily doped region, be doped to phosphorus.
Optionally, for described flash memories, described P type doped region is heavy doping, is doped to boron.
Optionally, for described flash memories, described grid from-inner-to-outer comprises floating boom and control gate, and the material of described floating boom is polysilicon, and thickness is 80nm～100nm, and the material of described control gate is polysilicon, and thickness is 150nm～200nm.
Optionally, for described flash memories, between described mid portion and floating boom, be formed with tunnel oxide, the material of described tunnel oxide is SiO
2, thickness is 5nm-20nm.
Optionally, for described flash memories, be also formed with ONO layer between described floating boom and control gate, thickness is 10nm～50nm.
Compared with prior art, in flash memories provided by the invention, adopt columned substrat structure, grid has been surrounded thereon, drawn by contact wire in described end, for applying underlayer voltage.Compared to existing technology, can have less grid long, use cylindrical-shaped structure can make the voltage of control gate and floating boom can control better raceway groove, the percentage of total depletion region size that drain depletion region, reduction source broadening occupies, suppress short-channel effect, opposing threshold voltage shift, the readout error of minimizing flash memory.Assist thermionic motion by bias voltage is drawn and applied to the substrate of cylindrical flash memories, provide enough energy of crossing oxide layer to complete compiling.
Accompanying drawing explanation
Fig. 1 is the structural representation of the flash memories of the embodiment of the present invention;
Fig. 2 is the cutaway view along A-A ' in Fig. 1;
Fig. 3 is the cutaway view along B-B ' in Fig. 1.
Embodiment
Below in conjunction with schematic diagram, flash memories of the present invention is described in more detail, has wherein represented the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of flash memories is provided, and comprising: a columned agent structure as substrate, described agent structure is N-type silicon structure, comprise mid portion and be positioned at two ends of mid portion both sides, be enclosed with grid around mid portion, form and enclose grid; Described two ends, as source electrode and drain electrode, include one deck P type doped region; Described end by P type doped region around part draw by contact wire, for applying underlayer voltage.
Below enumerate the preferred embodiment of described flash memories, to clearly demonstrate content of the present invention, it will be clear that content of the present invention is not restricted to following examples, other improvement by those of ordinary skills' routine techniques means are also within thought range of the present invention.
Based on above-mentioned thought, the preferred embodiment of flash memories is provided below, please refer to Fig. 1-Fig. 3, the structural representation of the flash memories that Fig. 1 is the embodiment of the present invention; Fig. 2 is the cutaway view along A-A ' in Fig. 1; Fig. 3 is the cutaway view along B-B ' in Fig. 1.
As shown in Figure 1, comprise: a columned agent structure as substrate, described agent structure is N-type silicon structure, comprise mid portion 11 and be positioned at two ends 12 of mid portion 11 both sides, the radius of described main part is 0.05 μ m～0.5 μ m, a for example better selection can be 0.1 μ m, and the length of mid portion 11 is 0.1 μ m～2 μ m.Described mid portion 11 is N-type doped region, is enclosed with grid 2 around mid portion 11, forms and encloses grid; Described two ends 12, as source electrode and drain electrode, include one deck P type doped region 122; Described end 12 by P type doped region 122 around part be N-type heavily doped region 121, be doped to phosphorus.The N-type heavily doped region 121 of described end 12 is drawn by contact wire, for applying underlayer voltage.
Incorporated by reference to Fig. 2, visible described grid 2 is tunnel oxide 21 from the inside to the outside successively, holds the mid portion 11 of agent structure, and the material of described tunnel oxide 21 is SiO
2, thickness is 5nm～20nm, for example in a preferred embodiment, its thickness can be 8nm; What holding tunnel oxide 21 is floating boom 22, and the material of described floating boom 22 is polysilicon, and thickness is 80nm～100nm, and for example in a preferred embodiment, its thickness can be 90nm; Described floating boom 22 is held by ONO layer 23, according to being followed successively by from the inside to the outside SiO
2, nitration case and SiO
2, the thickness of described ONO layer 23 can be 10nm～50nm, for example in a preferred embodiment, and SiO
2, nitration case and SiO
2thickness be followed successively by 3nm, 9nm, 6.5nm; What outermost layer held is control gate 24, and the material of described control gate 24 is polysilicon, and thickness is 150nm～200nm, and for example in a preferred embodiment, its thickness is 175nm.
Please refer to Fig. 3, on N-type heavily doped region 121, holding one deck P type doped region 122, thereby as source electrode and drain electrode, wherein, what adopt here is doped to heavy doping, is doped to boron.
In the present invention, in the time of the read operation of flash memory, control gate adds certain voltage, and this voltage is coupled to floating boom and induces the raceway groove of device, in the time that source drain terminal and substrate add certain voltage, has electric current to pass through device.Lower surface analysis advantage of the present invention: on the one hand, applying after grid voltage and drain voltage, forming vertical electric field, controlling the generation of band-to-band-tunneling (Band to Band Tunneling, BTBT); The BTBT in depletion layer having produced accelerates by tying electric field.Source is owing to also can being applied in certain voltage, thereby makes to tie electric field and vertical electric field is all weakened, causes compiling suppressed.Under the assistance that the hot electron (Band to Band Tunneling Hot Electron, BTBT-HE) band-to-band-tunneling being produced in such back of the body gate bias accelerates, the voltage difference of source drain terminal can be very little, can guarantee that like this device size can dwindle.On the other hand, what can derive is (the present invention omits this process), and the threshold voltage shift that encloses gate device is less than single gate device, illustrates that enclosing gate device can more effectively suppress threshold voltage shift than single gate device.For example enclose the threshold voltage of gate device in the time of the radius a=0.1 of main part μ m, in short ditch and long ditch situation, differ greatly and be about 0.01V, and according to Fig. 5 .16 of document " for the small geometry MOSFET model of VLSI simulation ", the threshold voltage shift of single gate device is approximately 0.1V under the long variation of identical ditch, considerably beyond the threshold voltage shift that encloses gate device.The transistor that the main consuming body part of the present invention (silicon nanowires) is made, control gate and floating boom are all enclosed on silicon nanowires, make the voltage of control gate and floating boom can control better raceway groove, the percentage of total depletion region size that drain depletion region, reduction source broadening occupies, reduces the impact of short-channel effect on device electrology characteristic.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. a flash memories, comprising: a columned agent structure as substrate, and described agent structure is N-type silicon structure, comprises mid portion and is positioned at two ends of mid portion both sides, is enclosed with grid around mid portion, forms and encloses grid; Described two ends, as source electrode and drain electrode, include one deck P type doped region; Described end by P type doped region around part draw by contact wire, for applying underlayer voltage.
2. flash memories as claimed in claim 1, is characterized in that, the radius of described agent structure is 0.05 μ m～0.5 μ m, and the length of mid portion is 0.1 μ m～2 μ m.
3. flash memories as claimed in claim 1, is characterized in that, described mid portion is N-type doped region, described end by P type doped region around part be N-type heavily doped region, be doped to phosphorus.
4. flash memories as claimed in claim 2, is characterized in that, described P type doped region is heavy doping, is doped to boron.
5. flash memories as claimed in claim 1, is characterized in that, described grid from-inner-to-outer comprises floating boom and control gate, the material of described floating boom is polysilicon, thickness is 80nm～100nm, and the material of described control gate is polysilicon, and thickness is 150nm～200nm.
6. flash memories as claimed in claim 5, is characterized in that, between described mid portion and floating boom, is formed with tunnel oxide, and the material of described tunnel oxide is SiO
2, thickness is 5nm-20nm.
7. flash memories as claimed in claim 5, is characterized in that, is also formed with ONO layer between described floating boom and control gate, and thickness is 10nm～50nm.
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| CN201410138977.XA CN103915442B (en) | 2014-04-08 | 2014-04-08 | Flash memories |
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| CN103915442B CN103915442B (en) | 2017-04-05 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332471A (en) * | 2014-11-17 | 2015-02-04 | 上海华力微电子有限公司 | SONOS (silicon oxide nitride oxide silicon) flash memory device and compiling method thereof |
| CN104637537A (en) * | 2014-11-17 | 2015-05-20 | 上海华力微电子有限公司 | Flash memory device and programming method thereof |
| CN104934435A (en) * | 2015-04-22 | 2015-09-23 | 上海华力微电子有限公司 | SONOS double-grid flash memory device and programming and erasing methods thereof |
| CN105742289A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Flash memory structure |
| CN111739944A (en) * | 2020-07-07 | 2020-10-02 | 上海大学 | Fully-enclosed gate synaptic transistor, preparation method and circuit connection method |
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| US5614746A (en) * | 1994-11-28 | 1997-03-25 | United Microelectronics Corporation | Structure and process of manufacture of split gate flash memory cell |
| KR100620549B1 (en) * | 2004-12-29 | 2006-09-13 | 학교법인고려중앙학원 | Manufacturing Method of Nano-Floating Gate Memory devices using Nanowires |
| CN102280492A (en) * | 2010-06-10 | 2011-12-14 | 日本优尼山帝斯电子株式会社 | Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory |
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Patent Citations (3)
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| US5614746A (en) * | 1994-11-28 | 1997-03-25 | United Microelectronics Corporation | Structure and process of manufacture of split gate flash memory cell |
| KR100620549B1 (en) * | 2004-12-29 | 2006-09-13 | 학교법인고려중앙학원 | Manufacturing Method of Nano-Floating Gate Memory devices using Nanowires |
| CN102280492A (en) * | 2010-06-10 | 2011-12-14 | 日本优尼山帝斯电子株式会社 | Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332471A (en) * | 2014-11-17 | 2015-02-04 | 上海华力微电子有限公司 | SONOS (silicon oxide nitride oxide silicon) flash memory device and compiling method thereof |
| CN104637537A (en) * | 2014-11-17 | 2015-05-20 | 上海华力微电子有限公司 | Flash memory device and programming method thereof |
| CN104332471B (en) * | 2014-11-17 | 2017-06-23 | 上海华力微电子有限公司 | A kind of SONOS flush memory devices and its Compilation Method |
| CN104637537B (en) * | 2014-11-17 | 2019-02-19 | 上海华力微电子有限公司 | A kind of flush memory device and its programmed method |
| CN104934435A (en) * | 2015-04-22 | 2015-09-23 | 上海华力微电子有限公司 | SONOS double-grid flash memory device and programming and erasing methods thereof |
| CN105742289A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Flash memory structure |
| CN111739944A (en) * | 2020-07-07 | 2020-10-02 | 上海大学 | Fully-enclosed gate synaptic transistor, preparation method and circuit connection method |
| CN111739944B (en) * | 2020-07-07 | 2021-06-01 | 上海大学 | Fully-enclosed gate synaptic transistor, preparation method and circuit connection method |
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| CN103915442B (en) | 2017-04-05 |
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