CN111739944B - Fully-enclosed gate synaptic transistor, preparation method and circuit connection method - Google Patents
Fully-enclosed gate synaptic transistor, preparation method and circuit connection method Download PDFInfo
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- CN111739944B CN111739944B CN202010644322.5A CN202010644322A CN111739944B CN 111739944 B CN111739944 B CN 111739944B CN 202010644322 A CN202010644322 A CN 202010644322A CN 111739944 B CN111739944 B CN 111739944B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
The invention relates to a fully-enclosed gate synaptic transistor, a preparation method and a circuit connection method, wherein the fully-enclosed gate synaptic transistor comprises an active layer, an insulating layer, a gate electrode, a source electrode and a drain electrode; the active layer is a cylinder, the outer side of the active layer is sequentially wrapped by the insulating layer and the gate electrode, one end of the active layer is provided with a source electrode, the other end of the active layer is provided with a drain electrode, the source electrode and the drain electrode are cylinders, the diameter of the bottom surface of the source electrode and the diameter of the bottom surface of the drain electrode are smaller than that of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are coaxially arranged. The invention enables the grid voltage to control the channel current from all directions, improves the control capability of the grid electrode and reduces the power consumption of the device.
Description
Technical Field
The invention relates to the technical field of synaptic transistors, in particular to a fully-surrounded gate synaptic transistor, a preparation method and a circuit connection method.
Background
With the rapid development of information technology, the data volume increases explosively, and the processing capacity for huge data volume also begins to encounter a bottleneck. Traditional computers based on von neumann architecture exhibit powerful computing power in dealing with problems of clear logic and clear data structure, but for some problems of fuzzy logic structure and huge data size, such as processing of images and videos, the traditional computers are very inefficient and consume huge energy. Inspired by the human brain, the research of the brain-like computer system has gained wide attention. The development of high performance synaptic transistors is particularly important in the manufacture of brain-like computers. At present, all traditional synaptic transistors are of a laminated structure based on Thin Film Transistor technology (Thin Film Transistor TFT), the control capability of a grid electrode on channel current is weak, and a series of problems of large channel leakage current, small on-off current ratio, large device power consumption and the like caused by the weak control capability cause the performance of synaptic Transistor devices to be low, and meanwhile, the mass mobility of an insulating layer in the traditional synaptic transistors is insufficient, and the synaptic characteristics need to be improved.
Disclosure of Invention
Based on this, an object of the present invention is to provide a fully-wrapped-gate synaptic transistor, a method for manufacturing the same, and a method for connecting a circuit, in which a gate surrounds an insulating layer and an active layer, so that a gate voltage can control a channel current from various directions, thereby improving a control capability of the gate electrode and reducing power consumption of a device.
In order to achieve the purpose, the invention provides the following scheme:
a fully-wrapped gate synaptic transistor comprises an active layer, an insulating layer, a gate electrode, a source electrode and a drain electrode; the active layer is a cylinder, the outer side of the active layer is sequentially wrapped by the insulating layer and the gate electrode, one end of the active layer is provided with a source electrode, the other end of the active layer is provided with a drain electrode, the source electrode and the drain electrode are cylinders, the diameter of the bottom surface of the source electrode and the diameter of the bottom surface of the drain electrode are smaller than that of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are coaxially arranged.
Optionally, the insulating layer material comprises one or any number of polyethylene oxide (PEO), Polyacrylonitrile (PAN), polyvinylidene fluoride (PVDF), polymethyl methacrylate (PMMA), polypropylene oxide (PPO), polyvinylidene chloride (PVDC), perovskite type, NASICON type, LISICON type and garnet type.
Optionally, the height of the active layer is 10-100 nm.
Optionally, the gate electrode has a height of 30 to 500nm and a thickness of 5 to 50 nm.
Optionally, the height of each of the source electrode and the drain electrode is 10-50 nm.
The invention also provides a preparation method of the fully-wrapped-gate synaptic transistor, which comprises the following steps:
depositing a source electrode on a substrate, wherein the source electrode is a cylinder;
depositing a first intermetallic insulator layer on the source electrode, the first intermetallic insulator layer having a height greater than or equal to a height of the source electrode;
providing a cylindrical gate electrode on the first intermetallic insulator layer, the gate electrode being provided coaxially with the source electrode;
an insulating layer is arranged on the inner side of the cylindrical gate electrode, and the insulating layer is cylindrical;
filling an active layer material into the insulating layer to form an active layer, wherein the active layer is a cylinder;
and a drain electrode is arranged on the active layer, the drain electrode is a cylinder, the diameters of the bottom surfaces of the source electrode and the drain electrode are smaller than that of the bottom surface of the active layer, and the drain electrode and the gate electrode are coaxially arranged.
Optionally, the providing a cylindrical gate electrode on the first intermetallic insulator layer specifically includes: and depositing a gate electrode material on the first intermetallic insulator layer to form a cylinder, and etching the cylinder to form the cylindrical gate electrode.
Optionally, the disposing an insulating layer inside the cylindrical gate electrode specifically includes: and arranging an insulating layer on the inner side of the gate electrode by adopting an electrostatic spinning process.
Optionally, the first intermetallic insulator layer comprises any one of borophosphosilicate glass, silicon dioxide and silicon nitride.
The invention also provides a circuit connection method for the fully-surrounded gate synaptic transistor, which depends on the preparation method of the fully-surrounded gate synaptic transistor, and the method comprises the following steps:
depositing a connecting line of the source electrode and the source electrode on a substrate according to a preset patterned connecting line of the source electrode and the source electrode; the number of the source electrodes is more than 1;
depositing a first intermetallic insulator layer on the source electrode and the connection line of the source electrode;
providing a cylindrical gate electrode on the first intermetallic insulator layer;
depositing a connection line of the gate electrode on the first intermetallic insulator layer according to a preset patterned connection line of the gate electrode;
depositing a second intermetallic insulator layer on the first intermetallic insulator layer, the second intermetallic insulator layer having a height equal to a height of the gate electrode;
sequentially arranging an insulating layer and an active layer on the inner side of the cylindrical gate electrode;
providing a drain electrode on the active layer;
depositing a third intermetallic insulator layer on the second intermetallic insulator layer, the third intermetallic insulator layer having a height less than the height of the drain electrode;
and depositing a connecting line of the drain electrode on the third intermetallic insulator layer according to a preset patterned connecting line of the drain electrode.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention aims to provide a fully-surrounded gate synaptic transistor, a preparation method and a circuit connection method.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a perspective view of a fully wrapped-around gate synaptic transistor according to one embodiment of the present invention;
FIG. 2 is a front view of a fully wrapped around gate synaptic transistor according to one embodiment of the present invention;
FIG. 3 is a cross-sectional view of a fully wrapped-around gate synapse transistor in accordance with an embodiment of the present invention;
FIG. 4 is a diagram illustrating a structure of a conventional stacked synapse transistor based on a bottom-gate TFT in accordance with an embodiment of the present invention;
FIG. 5 is a flow chart illustrating a method for fabricating a fully wrapped-around gate synaptic transistor according to an embodiment of the present invention;
FIG. 6 is a flow chart illustrating a circuit connection method for fully-wrapped-around gate synapse transistors in accordance with an embodiment of the present invention;
FIG. 7 is a flow chart of a connection process for fully encompassing a synapse transistor as a NAND gate in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram of a fully-wrapped synapse transistor connected as a NAND gate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a fully-surrounded gate synaptic transistor, a preparation method and a circuit connection method.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
FIGS. 1-3 illustrate a fully wrapped-around gate synapse transistor structure as shown in FIGS. 1-3, comprising an active layer, an insulating layer, a gate electrode, a source electrode, and a drain electrode; the active layer is a cylinder, the outer side of the active layer is sequentially wrapped by the insulating layer and the gate electrode, one end of the active layer is provided with a source electrode, the other end of the active layer is provided with a drain electrode, the source electrode and the drain electrode are cylinders, the diameter of the bottom surface of the source electrode and the diameter of the bottom surface of the drain electrode are smaller than that of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are coaxially arranged.
The gate electrode material comprises one or more of composite metals of Al, Au, Ag, Mo, W, Cu and Fe, the height of the gate electrode is 30-500 nm, and the thickness of the gate electrode is 5-50 nm.
The insulating layer material comprises one or more of polyethylene oxide (PEO), Polyacrylonitrile (PAN), polyvinylidene fluoride (PVDF), polymethyl methacrylate (PMMA), polypropylene oxide (PPO), polyvinylidene chloride (PVDC), perovskite type, NASICON type, LISICON type and garnet type, and the thickness is 10-100 nm.
The active layer material comprises one or more of SnSiO, SnZrO, InSnBaO, InZnO and InGaN, and the thickness of the active layer material is 10-100 nm.
The material of the source electrode and the drain electrode comprises one or more of Al, Au, Ag, Mo, W, Cu and Fe.
The height of the source electrode and the height of the drain electrode are both 10-50 nm.
The invention also provides a preparation method of the fully-wrapped-gate synaptic transistor, as shown in fig. 5, the method comprises the following steps:
step 101: depositing a source electrode on the substrate, wherein the source electrode is a cylinder.
Wherein, step 101 specifically includes: patterned source electrodes and interconnect lines are deposited on a substrate.
Step 102: depositing a first intermetallic insulator layer on the source electrode, the first intermetallic insulator layer having a height greater than or equal to a height of the source electrode. The insulation of the first intermetallic insulator layer is good.
Step 103: a cylindrical gate electrode is provided on the first metal-to-metal insulator layer, and the gate electrode is provided coaxially with the source electrode.
Wherein, step 103 specifically comprises: depositing a patterned metal cylinder on the first intermetallic insulator layer for manufacturing a gate electrode, wherein the metal cylinder is required to be deposited right above the source electrode, etching the interior of the metal cylinder for manufacturing the gate electrode completely through reactive ion etching to form a cylindrical gate electrode, and etching the first intermetallic insulator layer on the lower bottom surface of the cylinder to make the source electrode show leakage.
Step 104: an insulating layer is arranged on the inner side of the cylindrical gate electrode, and the insulating layer is cylindrical;
wherein, step 104 specifically includes: and manufacturing an insulating layer formed by nanowires of the solid electrolyte on the inner side of the gate electrode by adopting an electrostatic spinning process.
Step 105: and filling an active layer material in the insulating layer to form an active layer, wherein the active layer is a cylinder.
Wherein, step 105 specifically comprises: and sputtering an active layer material by a sputtering method to fill the inside of the gate electrode.
Step 106: and a drain electrode is arranged on the active layer, the drain electrode is a cylinder, the diameters of the bottom surfaces of the source electrode and the drain electrode are smaller than that of the bottom surface of the active layer, and the drain electrode and the gate electrode are coaxially arranged. The drain electrode is fabricated by evaporation.
The invention also provides a circuit connection method for a fully-wrapped-gate synapse transistor, as shown in FIG. 6, the method comprising:
step 201: depositing a connecting line of the source electrode and the source electrode on a substrate according to a preset patterned connecting line of the source electrode and the source electrode; the number of the source electrodes is greater than 1.
Before step 201, the method specifically includes: and selecting a substrate with a proper size according to the size of the manufactured fully-surrounded gate synaptic transistor, and cleaning and drying the substrate.
Step 201 specifically includes preparing a patterned source electrode on the substrate by thermal evaporation or sputtering, and connecting the source electrodes according to the circuit function, and the connecting wires are also prepared by sputtering or thermal evaporation.
Step 202: depositing a first intermetallic insulator layer on the source electrode and the connection line of the source electrode.
Wherein, step 202 specifically includes: the first intermetal insulator layer is prepared by a chemical vapor deposition or sputtering method, in order to separate the source electrode and the source electrode connection line prepared in step 201 from the gate electrode to be prepared in the following step.
Step 203: a cylindrical gate electrode is provided on the first intermetallic insulator layer.
Wherein, step 203 specifically comprises: and preparing a metal cylinder with the diameter of 50-500 nm and the height of 30-500 nm on the first metal insulator layer by a thermal evaporation or sputtering method, wherein the metal cylinder is coaxial with the source electrode. The method comprises the steps of firstly etching the interior of a metal cylinder completely by a reactive ion etching method to form a metal cylinder with the thickness of 5-50 nm, and then etching a first intermetallic insulator layer in the cylinder to expose a source electrode, so that a gate electrode is manufactured.
Step 204: and depositing the connecting line of the gate electrode on the first intermetallic insulator layer according to a preset patterned connecting line of the gate electrode.
Wherein, step 204 specifically includes: and manufacturing a connecting wire of the gate electrode by using a thermal evaporation or sputtering method, and connecting the gate electrodes according to the circuit function requirement.
Step 205: depositing a second intermetallic insulator layer on the first intermetallic insulator layer, the second intermetallic insulator layer having a height equal to a height of the gate electrode.
Wherein, step 205 specifically includes: the second intermetallic insulator layer is prepared by using a chemical vapor deposition or sputtering method, so that the gate electrode and the gate electrode metal connecting wire are buried to facilitate the manufacture of the subsequent step.
Step 206: an insulating layer and an active layer are sequentially provided inside the cylindrical gate electrode.
Wherein, step 206 specifically comprises: and then, manufacturing a solid electrolyte nanowire thin layer on the inner side of the cylindrical grid by using an electrostatic spinning process to serve as an insulating layer.
And sputtering an active layer material on the basis of the manufactured insulating layer to fill the cylinder of the gate electrode, so that the active layer is manufactured.
Step 207: a drain electrode is disposed on the active layer.
Wherein step 207 specifically comprises: the drain electrode is fabricated using a method of sputtering or thermally evaporating metal.
Step 208: depositing a third intermetallic insulator layer on the second intermetallic insulator layer, the third intermetallic insulator layer having a height less than a height of the drain electrode.
Wherein, step 208 specifically includes: and preparing a third intermetallic insulator layer by using a chemical vapor deposition or sputtering method, and burying the upper surfaces of the gate electrode, the insulating layer and the active layer, but exposing the upper half part of the drain electrode to facilitate the connection of a circuit.
Step 209: and depositing a connecting line of the drain electrode on the third intermetallic insulator layer according to a preset patterned connecting line of the drain electrode.
Wherein, step 209 specifically includes: and (3) preparing a metal connecting wire of the drain electrode by using a thermal evaporation or sputtering method, and connecting the exposed drain electrodes in the step 208 according to the circuit function requirement.
The fully wrapped synaptic transistor device is completed by this step, and the circuit with certain specific functions suitable for the device structure of the present invention is also completed.
The materials of the connecting line of the source electrode, the connecting line of the gate electrode and the connecting line of the drain electrode include: one or more of Al, Au, Ag, Mo, W, Cu and Fe, the thickness of the composite metal is 10-30 nm, and the width of the composite metal is 10-30 nm.
The material of the first intermetallic insulator layer, the second intermetallic insulator layer and the third intermetallic insulator layer includes any one of borophosphosilicate glass, silicon dioxide and silicon nitride.
Wherein, the sputtering and the etching methods are carried out under the condition of corresponding masks.
In the fully-wrapped gate structure synaptic transistor of the invention, the gate (gate electrode) wraps the insulating layer and the insulating layer in a fully-wrapped shape, so that many defects of the traditional synaptic transistor based on a bottom gate TFT structure or a top gate TFT structure are overcome, and the traditional stacked synaptic transistor based on the bottom gate TFT structure is shown in FIG. 4. In the traditional 'laminated' structure synaptic transistor, the gate voltage can only control the channel current from one direction, and the control capability of the gate voltage on the channel current is weaker, so that the channel leakage current of the synaptic transistor device is very large, the power consumption of the device is very high, and the stability and the efficiency of the device are greatly reduced. Meanwhile, the fully-surrounded gate synaptic transistor insulating layer disclosed by the invention is used for preparing the solid electrolyte nanowire by adopting an electrostatic spinning process, and compared with a traditional synaptic transistor device, the nanowire structure has higher mass mobility, the electric double layer effect is more obvious, and the synaptic property is more prominent.
Aiming at the structure and the preparation method of the fully-wrapped gate synaptic transistor device, the invention also provides a corresponding circuit interconnection process, so that independent single devices can be connected to realize specific functions. The fully-wrapped gate synaptic transistor structure and the preparation method thereof and the corresponding circuit interconnection process are compatible with the existing integrated circuit planarization process.
FIG. 7 is a process flow diagram of a NAND gate circuit connected according to the above-described circuit connection method for fully-surrounding gate synaptic transistors, and FIG. 8 is a schematic structural diagram of a fully-surrounding gate synaptic transistor connected NAND gate circuit.
The manufacturing process of the NAND gate circuit connected by the fully-enclosed synapse transistor comprises the following steps:
selecting a glass substrate with a proper size, sequentially cleaning the glass substrate with acetone, alcohol and deionized water, and drying the glass substrate for later use.
Two cylindrical copper source electrodes with the height of 30nm and the diameter of 60nm are prepared on a cleaned glass substrate by a sputtering method through a mask (note: all the sputtering, photoetching and etching steps in the scheme use corresponding masks, and the masks are omitted below for convenience of description).
A copper wire with a height of 10nm and a width of 20nm was prepared by sputtering, and two source electrodes were connected.
And preparing a first intermetallic insulator layer by a chemical vapor deposition method, wherein the material of the first intermetallic insulator layer is Boron Phosphorus Silicon Glass (BPSG) with the thickness of 50nm, and the purpose is to separate the source electrode prepared in the step and the metal connection from the gate electrode prepared in the following step.
On the first intermetallic insulator layer, a small metal copper cylinder with the diameter of 200nm and the height of 300nm is prepared by a sputtering method and is used for manufacturing a gate electrode, and the small metal copper cylinder is aligned with the center of a source electrode.
The method comprises the steps of firstly etching the inside of a small metal copper cylinder completely by a reactive ion etching method to form a small metal cylinder with the thickness of 20nm, and then etching a first intermetallic insulator layer below the small cylinder to expose a source electrode so as to be convenient for subsequent connection with an active layer, so that the gate electrode is manufactured.
Copper wires with the height of 10nm and the width of 20nm are manufactured by a sputtering method, and two grids are respectively led out of ports to serve as input ports input1 and input 2.
And preparing a second intermetallic insulator layer with the height of 300nm by using a chemical vapor deposition method, wherein the material is also boron-phosphorus-silicon glass, and the purpose is to bury the gate electrode and the gate electrode metal connecting wire so as to facilitate the manufacture of the subsequent steps.
And then, a solid electrolyte nanowire thin layer is manufactured on the inner side of the cylindrical gate electrode by an electrostatic spinning process to serve as an insulating layer, garnet-type solid electrolyte is selected as the solid electrolyte material, and the thickness of the insulating layer is 30 nm.
Sputtering InZnO to fill the small cylinder of the grid electrode, thus completing the manufacturing of the active layer.
Two cylindrical copper drain electrodes with a height of 30nm and a diameter of 60nm were fabricated using a sputtering method.
And preparing a third intermetallic insulator layer by using a chemical vapor deposition borophosphosilicate glass method, burying the upper surfaces of the grid electrode, the insulating layer and the active layer, but exposing the upper half part of the drain electrode to facilitate the connection of a circuit, wherein the thickness of the third intermetallic insulator layer is controlled to be 15 nm. Thus, the independent fully-enclosed synaptic transistor device is prepared.
Finally, a sputtering method is used for preparing a copper wire with the height of 10nm and the width of 20nm, two exposed drain electrodes are respectively led out of two interfaces, wherein the first interface is used as VDDAnd a ground connection port, the second interface being an output port, as shown in fig. 8. Finally, the circuit of the device structure suitable for the invention, which takes the NAND gate as an example, is connected.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A fully-wrapped-gate synaptic transistor comprising an active layer, an insulating layer, a gate electrode, a source electrode, and a drain electrode; the active layer is a cylinder, the outer side of the active layer is sequentially wrapped by the insulating layer and the gate electrode, one end of the active layer is provided with a source electrode, the other end of the active layer is provided with a drain electrode, the source electrode and the drain electrode are cylinders, the diameter of the bottom surface of the source electrode and the diameter of the bottom surface of the drain electrode are smaller than that of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are coaxially arranged.
2. The fully-wrapped-gate synaptic transistor of claim 1, wherein the insulating layer material comprises one or any of polyethylene oxide, polyacrylonitrile, polyvinylidene fluoride, polymethyl methacrylate, polypropylene oxide, polyvinylidene chloride, perovskite type, NASICON type, LISICON type, and garnet type.
3. The fully-wrapped-gate synaptic transistor of claim 1, wherein the height of the active layer is between 10nm and 100 nm.
4. The fully-wrapped-gate synaptic transistor according to claim 1, wherein the gate electrode has a height of 30-500 nm and a thickness of 5-50 nm.
5. The fully-wrapped-gate synaptic transistor according to claim 1, wherein the height of each of the source electrode and the drain electrode is 10-50 nm.
6. A method for preparing a fully-wrapped-gate synaptic transistor, the method comprising:
depositing a source electrode on a substrate, wherein the source electrode is a cylinder;
depositing a first intermetallic insulator layer on the source electrode, the first intermetallic insulator layer having a height greater than or equal to a height of the source electrode;
providing a cylindrical gate electrode on the first intermetallic insulator layer, the gate electrode being provided coaxially with the source electrode;
an insulating layer is arranged on the inner side of the cylindrical gate electrode, and the insulating layer is cylindrical;
filling an active layer material into the insulating layer to form an active layer, wherein the active layer is a cylinder;
and a drain electrode is arranged on the active layer, the drain electrode is a cylinder, the diameters of the bottom surfaces of the source electrode and the drain electrode are smaller than that of the bottom surface of the active layer, and the drain electrode and the gate electrode are coaxially arranged.
7. The method according to claim 6, wherein the step of providing a cylindrical gate electrode on the first intermetallic insulator layer comprises: and depositing a gate electrode material on the first intermetallic insulator layer to form a cylinder, and etching the cylinder to form the cylindrical gate electrode.
8. The method according to claim 6, wherein the step of providing an insulating layer inside the cylindrical gate electrode comprises: and arranging an insulating layer on the inner side of the gate electrode by adopting an electrostatic spinning process.
9. The method of claim 6, wherein the first inter-metal insulator layer comprises any one of borophosphosilicate glass, silicon dioxide, and silicon nitride.
10. A circuit connection method for a fully-wrapped-gate synaptic transistor, in accordance with a method of manufacturing a fully-wrapped-gate synaptic transistor according to any one of claims 6-9, the method comprising:
depositing a connecting line of the source electrode and the source electrode on a substrate according to a preset patterned connecting line of the source electrode and the source electrode; the number of the source electrodes is more than 1;
depositing a first intermetallic insulator layer on the source electrode and the connection line of the source electrode; the height of the first intermetallic insulator layer is greater than that of the connection line of the source electrode;
providing a cylindrical gate electrode on the first intermetallic insulator layer;
depositing a connection line of the gate electrode on the first intermetallic insulator layer according to a preset patterned connection line of the gate electrode;
depositing a second intermetallic insulator layer on the first intermetallic insulator layer, the second intermetallic insulator layer having a height equal to a height of the gate electrode;
sequentially arranging an insulating layer and an active layer on the inner side of the cylindrical gate electrode;
providing a drain electrode on the active layer;
depositing a third intermetallic insulator layer on the second intermetallic insulator layer, the third intermetallic insulator layer having a height less than the height of the drain electrode;
and depositing a connecting line of the drain electrode on the third intermetallic insulator layer according to a preset patterned connecting line of the drain electrode.
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