TWI661562B - Neuron transistor and the method for preparing the same - Google Patents

Abstract

The invention provides a neuron electric crystal structure and a preparation method thereof. The structure includes: a semiconductor substrate; an insulating layer on the semiconductor substrate; a semiconductor channel on the insulating layer using a two-dimensional semiconductor material; Gate potential adjustment structure on semiconductor channel; Nano carbon tube gate array above the gate potential adjustment structure; Source contact electrodes respectively located at both ends of the nano carbon tube gate array and respectively connected to the semiconductor channel And drain contact electrodes; and a side wall isolation structure between the nano-carbon tube gate array and gate potential adjustment structure and the source contact electrode and the drain contact electrode. The neuron electrical crystal structure of the present invention uses two-dimensional semiconductor material as a channel and a metal nano-carbon tube gate array as a multi-input gate electrode, which makes it easier to control the channel charge, significantly reduces the gate size, and is conducive to solving the problem. Many problems caused by the increase in the number of transistors and interconnections in the circuit.

Description

   Neuron electric crystal structure and preparation method thereof   

The invention relates to the technical field of integrated circuits, in particular to a neuron electric crystal structure and a preparation method thereof.

In order to solve the problem of increasing the component density on the wafer, a neuron MOS transistor (Neuron MOSFET, abbreviated as neuMOS or vMOS) with a floating gate connected to a capacitor at the input end is caused by its simple structure and special functions. Increasing attention.

Neural components are functionally equivalent to nerve cells (neurons) that make up information in a human brain, eyes, etc. using circuits to conduct information. Specifically, a neural component can weight multiple input signals separately, and when the addition result of the weighted signals reaches a threshold, output a predetermined signal. This method of weighting input signals of neural components is realized by a neuron transistor therein. The neuron transistor has a gate structure of multiple input electrodes. When the sum of the input voltages of the multiple input gates reaches a predetermined value, Only when the source and drain are connected. The weighting method of the neural components is equivalent to the synapse of the nerve cell, which can be composed of a resistor and a field effect transistor, and the neuron crystal is equivalent to the cell body of the nerve cell. The summation process of the neuron transistor on the gate can use the voltage mode of the capacitive coupling effect. There is no current other than the capacitor charge and discharge current, so there is basically no power consumption.

With the development of integrated circuits and the improvement of their integration, the traditional Crystal-integrated silicon integrated circuits have encountered many difficult and urgent problems, and neuron MOS transistors, as a unit transistor with powerful functions, have increased the number of transistors and interconnections in integrated circuits. The problems it provides provide an effective way.

In view of the foregoing prior art, an object of the present invention is to provide a neuron electric crystal structure and a preparation method thereof, which are used to solve various problems in the prior art.

In order to achieve the above object and other related objects, the present invention provides a neuron transistor structure, including: a semiconductor substrate; an insulating layer on the semiconductor substrate; a semiconductor channel on the insulating layer, using a two-dimensional semiconductor material A gate potential adjustment structure, which is located on the semiconductor channel, and includes a first dielectric layer, a potential adjustment layer, and a second dielectric layer in order from bottom to top; a nano-carbon tube gate array located on the gate potential adjustment structure Comprising a plurality of nano carbon tubes and a plurality of gate contact electrodes respectively leading out of the plurality of nano carbon tubes; a source contact electrode and a drain contact electrode are respectively located at two ends of the nano carbon tube gate array and are respectively connected with The semiconductor channel is connected.

Optionally, between the source contact electrode and the nano carbon tube gate array and the gate potential adjustment structure, and between the drain contact electrode and the nano carbon tube gate array and the gate potential adjustment structure, With side wall isolation structure.

Optionally, the semiconductor substrate is a silicon substrate.

Optionally, the insulating layer is silicon oxide.

Optionally, the two-dimensional semiconductor material used for the semiconductor channel is MoS ₂ , WS ₂ , ReS ₂ or SnO.

Optionally, in the gate potential adjustment structure, materials of the first dielectric layer and the second dielectric layer are silicon oxide.

Optionally, in the gate potential adjustment structure, a material of the potential adjustment layer is polycrystalline silicon.

Optionally, the thickness of the gate potential adjusting structure is 2-100 nm.

Optionally, the nano carbon tube gate array adopts a metallic nano carbon tube, and each nano carbon tube has a diameter of 0.75 to 3 nm and a length of 100 nm to 50 μm.

Optionally, a surface of a plurality of nano carbon tubes of the nano carbon tube gate array is covered with a passivation layer.

Optionally, the number of the carbon nanotubes is three or more.

In order to achieve the above object and other related objects, the present invention also provides a method for preparing a neuron electrical crystal structure, including the following steps: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; and adopting two-dimensional on the insulating layer A semiconductor material forms a semiconductor channel; a gate potential adjustment structure is formed on the semiconductor channel, and the gate potential adjustment structure includes a first dielectric layer, a potential adjustment layer, and a second dielectric layer in order from bottom to top; A plurality of nano carbon tubes forming a nano carbon tube gate array on the adjustment structure; a passivation layer is covered on the plurality of nano carbon tube gates; openings are respectively formed at both ends of the nano carbon tube gate array to expose the semiconductor Top of the channel A side wall isolation structure is formed on a side of the opening immediately adjacent to the nano-carbon gate array; a conductive material is filled in the opening to form a source contact electrode and a drain contact electrode respectively connected to the semiconductor channel; and Forming a plurality of gate contact electrodes respectively leading out the plurality of nano carbon tubes; wherein the side wall isolation structure enables the nano carbon tube gate array and the gate potential adjustment structure to be in contact with the source contact electrodes and The drain contact electrodes are separated.

Optionally, the method for forming a plurality of gate contact electrodes includes the steps of: etching the passivation layer to form a plurality of through holes to respectively expose the plurality of nano carbon tubes, and then filling the through holes with a conductive material to form a plurality of through holes. The brake contacts the electrodes.

As mentioned above, the neuron electronic crystal structure and the preparation method thereof have the following beneficial effects: The neuron electronic crystal structure of the present invention replaces the traditional silicon-doped channel with a two-dimensional semiconductor material channel, making the channel charge easier to control The use of a metal nano carbon tube gate array as a multi-input gate electrode of a neuron transistor can significantly reduce the size of the gate electrode. Compared with the existing neuron MOS transistor, the neuron transistor of the present invention enables device performance to be obtained. Further improvement and further reduction in device size are conducive to solving many problems caused by the increase in the number of transistors and interconnection lines in integrated circuits.

100‧‧‧ semiconductor substrate

200‧‧‧ Insulation

300‧‧‧Semiconductor Channel

400‧‧‧Gate potential adjustment structure

401‧‧‧first dielectric layer

402‧‧‧Second dielectric layer

403‧‧‧Potential adjustment layer

500‧‧‧nanometer carbon tube gate array

501‧‧‧nanometer carbon tube

502‧‧‧Brake contact electrode

503‧‧‧ passivation layer

600‧‧‧ source contact electrode

700‧‧‧ Drain contact electrode

800‧‧‧Side wall isolation structure

FIG. 1 is a schematic diagram showing a structure of a neuron electrical crystal according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a neuron electric crystal according to an embodiment of the present invention.

Figures 3a-3i are schematic diagrams illustrating a process for preparing a neuron's electronic crystal structure according to an embodiment of the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the illustrations provided in the following embodiments are only a schematic illustration of the basic idea of the present invention, and the drawings only show the components related to the present invention and not the number, shape and For size drawing, the type, quantity, and proportion of each component can be changed at will in actual implementation, and the component layout type may be more complicated.

This embodiment will provide a neuron transistor crystal structure using a two-dimensional semiconductor material as a channel and a metal nanocarbon tube gate array as a multi-input gate electrode. A potential adjustment layer is provided between the channel and the gate array, and the potential is changed by changing the potential. Adjust the state of the layer to adjust the channel potential. Compared with the existing neuron MOS transistor, the channel charge is easier to control and the gate size can be significantly reduced, which is conducive to solving many problems caused by the increase in the number of transistors and interconnection lines in integrated circuits.

Please refer to FIG. 1. A neuron transistor structure provided in this embodiment includes: Including: semiconductor substrate 100; insulating layer 200 on the semiconductor substrate 100; semiconductor channel 300 on the insulating layer 200 using a two-dimensional semiconductor material; gate potential adjustment structure 400 on the semiconductor channel 300 , From the bottom to the top, a first dielectric layer 401, a potential adjustment layer 403, and a second dielectric layer 402 are sequentially included; a nano carbon tube gate array 500 is located on the gate potential adjustment structure 400 and includes a plurality of nano carbons; A tube 501 and a plurality of gate contact electrodes 502 respectively leading to the plurality of nano carbon tubes 501; a source contact electrode 600 and a drain contact electrode 700 are respectively located at two ends of the nano carbon tube gate array 500, and are respectively connected with The semiconductor channel 300 is connected.

In this embodiment, between the source contact electrode 600 and the nano carbon tube gate array 500 and the gate potential adjustment structure 400, and between the drain contact electrode 700 and the nano carbon tube gate array 500 and the gate Side wall isolation structures 800 are respectively provided between the potential adjustment structures 400.

In this embodiment, the semiconductor substrate 100 may be a silicon substrate or other suitable semiconductor material substrate. The insulating layer 200 may be silicon oxide or other suitable insulating materials.

In this embodiment, the two-dimensional semiconductor material used for the semiconductor channel 300 may be materials such as MoS ₂ , WS ₂ , ReS ₂ , and SnO.

In this embodiment, the gate potential adjustment structure 400 adopts a “sandwich” structure in which a potential adjustment layer is sandwiched between two insulating materials, including a first dielectric layer 401, a potential adjustment layer 403, and a second dielectric layer 402. A material of the first dielectric layer 401 and the second dielectric layer 402 is an insulating material, and may be, for example, silicon oxide. The potential adjustment layer 403 is used to adjust the channel potential. The material may be polycrystalline silicon or other materials suitable for adjusting the potential. Specifically, the brake The thickness of the bit adjustment structure 400 may be 2-100 nm.

In this embodiment, the nano carbon tube gate array 500 uses a metal nano carbon tube. The diameter of each nano carbon tube 501 is 0.75 to 3 nm, and the length is 100 nm to 50 μm. Since a neuron transistor usually includes at least three input electrodes, in this embodiment, the nano carbon tube gate array 500 is used as a multi-input gate electrode of a neuron transistor, and the number of the nano carbon tube 501 should be three. More than one, specifically, a larger number of nano carbon tubes 501 can be designed and arranged according to actual needs.

In this embodiment, the surface of the plurality of nano carbon tubes 501 of the nano carbon tube gate array 500 is covered with a passivation layer 503. Specifically, the material of the passivation layer 503 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the passivation layer 503 can be designed according to actual needs, and the surface of the nano carbon tube 501 should be completely wrapped to cover the nano carbon tube 501 from the surrounding environment.

Figure 2 is a schematic diagram of the structure of a neuron's electric crystal provided in this embodiment. The source contact electrode is connected to Vss, the drain contact electrode is connected to Vdd, and the two ends of the semiconductor channel are connected to each other. , Vg2, Vg3, ... Vgn, a potential adjustment layer is provided between the gate electrode array and the semiconductor channel, and the potential of the semiconductor channel can be adjusted by changing the state of the potential adjustment layer, thereby achieving the weighting function of the neuron transistor on the gate .

The method for preparing the neuron crystal structure provided in this embodiment is further described in detail below with reference to the accompanying drawings.

Referring to FIGS. 3a to 3i, this embodiment provides a method for preparing a neuron's electronic crystal structure, which includes the following steps: First, as shown in FIG. 3a, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be any suitable semiconductor material, such as a silicon substrate.

As shown in FIG. 3B, an insulating layer 200 is formed on the semiconductor substrate 100. The insulating layer 200 may be silicon oxide or other suitable insulating materials. For example, the insulating layer 200 may be formed by growing an oxide layer on a silicon substrate.

As shown in FIG. 3c, a semiconductor channel 300 is formed on the insulating layer 200 by using a two-dimensional semiconductor material. The two-dimensional semiconductor material used in the semiconductor channel 300 may be materials such as MoS ₂ , WS ₂ , ReS ₂ , and SnO. The method for forming the semiconductor channel 300 may be a deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable methods. Process.

As shown in FIG. 3D, a gate potential adjustment structure 400 is formed on the semiconductor channel 300. The gate potential adjustment structure 400 includes a first dielectric layer 401, a potential adjustment layer 403, and a second dielectric layer in this order from bottom to top. 402. Wherein, the material of the first dielectric layer 401 and the second dielectric layer 402 is an insulating material, and for example, it can be formed of silicon oxide. The potential adjustment layer 403 is used to adjust the channel potential, and may be made of polycrystalline silicon or other materials suitable for adjusting the potential. The method for forming the gate potential adjusting structure 400 may be selected from one or more of CVD, MOCVD, ALD, molecular beam epitaxy (MBE), or other suitable processes. The thickness of the formed gate potential adjusting structure 400 may be 2-50 nm.

As shown in FIG. 3e, a plurality of nano carbon tubes 501 of a nano carbon tube gate array 500 are formed on the gate potential adjusting structure 400. A diameter range of each nano carbon tube 501 may be 0.75 to 3 nm, and a length range may be 100 nm to 50 μm. Preferably, a metallic carbon nanotube is used. The method for forming the plurality of nano carbon tubes 501 may be an arc method, a laser evaporation method, a chemical vapor deposition method, a pyrolysis polymerization method, or the like.

Then, as shown in FIG. 3f, the plurality of nano carbon tubes 501 are covered with passivation. Layer 503. Specifically, the material of the passivation layer 503 may be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the passivation layer 503 can be designed according to actual needs. The passivation layer 503 should completely cover and cover the surface of each of the carbon nanotubes 501 to achieve isolation of the carbon nanotubes 501 from the surrounding environment. The method for forming the passivation layer 503 may be selected from one or more of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, atomic layer deposition, or other suitable processes.

As shown in FIG. 3g, openings are respectively formed at both ends of the nano carbon gate array 500 to expose the top of the semiconductor channel 300. When the left and right openings are formed, excess passivation layers 503 at both ends of the carbon nanotube gate array 500 and excess gate potential adjustment structures 400 below the ends are removed, so that the carbon nanotube gate array 500 The semiconductor channels 300 buried below are exposed at the left and right ends. The method of forming the opening may be dry etching, atomic layer etching (ALE), or other suitable methods.

Then, as shown in FIG. 3h, a side wall isolation structure 800 is formed on a side of the opening immediately adjacent to the nano carbon tube gate array 500. Specifically, side wall isolation structures 800 are formed in the left and right openings. The side wall isolation structure 800 may be manufactured by a side wall isolation (Spacer) process, and its manufacturing methods, materials, and structural forms are well known to those skilled in the art, so they are not described in detail here.

Finally, as shown in FIG. 3i, the opening is filled with a conductive material to form a source contact electrode 600 and a drain contact electrode 700 respectively connected to the semiconductor channel 300; and forming the plurality of nanometer carbon tubes 501 respectively A plurality of gate contact electrodes 502; wherein the side wall isolation structure 800 separates the nano carbon tube gate array 500 and the gate potential adjustment structure 400 from the source contact electrode 600 and the drain contact electrode 700, respectively . Specifically, the method for forming a plurality of gate contact electrodes 502 may include a step of etching the passivation layer 503 to form a plurality of through holes to expose the plurality of nanometers, respectively. The carbon tube 501 is then filled with a conductive material in the through hole to form a plurality of gate contact electrodes 502. The method for forming the through hole may be dry etching, atomic layer etching (ALE), or other suitable methods. The gate contact electrode 502, the source contact electrode 600, and the drain contact electrode 700 may be made of conductive materials such as Ti, Al, Ni, Au, or other suitable metal contact materials and structures.

In summary, the neuron transistor crystal structure of the present invention replaces the traditional silicon-doped channels with two-dimensional semiconductor material channels to make the channel charge easier to control. A metal nano-carbon gate array is used as the multi-input of the neuron transistor. The gate electrode can significantly reduce the size of the gate electrode. Compared with the existing neuron MOS transistor, the neuron transistor of the present invention further improves the performance of the device and further reduces the size of the device, which is conducive to solving many problems caused by the increase in the number of transistors and interconnection lines in the integrated circuit . Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims (13)

A neuron electronic crystal structure includes: a semiconductor substrate; an insulating layer on the semiconductor substrate; a semiconductor channel on the insulating layer using a two-dimensional semiconductor material; a gate potential adjustment structure on the semiconductor channel , From the bottom to the top, including a first dielectric layer, a potential adjustment layer and a second dielectric layer; a carbon nanotube gate array, which is located on the gate potential adjustment structure, includes a plurality of nano carbon tubes and a lead-out port. A plurality of gate contact electrodes of the plurality of nano carbon tubes; a source contact electrode and a drain contact electrode are respectively located at two ends of the nano carbon tube gate array and are respectively connected to the semiconductor channel. The neuron transistor structure according to claim 1, wherein between the source contact electrode and the nano-carbon tube gate array and gate potential adjustment structure, and between the drain contact electrode and the nano-carbon tube Side wall isolation structures are respectively provided between the gate array and the gate potential adjustment structure. The neuron transistor structure according to claim 1, wherein the semiconductor substrate is a silicon substrate. The neuron transistor structure according to claim 1, wherein the insulating layer is silicon oxide. The neuron electronic crystal structure according to claim 1, wherein the two-dimensional semiconductor material used for the semiconductor channel is MoS ₂ , WS ₂ , ReS ₂ or SnO. The neuron electrical crystal structure according to claim 1, wherein in the gate potential adjustment structure, materials of the first dielectric layer and the second dielectric layer are silicon oxide. The neuron electric crystal structure according to claim 1, wherein in the gate potential adjustment structure, a material of the potential adjustment layer is polycrystalline silicon. The neuron electronic crystal structure according to claim 1, wherein the thickness of the gate potential adjusting structure is 2-100 nm. The neuron electronic crystal structure according to claim 1, wherein the nano carbon tube gate array uses metallic nano carbon tubes, and each nano carbon tube has a diameter of 0.75 to 3 nm and a length of 100 nm to 50 μm. The neuron transistor structure according to claim 1, wherein a plurality of nano carbon tubes of the nano carbon tube gate array are covered with a passivation layer. The neuron transistor structure according to claim 1, wherein the number of the carbon nanotubes is three or more. A method for preparing a neuron electrical crystal structure includes the following steps: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a semiconductor channel using a two-dimensional semiconductor material on the insulating layer; and forming a semiconductor channel on the semiconductor channel Gate potential adjusting structure, which includes a first dielectric layer, a potential adjusting layer, and a second dielectric layer in order from bottom to top; a plurality of nano carbon tube gate arrays are formed on the gate potential adjusting structure. Carbon nanotubes; covering the plurality of carbon nanotubes with a passivation layer; forming openings at the two ends of the carbon nanotube gate array respectively to expose the top of the semiconductor channel; and the openings are immediately adjacent to the nanometers A side wall isolation structure is formed on one side of the carbon tube gate array; a conductive material is filled in the opening to form a source contact electrode and a drain contact electrode respectively connected to the semiconductor channel; and a plurality of nano carbon tubes are drawn out respectively A plurality of gate contact electrodes; wherein the side wall isolation structure enables the nano carbon tube gate array and the gate potential adjustment structure to be in contact with the source contact electrode and A contact electrode spaced apart. The method for preparing a neuron electrical crystal structure according to claim 12, wherein the method of forming a plurality of gate contact electrodes includes the steps of: etching the passivation layer to form a plurality of through holes to expose the plurality of nano carbon tubes, respectively; A conductive material is then filled in the through holes to form a plurality of gate contact electrodes.