CN102339735B - Preparation method for graphene transistor - Google Patents
Preparation method for graphene transistor Download PDFInfo
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- CN102339735B CN102339735B CN 201110308804 CN201110308804A CN102339735B CN 102339735 B CN102339735 B CN 102339735B CN 201110308804 CN201110308804 CN 201110308804 CN 201110308804 A CN201110308804 A CN 201110308804A CN 102339735 B CN102339735 B CN 102339735B
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Abstract
The invention discloses a preparation method for a graphene transistor. In the method, a carbon nano tube put into a nano groove is used as a grid electrode, and air is used as a grid medium; and a single-grid or multi-grid graphene transistor structure, the groove length of which is close to the diameter of the carbon nano tube and in which the carbon nano tube is used as the grid electrode, can be prepared by transferring graphene prepared by mechanical peeling, chemical vapor deposition (CVD) technology or other growth methods to the position above the groove of the carbon nano tube. According to the method, a novel transistor with full-carbon structure is prepared by combining the carbon nano tube and the graphene.
Description
Technical field
The present invention relates to nanofabrication technique, specifically a kind of transistorized preparation method of Graphene who makes gate electrode of carbon nano-tube.
Background technology
Graphene, namely mono-layer graphite is up to now the thinnest Two-dimensional electron thin-film material.The electron mobility of Graphene is very high, up to 10
5Cm
2V
-1s
-1The order of magnitude is far above electron mobility in the silicon.In theory, all sp in the Graphene
2The carbon atom of hydridization all is saturated to key, Stability Analysis of Structures, and high, the anti-electrical breakdown capability of its current density that can carry is strong; Utilize Graphene fabricating yard effect transistor, can make channel thickness be reduced to monatomic yardstick, its channel length also might foreshorten to nano-scale, and does not have the short channel effect that is similar in the silicon-based devices, therefore Graphene will have huge application potential in the high-speed electronic components field.
At present, the transistorized structure of Graphene mainly contains two kinds, a kind of is back grid structure, Graphene is done raceway groove, silicon dioxide with surface of silicon is done gate medium, does gate electrode with highly doped silicon base, the transistor of this kind structure, its channel length is because of lithographic accuracy or be limited to other micro fabrication, and the minimum channel length of report is 40 nanometers at present; And the transistor parasitic capacitance of back grid structure is very large, can't realize the integrated of device; Another kind of transistor arrangement is top gate structure, and Graphene is made raceway groove, uses SiO
2, Al
2O
3Or HfO
2Deng doing gate dielectric material etc., with electron beam lithography definition gate electrode and gate medium, but its channel length or gate electrode are subject to the electron beam lithography precision, usually are difficult to reach below 10 nanometers.Owing to being subject to micro-processing technology or technical process, above-mentioned two kinds of transistorized channel lengths of structure graphite alkene are difficult to be reduced to below 10 nanometers.
In order to reduce channel length, IBM has proposed self aligned method and has reduced channel length, namely utilizes ald Al
2O
3The time, optionally be deposited into the metal aluminium electrode surface, autoregistration ground sedimentary origin drain electrode.But the transistor channel length of preparation still is subjected to the restriction of technological level in this way, and the selection of gate dielectric material also is restricted (D.B.Farmer and Y.-M.Lin et al., Graphene field-effect transistors with self-aligned gates, Appl.Phys.Lett.Vol.97,2010, P.013103).In addition by utilizing Co
2The Si nano wire is done gate electrode, arrives Co with ald
2The Al of Si nanowire surface
2O
3Do gate dielectric material, prepare the Graphene transistor with self aligned method, its channel length can be reduced to the size of nano wire gate electrode, i.e. 100-300nm.The transistorized channel length of Graphene of the method preparation depends on Co
2Si/Al
2O
3The diameter of nano wire, Co
2Si/Al
2O
3The I of the diameter of nano wire reaches 100nm, therefore also be difficult in this way prepare channel length less than Graphene transistor (the L.Liao and Y.-C.Lin et al. of 10nm, High-speed graphene transistors with a self-alignednanowire gate, Nature, Vol.467, No.16,2010, P.305; L.Liao and J.W.Bai et al, ScalableFabrication of Self-Aligned Graphene Transistors and Circuits on Glass, Nano letters, DOI:10.1021/nl201922c, 2011).
Summary of the invention
The object of the invention is to propose a kind of transistorized preparation method of Graphene who makes gate electrode of carbon nano-tube.
Technical scheme provided by the invention is as follows:
The transistorized preparation method of a kind of Graphene, its step comprises:
(1) at first in substrate preparation as scheme the carbon nano-tube shown in (1) and be positioned over structure in the groove.This structure can obtain by two processes, and namely (a) preparation nanoscale groove, (b) place (or growth) carbon nano-tube, this (a) and (b) front and back of two processes sequentially do not have specific (special) requirements, can be in no particular order.For example: can prepare groove with micro-machined method in substrate first, then carbon nano-tube or the carbon nano-tube that will prepare are transferred in the groove in groove; Also can transfer in the substrate at carbon nano-tube in the substrate or with the carbon nano-tube of preparing first, and then the preparation groove, carbon nano-tube is placed in the groove;
Wherein, substrate can be SiO
2, quartzy, GaAs or plastic or other material; Carbon nano-tube can be Single Walled Carbon Nanotube, multi-walled carbon nano-tubes or carbon nano-tube tube bank; The structure that carbon nano-tube is positioned in the groove can be one or more, groove width＜1.5 μ m, and the degree of depth＜300nm, groove pitch is 2nm～1 μ m;
(2) with electric conducting material carbon nano-tube is drawn, be used for electrical performance testing, shown in figure (2).Electric conducting material can be metal material (as: Al, Pd or Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate)) etc., also can be high doping semiconductor material, conductive plastics or polymeric material etc.
Drawing the process of carbon nano-tube also can carry out before the groove preparation;
(3) directly utilize air to do gate dielectric material, Graphene is transferred to above the groove at carbon nano-tube place, the air in the groove between carbon nano-tube and the Graphene is gate medium, shown in figure (3); Graphene can be that the method with mechanical stripping directly obtains, and is transferred to substrate surface; Also can be with the preparation of the methods such as chemical vapour deposition (CVD) or thermal decomposition, again Graphene be transferred to substrate.Graphene can be individual layer, and is two-layer or multilayer.Graphene can be across on a groove, also can be simultaneously across on a plurality of grooves;
(4) draw at the two ends of Graphene depositing conductive material, be used for electrical performance testing, shown in figure (4).Electric conducting material can be metal material (as: Al, Pd or Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate)) etc., also can be high doping semiconductor material, conductive plastics or polymeric material etc.
The principle of the invention:
Basic principle of the present invention:
Utilization is preset in the interior carbon nano-tube of nanoscale groove as gate electrode, utilize air to make gate medium, with mechanical stripping, CVD technology or be transferred to the top of carbon nano-tube place groove with the Graphene of other growing method preparation, carbon nano-tube is as gate electrode, and utilize the graphic method such as electron beam exposure source, leakage and gate electrode to be drawn (being used for electrical performance testing), then can make channel length near carbon nano-tube diameter, carbon nano-tube single grid or the multiple-grid Graphene transistor arrangement as gate electrode.
Advantage of the present invention is as follows:
At first, the Graphene transistor arrangement that proposes among the present invention be with carbon nano-tube as gate electrode, so the channel length of gate electrode control can be very little (＜10nm), even near the diameter of single Single Walled Carbon Nanotube, for example 1.4nm.Secondly, directly utilize air to make gate medium, Graphene is suspended from the groove top, its lower surface not with carbon nano-tube or substrate contact, the problem of having avoided electric leakage or having reduced because of the mobility due to substrate or the gate medium can make Graphene substantially keep its intrinsic property; By the combination of carbon nano-tube and Graphene, might realize transistor arrangement or the circuit of full carbon in addition.
Description of drawings
Fig. 1. for carbon nano-tube is positioned over structural representation in the groove;
Fig. 2. be the schematic diagram of carbon nano-tube being drawn with electric conducting material;
Fig. 3. be the schematic diagram on the groove that Graphene is transferred to the carbon nano-tube place;
Fig. 4. be the schematic diagram at the two ends of Graphene depositing conductive material.
Embodiment
Embodiment one,
(1) at first at Si/SiO
2Arrange Single Walled Carbon Nanotube in the substrate, with Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate) carbon nano-tube is drawn.
(2) pass through PVD sputter one deck SiO on the surface of said structure
2, thickness is 30nm, then uses the hf etching silicon dioxide (SiO that comprises the PVD sputter
2SiO with original substrate surface
2), owing to the enhanced etching effect of carbon nano-tube, will produce the groove of a nanoscale in the position of carbon nano-tube, carbon nano-tube also can fall in the groove thereupon;
(3) Graphene is peeled off and is transferred to above the groove at carbon nano-tube place with the method for mechanical stripping, the air in the groove between carbon nano-tube and the Graphene is gate medium;
(4) draw at the two ends of Graphene depositing conductive material, be used for the test electric property, electric conducting material is palladium (Pd).
Embodiment two,
(1) groove that at first utilizes the method for electron beam exposure and etching to prepare in quartz substrate.Groove width 1 μ m, gash depth is: 50nm.Growing single-wall carbon nano tube in groove.
(2) with palladium (Pd) carbon nano-tube is drawn.
(3) directly will transfer to above the groove at carbon nano-tube place with the Graphene of chemical vapour deposition technique preparation, the air in the groove between carbon nano-tube and the Graphene is gate medium;
(4) draw at the two ends of Graphene depositing conductive material, be used for the test electric property, electric conducting material is Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate).
Above-described embodiment is not for limiting the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can make various conversion and modification, so protection scope of the present invention is looked the claim scope and defined.
Claims (9)
1. transistorized preparation method of Graphene, its step comprises:
1) prepares nanoscale groove structures single or several placement carbon nano-tube in substrate, be provided with carbon nano-tube in the groove as gate electrode;
2) by electric conducting material carbon nano-tube is drawn;
3) Graphene is transferred to above the groove at carbon nano-tube place, the air in the groove between carbon nano-tube and the Graphene is gate medium;
4) draw at the two ends of Graphene depositing conductive material.
2. the method for claim 1 is characterized in that step 1) be specially: prepare groove with micro-machined method in substrate first, then carbon nano-tube or the carbon nano-tube that will prepare are transferred in the nanoscale groove in groove.
3. the method for claim 1 is characterized in that step 1) in substrate be SiO
2, quartzy, GaAs or plastics.
4. the method for claim 1 is characterized in that step 1) in carbon nano-tube be Single Walled Carbon Nanotube, multi-walled carbon nano-tubes or carbon nano-tube tube bank.
5. the method for claim 1 is characterized in that step 1) in the carbon nano-tube that is positioned in the groove be one or more.
6. the method for claim 1 is characterized in that step 1) in the spacing of groove be 2nm～1 μ m, groove width＜1.5 μ m, gash depth＜300nm.
7. the method for claim 1 is characterized in that step 3) in Graphene be single or multiple lift.
8. the method for claim 1 is characterized in that step 3) in Graphene across on a groove, or simultaneously across on a plurality of grooves, and place in advance carbon nano-tube in the groove.
9. the method for claim 1 is characterized in that, described electric conducting material is metal material, high doping semiconductor material, conductive plastics or polymeric material.
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| CN 201110308804 CN102339735B (en) | 2011-10-12 | 2011-10-12 | Preparation method for graphene transistor |
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| CN 201110308804 CN102339735B (en) | 2011-10-12 | 2011-10-12 | Preparation method for graphene transistor |
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| CN102339735B true CN102339735B (en) | 2013-03-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8796096B2 (en) * | 2012-12-04 | 2014-08-05 | International Business Machines Corporation | Self-aligned double-gate graphene transistor |
| CN103594378B (en) * | 2013-11-23 | 2016-08-17 | 中北大学 | The preparation method of the unsettled graphene-channel transistor of groove structure |
| CN104392945A (en) * | 2014-10-31 | 2015-03-04 | 北京工业大学 | Method for estimating mobility of graphene grown on copper foil through CVD method based on field effect |
| CN108258038B (en) * | 2016-12-28 | 2020-10-16 | 上海新昇半导体科技有限公司 | Neuron transistor structure and preparation method thereof |
| CN108258044B (en) * | 2016-12-28 | 2020-12-15 | 上海新昇半导体科技有限公司 | Neuron transistor structure and preparation method thereof |
| CN108257968A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of no pn junction p n trench gate array memory structure and preparation method thereof |
| CN107768251A (en) * | 2017-10-17 | 2018-03-06 | 江苏大学 | A kind of preparation method of the graphene field effect transistor based on Bubbling method |
| CN110190122B (en) * | 2018-02-23 | 2022-07-12 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN111969037A (en) * | 2020-07-21 | 2020-11-20 | 上海集成电路研发中心有限公司 | Air-gap graphene field effect tube structure and preparation method |
| CN116544279A (en) * | 2023-04-30 | 2023-08-04 | 天津大学 | All-carbon graphene device and preparation method thereof |
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| KR101480082B1 (en) * | 2008-10-09 | 2015-01-08 | 삼성전자주식회사 | Quantum interference transistor using Graphene and methods of manufacturing and operating the same |
| KR101156620B1 (en) * | 2009-04-08 | 2012-06-14 | 한국전자통신연구원 | Field effect transistor having graphene channel layer |
| CN102074584B (en) * | 2010-12-06 | 2012-07-04 | 复旦大学 | Air-gap grapheme transistor and manufacturing method thereof |
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