CN102339735A - Preparation method for graphene transistor - Google Patents
Preparation method for graphene transistor Download PDFInfo
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- CN102339735A CN102339735A CN2011103088044A CN201110308804A CN102339735A CN 102339735 A CN102339735 A CN 102339735A CN 2011103088044 A CN2011103088044 A CN 2011103088044A CN 201110308804 A CN201110308804 A CN 201110308804A CN 102339735 A CN102339735 A CN 102339735A
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Abstract
The invention discloses a preparation method for a graphene transistor. In the method, a carbon nano tube put into a nano groove is used as a grid electrode, and air is used as a grid medium; and a single-grid or multi-grid graphene transistor structure, the groove length of which is close to the diameter of the carbon nano tube and in which the carbon nano tube is used as the grid electrode, can be prepared by transferring graphene prepared by mechanical peeling, chemical vapor deposition (CVD) technology or other growth methods to the position above the groove of the carbon nano tube. According to the method, a novel transistor with full-carbon structure is prepared by combining the carbon nano tube and the graphene.
Description
Technical field
The present invention relates to nanofabrication technique, specifically is a kind of transistorized preparation method of Graphene who makes gate electrode of CNT.
Background technology
Graphene, promptly mono-layer graphite is the thinnest up to now two-dimentional electric thin material.The electron mobility of Graphene is very high, up to 10
5Cm
2V
-1s
-1The order of magnitude is far above electron mobility in the silicon.In theory, all sp in the Graphene
2The carbon atom of hydridization all is saturated to key, Stability Analysis of Structures, and its current density that can carry is high, anti-electrical breakdown capability is strong; Utilize Graphene fabricating yard effect transistor; Can make channel thickness be reduced to monatomic yardstick; Its channel length also might foreshorten to nano-scale, and does not have the short channel effect that is similar in the silicon-based devices, so Graphene will have huge application potential in the high-speed electronic components field.
At present, the transistorized structure of Graphene mainly contains two kinds, and a kind of is back grid structure; Graphene is done raceway groove; Silicon dioxide with surface of silicon is done gate medium, does gate electrode with highly doped silicon base, the transistor of this kind structure; Its channel length is because of lithographic accuracy or be limited to other micro fabrication, and the minimum channel length of report is 40 nanometers at present; And the transistor parasitic capacitance of back grid structure is very big, can't realize the integrated of device; Another kind of transistor arrangement is a top gate structure, and Graphene is made raceway groove, uses SiO
2, Al
2O
3Or HfO
2Deng doing gate dielectric material etc., with electron beam lithography definition gate electrode and gate medium, but its channel length or gate electrode are subject to the electron beam lithography precision, are difficult to usually reach below 10 nanometers.Owing to be subject to micro-processing technology or technical process, above-mentioned two kinds of transistorized channel lengths of structure Graphene are difficult to be reduced to below 10 nanometers.
In order to reduce channel length, IBM has proposed self aligned method and has reduced channel length, promptly utilizes ald Al
2O
3The time, optionally be deposited into the metal aluminium electrode surface, autoregistration ground sedimentary origin drain electrode.But the transistor channel length of preparation still receives the restriction of technological level in this way; And the selection of gate dielectric material also is restricted (D.B.Farmer and Y.-M.Lin et al.; Graphene field-effect transistors with self-aligned gates; Appl.Phys.Lett.Vol.97,2010, P.013103).In addition through utilizing Co
2The Si nano wire is done gate electrode, arrives Co with ald
2The Al of Si nanowire surface
2O
3Do gate dielectric material, prepare the Graphene transistor with self aligned method, its channel length can be reduced to the size of nano wire gate electrode, i.e. 100-300nm.The transistorized channel length of Graphene of this method preparation depends on Co
2Si/Al
2O
3The diameter of nano wire, Co
2Si/Al
2O
3The I of the diameter of nano wire reaches 100nm; So also be difficult to prepare Graphene transistor (L.Liao and Y.-C.Lin et al., High-speed graphene transistors with a self-alignednanowire gate, the Nature of channel length in this way less than 10nm; Vol.467; No.16,2010, P.305; L.Liao and J.W.Bai et al, ScalableFabrication of Self-Aligned Graphene Transistors and Circuits on Glass, Nano letters, DOI:10.1021/nl201922c, 2011).
Summary of the invention
The objective of the invention is to propose a kind of transistorized preparation method of Graphene who makes gate electrode of CNT.
Technical scheme provided by the invention is following:
The transistorized preparation method of a kind of Graphene, its step comprises:
(1) at first is positioned over the structure in the groove at the CNT of preparation shown in figure (1) in the substrate.This structure can obtain through two processes, and promptly (a) preparation nanoscale groove, (b) place (or growth) CNT, this (a) and (b) front and back of two processes do not have in proper order specific (special) requirements, can be in no particular order.For example: can in substrate, prepare groove with micro-machined method earlier, the CNT that carbon nano-tube perhaps will have been prepared in groove is then transferred in the groove; Also can perhaps the CNT of preparing be transferred in the substrate at carbon nano-tube in the substrate earlier, and then the preparation groove, CNT is placed in the groove;
Wherein, substrate can be SiO
2, quartzy, GaAs or plastic or other material; CNT can be SWCN, multi-walled carbon nano-tubes or CNT tube bank; The structure that CNT is positioned in the groove can be one or more, groove width＜1.5 μ m, and the degree of depth＜300nm, groove pitch is 2nm～1 μ m;
(2) with electric conducting material CNT is drawn, be used for electrical performance testing, shown in figure (2).Electric conducting material can be metal material (as: Al, Pd or Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate)) etc., also can be high doping semiconductor material, conductive plastics or polymeric material etc.
Drawing the process of CNT also can carry out before the groove preparation;
(3) directly utilize air to do gate dielectric material, Graphene is transferred to above the groove at CNT place, the air in the groove between CNT and the Graphene is a gate medium, shown in figure (3); Graphene can be that the method with mechanical stripping directly obtains, and is transferred to substrate surface; Also can be with the preparation of methods such as chemical vapour deposition (CVD) or thermal decomposition, again Graphene transferred to substrate.Graphene can be individual layer, and is two-layer or multilayer.Graphene can be across on a groove, also can be simultaneously across on a plurality of grooves;
(4) depositing conductive material is drawn at the two ends of Graphene, is used for electrical performance testing, shown in figure (4).Electric conducting material can be metal material (as: Al, Pd or Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate)) etc., also can be high doping semiconductor material, conductive plastics or polymeric material etc.
The principle of the invention:
Basic principle of the present invention:
Utilization is preset in the interior CNT of nanoscale groove as gate electrode; Utilize air to make gate medium; Be transferred to the top that CNT belongs to groove with mechanical stripping, CVD technology or with the Graphene of other growing method preparation; CNT is as gate electrode; And utilize electron beam exposure figures method that source, leakage and gate electrode are drawn (being used for electrical performance testing), then can make channel length near CNT diameter, CNT single grid or multiple-grid Graphene transistor arrangement as gate electrode.
Advantage of the present invention is following:
At first, the Graphene transistor arrangement that proposes among the present invention be with CNT as gate electrode, so the channel length of gate electrode control can be very little (＜10nm), even near the diameter of single SWCN, for example 1.4nm.Secondly, directly utilize air to make gate medium, Graphene is suspended from the groove top, and its lower surface contact with CNT or substrate, has avoided electric leakage or because of the problem of the mobility reduction due to substrate or the gate medium, can make Graphene keep its intrinsic property basically; Through the combination of CNT and Graphene, might realize the transistor arrangement or the circuit of full carbon in addition.
Description of drawings
Fig. 1. for CNT is positioned over the structural representation in the groove;
Fig. 2. be the sketch map of CNT being drawn with electric conducting material;
Fig. 3. be the sketch map on the groove that Graphene is transferred to the CNT place;
Fig. 4. be sketch map at the two ends of Graphene depositing conductive material.
Embodiment
Embodiment one,
(1) at first at Si/SiO
2Arrange SWCN in the substrate, CNT is drawn with Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate).
(2) pass through PVD sputter one deck SiO on the surface of said structure
2, thickness is 30nm, uses the hf etching silicon dioxide (SiO that comprises the PVD sputter then
2SiO with original substrate surface
2), owing to the enhancing corrasion of CNT, will produce the groove of a nanoscale in the position of CNT, CNT also can fall in the groove thereupon;
(3) Graphene is peeled off and is transferred to above the groove at CNT place with the method for mechanical stripping, the air in the groove between CNT and the Graphene is a gate medium;
(4) depositing conductive material is drawn at the two ends of Graphene, is used to test electric property, and electric conducting material is palladium (Pd).
Embodiment two,
(1) groove that at first on quartz substrate, utilizes the method for electron beam exposure and etching to prepare.Groove width 1 μ m, gash depth is: 50nm.Growing single-wall carbon nano tube in groove.
(2) with palladium (Pd) CNT is drawn.
(3) directly will transfer to above the groove at CNT place with the Graphene of chemical vapour deposition technique preparation, the air in the groove between CNT and the Graphene is a gate medium;
(4) depositing conductive material is drawn at the two ends of Graphene, is used to test electric property, and electric conducting material is Au/Ti double-level-metal (Au is positioned at the top, and Ti is positioned at the below, as with the adhesion layer of substrate).
Above-described embodiment is used to limit the present invention, and any those skilled in the art is not breaking away from the spirit and scope of the present invention, can make various conversion and modification, so protection scope of the present invention is looked the claim scope and defined.
Claims (9)
1. transistorized preparation method of Graphene, its step comprises:
1) in substrate, prepares nanoscale groove structures single or several placement CNTs, be provided with CNT in the groove as gate electrode;
2) through electric conducting material CNT is drawn;
3) Graphene is transferred to above the groove at CNT place, the air in the groove between CNT and the Graphene is a gate medium;
4) depositing conductive material is drawn at the two ends of Graphene.
2. the method for claim 1 is characterized in that, step 1) is specially: in substrate, prepare groove with micro-machined method earlier, the CNT that carbon nano-tube perhaps will have been prepared in groove is then transferred in the nanoscale groove.
3. the method for claim 1 is characterized in that, substrate is SiO in the step 1)
2, quartzy, GaAs or plastics.
4. the method for claim 1 is characterized in that, CNT is SWCN, multi-walled carbon nano-tubes or CNT tube bank in the step 1).
5. the method for claim 1 is characterized in that, the CNT that is positioned in the step 1) in the groove is one or more.
6. the method for claim 1 is characterized in that, the spacing of groove is 2nm～1 μ m in the step 1), groove width＜1.5 μ m, gash depth＜300nm.
7. the method for claim 1 is characterized in that, Graphene is individual layer, two-layer or multilayer in the step 3).
8. the method for claim 1 is characterized in that, Graphene or simultaneously across on a plurality of grooves, and is placed CNT across on a groove in advance in the step 3) in the groove.
9. the method for claim 1 is characterized in that, said electric conducting material is metal material, high doping semiconductor material, conductive plastics or polymeric material.
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| CN 201110308804 CN102339735B (en) | 2011-10-12 | 2011-10-12 | Preparation method for graphene transistor |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594378A (en) * | 2013-11-23 | 2014-02-19 | 中北大学 | Method for manufacturing suspended graphene channel transistor of groove structure |
| CN103855218A (en) * | 2012-12-04 | 2014-06-11 | 国际商业机器公司 | SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR and method for fabricating same |
| CN104392945A (en) * | 2014-10-31 | 2015-03-04 | 北京工业大学 | Method for estimating mobility of graphene grown on copper foil through CVD method based on field effect |
| CN107768251A (en) * | 2017-10-17 | 2018-03-06 | 江苏大学 | A kind of preparation method of the graphene field effect transistor based on Bubbling method |
| CN108258038A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | Neuron MOS transistor structure and preparation method thereof |
| CN108258044A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of Neuron MOS transistor structure and preparation method thereof |
| CN108257968A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of no pn junction p n trench gate array memory structure and preparation method thereof |
| CN110190122A (en) * | 2018-02-23 | 2019-08-30 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| WO2022017387A1 (en) * | 2020-07-21 | 2022-01-27 | 上海集成电路研发中心有限公司 | Gap graphene field effect transistor structure and manufacturing method |
| CN116544279A (en) * | 2023-04-30 | 2023-08-04 | 天津大学 | All-carbon graphene device and preparation method thereof |
| CN116544279B (en) * | 2023-04-30 | 2024-06-04 | 天津大学 | All-carbon graphene device and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719510A (en) * | 2008-10-09 | 2010-06-02 | 三星电子株式会社 | Quantum interference transistor using graphene and methods of manufacturing and operating the same |
| US20100258787A1 (en) * | 2009-04-08 | 2010-10-14 | Electronics And Telecommunications Research Institute | Field effect transistor having graphene channel layer |
| CN102074584A (en) * | 2010-12-06 | 2011-05-25 | 复旦大学 | Air-gap grapheme transistor and manufacturing method thereof |
-
2011
- 2011-10-12 CN CN 201110308804 patent/CN102339735B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719510A (en) * | 2008-10-09 | 2010-06-02 | 三星电子株式会社 | Quantum interference transistor using graphene and methods of manufacturing and operating the same |
| US20100258787A1 (en) * | 2009-04-08 | 2010-10-14 | Electronics And Telecommunications Research Institute | Field effect transistor having graphene channel layer |
| CN102074584A (en) * | 2010-12-06 | 2011-05-25 | 复旦大学 | Air-gap grapheme transistor and manufacturing method thereof |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855218A (en) * | 2012-12-04 | 2014-06-11 | 国际商业机器公司 | SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR and method for fabricating same |
| CN103855218B (en) * | 2012-12-04 | 2016-09-28 | 国际商业机器公司 | Autoregistration double grid grapheme transistor and manufacture method thereof |
| CN103594378A (en) * | 2013-11-23 | 2014-02-19 | 中北大学 | Method for manufacturing suspended graphene channel transistor of groove structure |
| CN103594378B (en) * | 2013-11-23 | 2016-08-17 | 中北大学 | The preparation method of the unsettled graphene-channel transistor of groove structure |
| CN104392945A (en) * | 2014-10-31 | 2015-03-04 | 北京工业大学 | Method for estimating mobility of graphene grown on copper foil through CVD method based on field effect |
| CN108258038A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | Neuron MOS transistor structure and preparation method thereof |
| CN108258044A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of Neuron MOS transistor structure and preparation method thereof |
| CN108257968A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of no pn junction p n trench gate array memory structure and preparation method thereof |
| CN108258038B (en) * | 2016-12-28 | 2020-10-16 | 上海新昇半导体科技有限公司 | Neuron transistor structure and preparation method thereof |
| CN108258044B (en) * | 2016-12-28 | 2020-12-15 | 上海新昇半导体科技有限公司 | Neuron transistor structure and preparation method thereof |
| CN107768251A (en) * | 2017-10-17 | 2018-03-06 | 江苏大学 | A kind of preparation method of the graphene field effect transistor based on Bubbling method |
| CN110190122A (en) * | 2018-02-23 | 2019-08-30 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| WO2022017387A1 (en) * | 2020-07-21 | 2022-01-27 | 上海集成电路研发中心有限公司 | Gap graphene field effect transistor structure and manufacturing method |
| CN116544279A (en) * | 2023-04-30 | 2023-08-04 | 天津大学 | All-carbon graphene device and preparation method thereof |
| CN116544279B (en) * | 2023-04-30 | 2024-06-04 | 天津大学 | All-carbon graphene device and preparation method thereof |
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| CN102339735B (en) | 2013-03-06 |
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