TWI651836B - Gate array contactless semiconductor channel memory structure and preparation method thereof - Google Patents

Abstract

The invention provides a gate array non-contact semiconductor channel memory structure and a preparation method thereof. The structure includes: a semiconductor substrate; an insulating layer on the semiconductor substrate; and a semiconductor using a two-dimensional semiconductor material on the insulating layer. A channel; a gate charge trapping structure on the semiconductor channel; a nano carbon tube gate array above the gate charge trapping structure; and two ends of the nano carbon tube gate array, respectively, and A source contact electrode and a drain contact electrode connected to the semiconductor channel. The memory structure of the present invention uses two-dimensional semiconductor material channels instead of traditional silicon-doped channels, and uses a metal nano-carbon tube gate array, which improves gate charge trapping performance, simplifies element structure, and further increases memory array density. .

Description

   Gate array non-contact semiconductor channel memory structure and preparation method thereof   

The invention relates to the technical field of integrated circuits, in particular to a gate array non-contact semiconductor channel memory structure and a preparation method thereof.

For different architectures of NAND memory, the material of the memory layer can be divided into three-dimensional floating gate memory and three-dimensional charge trapping memory. For the former three-dimensional floating gate memory, because the polycrystalline silicon floating gate is used as the memory layer, the memory cell area is larger, and the process is more difficult when more layers of memory cells are stacked. Therefore, the peripheral circuit is mainly placed under the memory array. To achieve area reduction. For the latter three-dimensional charge trapping memory, it can be divided into vertical gate type and vertical channel type. The three-dimensional charge trapping flash memory structure based on the vertical gate structure is difficult to process in the vertical channel type, and its mass production has not been announced. Vertical channel 3D charge trapping memory is the earliest flash memory product to achieve mass production. In August 2013, Samsung Electronics introduced the first 24-layer 3D vertical channel charge trapping 3D memory. July 2014 The second generation of 32-layer 128Gb products was launched in January, and 48-layer 256Gb products were launched in 2015.

The vertical channel type three-dimensional charge trapping flash memory introduced by Samsung Electronics uses vertical polycrystalline silicon cylinders as channels, and multiple layers of gates surround the polycrystalline silicon cylinders. Each layer of gates serves as a word line, so that the word line becomes horizontal. Layer, bit line connected to vertical polycrystalline silicon circle The top of the cylinder. The common source lines are drawn out one by one by making heavily doped regions on the substrate. The gate is memorized by a charge trapping method, and a tunneling layer, a charge trapping layer, and a blocking layer are provided between the polycrystalline silicon channel and the gate metal. For a detailed description of the element structure, please refer to the patent document with patent publication number CN104425511A.

The key technologies of this vertical channel type 3D charge trapping flash memory are ultra deep hole etching and high quality thin film process. The 32-layer ultra-deep hole has an aspect ratio close to 30: 1, and the diameter difference between the upper and lower holes must be less than 10-20nm. The gate dielectric multilayer film not only requires the thickness of the top layer and the bottom layer to be substantially the same, but also places high requirements on the uniformity of the material. The channel material is generally a polycrystalline silicon thin film, which requires good crystallinity and large grains, and also needs a low defect density interface with the gate dielectric layer. As a kind of charge trapping memory, there is almost no coupling effect between memory cells. The programming and erase operations use Fowler-Nordheim (FN) tunneling of electrons and holes, respectively. In order to increase the erasing speed, the tunneling layer usually uses a stacked structure based on silicon oxide and silicon oxynitride materials. The memory layer is generally a high trap density material based on silicon nitride. In order to reduce the gate reverse injection, the barrier layer uses materials such as silicon oxide or aluminum oxide.

However, in the existing vertical channel type three-dimensional charge trapping memory, the material of the channel of the device is polycrystalline silicon film, which requires good crystallinity and large crystal grains. At the same time, the thickness of the channel of the polycrystalline silicon film must be as thin as possible, and it is difficult to balance the manufacturing process. , Affecting product yield.

In view of the foregoing prior art, an object of the present invention is to provide a gate array non-contact semiconductor channel memory structure and a preparation method thereof, which are used to solve various problems in the prior art.

In order to achieve the above object and other related objects, the present invention provides a gate array non-contact semiconductor channel memory structure including: a semiconductor substrate; an insulating layer on the semiconductor substrate; a semiconductor channel on the insulating layer, Using a two-dimensional semiconductor material; a gate charge trapping structure located on the semiconductor channel, which includes a tunnel layer, a charge trapping layer, and a barrier layer in order from bottom to top; a nano-carbon tube gate array located above the gate charge trapping structure, It includes a plurality of nano carbon tubes and a plurality of gate contact electrodes respectively leading out of the plurality of nano carbon tubes; a source contact electrode and a drain contact electrode are respectively located at two ends of the nano carbon tube gate array, and are respectively connected with all the carbon nanotube gate arrays. Said semiconductor channel connection.

Optionally, the semiconductor substrate is a silicon substrate.

Optionally, the insulating layer is silicon oxide.

Optionally, the two-dimensional semiconductor material used for the semiconductor channel is MoS ₂ , WS ₂ , ReS ₂ or SnO.

Optionally, in the gate charge trapping structure, a material of the tunnel layer is silicon oxide, a material of the charge trapping layer is silicon nitride, and a material of the barrier layer is silicon oxide.

Optionally, the nano carbon tube gate array adopts a metallic nano carbon tube, and each nano carbon tube has a diameter of 0.75 to 3 nm and a length of 100 nm to 50 μm.

Optionally, a surface of a plurality of nano carbon tubes of the nano carbon tube gate array is covered with a passivation layer.

Optionally, the gate array contactless semiconductor channel memory structure includes a plurality of The semiconductor channel, each of the semiconductor channels corresponds to a set of memory cell strings; the nano carbon tube gate array includes a plurality of sets of nano carbon tubes respectively corresponding to a plurality of sets of memory cell strings; a nano of each set of memory cell strings The carbon tube is arranged on the corresponding semiconductor channel, and includes a plurality of word line gate nano carbon tubes, a string selection gate nano carbon tube, and a ground selection gate nano carbon tube. The carbon tube and the ground selection gate nano carbon tube are respectively located at two ends of a plurality of word line gate nano carbon tubes.

In order to achieve the above object and other related objects, the present invention also provides a method for preparing a gate array non-contact semiconductor channel memory structure, including the following steps: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; and insulating the insulation A two-dimensional semiconductor material is used to form a semiconductor channel on the layer; a gate charge trap structure is formed on the semiconductor channel, and the gate charge trap structure includes a tunnel layer, a charge trap layer, and a barrier layer in order from bottom to top; Forming a plurality of nano carbon tube gate arrays on the structure; covering the plurality of nano carbon tubes with a passivation layer; forming a plurality of gate contact electrodes respectively leading out of the plurality of nano carbon tubes, and A source contact electrode and a drain contact electrode which are respectively located at two ends of the nano carbon tube gate array and are connected to the semiconductor channel.

Optionally, when a two-dimensional semiconductor material is used to form a semiconductor channel on the insulating layer, a plurality of semiconductor channels are simultaneously formed.

Further optionally, when a plurality of nano carbon tubes of a nano carbon tube gate array are formed on the gate charge trapping structure, a plurality of groups of nano carbon tubes are arranged according to the positions of the plurality of semiconductor channels, so that each group Nano carbon tubes are located above the corresponding semiconductor channels.

Optionally, the method for forming a plurality of gate contact electrodes includes the steps of: etching the passivation layer to form a plurality of through holes to respectively expose the plurality of nano carbon tubes, and then filling the through holes with a conductive material to form a plurality of through holes. The brake contacts the electrodes.

Optionally, the method of forming the source contact electrode and the drain contact electrode includes the steps of: etching openings at both ends of the nano carbon tube gate array to expose the top of the semiconductor channel, and then filling the opening with a conductive material , Forming a source contact electrode and a drain contact electrode.

As described above, the gate array non-contact semiconductor channel memory structure of the present invention and the preparation method thereof have the following beneficial effects: The gate array non-contact semiconductor channel memory structure of the present invention uses a gate charge trapping method for the memory unit By replacing the traditional silicon-doped channels with two-dimensional semiconductor material channels, the charge is easier to control, and the gate charge capture performance is improved. The metal nano-carbon tube gate array is used to significantly reduce the gate size, compared to the existing vertical In the channel-type NAND structure, the device performance is further improved, the device structure is further simplified, and the memory array density is increased.

100‧‧‧ semiconductor substrate

200‧‧‧ Insulation

300‧‧‧Semiconductor Channel

400‧‧‧ Gate charge trapping structure

401‧‧‧ tunnel floor

402‧‧‧ charge trapping layer

403‧‧‧ barrier

500‧‧‧nanometer carbon tube gate array

501‧‧‧nanometer carbon tube

502‧‧‧Brake contact electrode

503‧‧‧ passivation layer

600‧‧‧ source contact electrode

700‧‧‧ Drain contact electrode

FIG. 1 is a schematic diagram of a gate array non-contact semiconductor channel memory structure according to an embodiment of the present invention.

Figures 2a-2g are schematic diagrams showing the fabrication process of a gate array non-contact semiconductor channel memory structure according to an embodiment of the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the illustrations provided in the following embodiments are only a schematic illustration of the basic idea of the present invention, and the drawings only show the components related to the present invention and not the number, shape and For size drawing, the type, quantity, and proportion of each component can be changed at will in actual implementation, and the component layout type may be more complicated.

This embodiment provides a memory structure and a preparation method that can be applied to a NAND flash memory. The memory structure of a NAND memory includes a memory array, and the memory array may be composed of multiple sets of memory cell strings. Each group of memory cell strings in this embodiment adopts a form in which a plurality of gate non-contact type switching transistors share a horizontal channel, and a plurality of gate non-contact type switching transistors, that is, the gates are connected to the ground selection line (GSL) Ground selection transistors, the gates are respectively connected to a plurality of gate-controlled charge trapping memory cells of a plurality of word lines (WL), and the string selection transistors are connected to a string selection line (SSL). The gate electrodes of these gateless contactless switching transistors are made of metal carbon nanotubes, which are arranged in a horizontal direction as an array of gate electrodes. The gate dielectric layer uses a dielectric charge-trapping structure. The shared horizontal channel uses a two-dimensional semiconductor. Materials replace traditional silicon-doped materials, which improves gate charge trapping performance and simplifies device structure.

Referring to FIG. 1, a gate array non-contact semiconductor channel memory structure provided in this embodiment specifically includes: a semiconductor substrate 100; An insulating layer 200 is located on the semiconductor substrate 100; a semiconductor channel 300 using a two-dimensional semiconductor material is located on the insulating layer 200; a gate charge trapping structure 400 is located on the semiconductor channel 300, and includes from bottom to top The tunnel layer 401, the charge trapping layer 402, and the barrier layer 403; the nano carbon tube gate array 500, which is located on the gate charge trapping structure 400, includes a plurality of nano carbon tubes 501 and each of the plurality of nano carbons is led out. A plurality of gate contact electrodes 502; a source contact electrode 600 and a drain contact electrode 700 of the tube 501 are respectively located at two ends of the nano carbon tube gate array 500 and are respectively connected to the semiconductor channel 300.

In this embodiment, the semiconductor substrate 100 may be a silicon substrate or other suitable semiconductor material substrate. The insulating layer 200 may be silicon oxide or other suitable insulating materials.

In this embodiment, the two-dimensional semiconductor material used for the semiconductor channel 300 may be materials such as MoS ₂ , WS ₂ , ReS ₂ , and SnO.

In this embodiment, the gate charge trapping structure 400 is made of an insulating material, for example, it may be an ONO dielectric material, that is, silicon oxide, silicon nitride, or silicon oxide. The material of the tunnel layer 401 may be silicon oxide, the material of the charge trapping layer 402 may be silicon nitride, and the material of the barrier layer 403 may be silicon oxide or high-k with high dielectric constant. Dielectric material. Specifically, the thickness of the gate charge trapping structure 400 may be 2-50 nm.

In this embodiment, the nano carbon tube gate array 500 may be a metallic nano carbon tube. The diameter of each nano carbon tube 501 may be 0.75 to 3 nm, and the length may be 100 nm to 50 μm.

In this embodiment, the surface of the plurality of nano carbon tubes 501 of the nano carbon tube gate array 500 is covered with a passivation layer 503. Specifically, the material of the passivation layer 503 may be, for example, silicon oxide, silicon Insulating materials such as nitride or silicon oxynitride. The thickness of the passivation layer 503 can be designed according to actual needs, and the surface of the nano carbon tube 501 should be completely wrapped to cover the nano carbon tube 501 from the surrounding environment.

In this embodiment, in order to form a memory array, there may be a plurality of semiconductor channels 300, and each semiconductor channel 300 corresponds to a group of memory cell strings; the carbon nanotube array 500 may include a plurality of memory cell strings respectively. Nano tube 501 of each group of memory cell strings are arranged on the corresponding semiconductor channel 300, including a plurality of word line gate carbon nanotubes, string selection gate carbon nanotubes And a ground selection gate nanometer carbon tube, wherein the string selection gate nanometer carbon tube and the ground selection gate nanometer carbon tube are respectively located at two ends of a plurality of word line gate nanometer carbon tubes. The width of each semiconductor channel 300 may be 2-50 nm. The plurality of semiconductor channels 300 may be filled with a dielectric material to achieve isolation. The number of nanometer carbon tubes 501 of each group of memory cell strings can be designed according to actual needs. For example, one string selects the gate nanometer carbon tube and one ground selects the gate nanometer carbon tube, and the word line gate nanometer. The number of carbon tubes can be 24, 32, 48, or even more.

The difference between the gate array non-contact semiconductor channel memory structure provided in this embodiment and the vertical channel NAND structure in the prior art is mainly that the memory structure in this embodiment uses horizontal channels, and the gate charge capture structure also serves as the gate. The dielectric layer is located above the horizontal channel, and the gate electrodes are arranged in an array in the horizontal direction. This element structure is simpler. Because the memory cell uses the gate charge capture method, in order to improve the gate charge capture performance of the component, a two-dimensional The semiconductor material replaces the traditional silicon-doped material as the channel, and the nano-carbon tube is used as the gate electrode array, so that the conductivity of the channel is easier to control, so that the gate size can be reduced, the memory array density can be increased, and the performance of the memory device can be obtained. Further improvement. In the prior art, the vertical channel structure is used, and the channel structure is also relatively complicated. Usually, it includes multiple layers of films. There are buried insulation layers. Polycrystalline silicon thin films are usually used for vertical channels, which require good crystallinity and large crystal grains. At the same time, the thickness of polycrystalline silicon thin film channels must be as thin as possible, making it difficult to take into account the manufacturing process. Therefore, compared with the existing vertical channel type NAND, the gate array non-contact semiconductor channel memory structure provided in this embodiment has a simpler structure, and the component performance is also significantly improved.

The method for preparing the gate array non-contact semiconductor channel memory structure provided in this embodiment is further described in detail below with reference to the accompanying drawings.

Referring to FIGS. 2a-2g, this embodiment provides a method for preparing a gate array non-contact semiconductor channel memory structure, including the following steps: First, as shown in FIG. 2a, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be any suitable semiconductor material, such as a silicon substrate.

As shown in FIG. 2B, an insulating layer 200 is formed on the semiconductor substrate 100. The insulating layer 200 may be silicon oxide or other suitable insulating materials. For example, the insulating layer 200 may be formed by growing an oxide layer on a silicon substrate.

As shown in FIG. 2c, a semiconductor channel 300 is formed on the insulating layer 200 by using a two-dimensional semiconductor material. The two-dimensional semiconductor material used in the semiconductor channel 300 may be materials such as MoS ₂ , WS ₂ , ReS ₂ , and SnO. The method for forming the semiconductor channel 300 may be a deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable methods. Process.

As shown in FIG. 2d, a gate charge trapping structure 400 is formed on the semiconductor channel 300. The gate charge trapping structure 400 includes a tunnel layer 401, a charge trapping layer 402, and a blocking layer 403 in this order from bottom to top. In this embodiment, the tunnel layer 401 may be silicon oxide, the charge trapping layer 402 may be silicon nitride, and the barrier layer 403 may be silicon oxide. Forming the gate charge trapping structure 400 The method may be selected from one or more of CVD, MOCVD, ALD, molecular beam epitaxy (MBE), or other suitable processes. The thickness of the gate charge trapping structure 400 may be 2-50 nm.

As shown in FIG. 2e, a plurality of nano carbon tubes 501 of a nano carbon tube gate array 500 are formed on the gate charge trapping structure 400. A diameter range of each nano carbon tube 501 may be 0.75 to 3 nm, and a length range may be 100 nm to 50 μm. Preferably, a metallic carbon nanotube is used. The method for forming the plurality of nano carbon tubes 501 may be an arc method, a laser evaporation method, a chemical vapor deposition method, a pyrolysis polymerization method, or the like.

Then, as shown in FIG. 2f, a passivation layer 503 is covered on the plurality of nano carbon tubes 501. Specifically, the material of the passivation layer 503 may be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the passivation layer 503 can be designed according to actual needs. The passivation layer 503 should completely cover and cover the surface of each of the carbon nanotubes 501 to achieve isolation of the carbon nanotubes 501 from the surrounding environment. The method for forming the passivation layer 503 may be selected from one or more of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, atomic layer deposition, or other suitable processes.

Finally, as shown in FIG. 2g, a plurality of gate contact electrodes 502 respectively leading to the plurality of nano carbon tubes 501 are formed, and the two ends of the nano carbon tube gate array 500 are respectively connected to the semiconductor channel 300. The source contact electrode 600 and the drain contact electrode 700.

Specifically, the method for forming a plurality of gate contact electrodes 502 may include the steps of etching the passivation layer 503 to form a plurality of through holes to expose the plurality of nano carbon tubes 501 respectively, and then filling the through holes with a conductive material. A plurality of gate contact electrodes 502 are formed. The method of forming the source contact electrode 600 and the drain contact electrode 700 may include the steps of: etching openings at both ends of the nano carbon tube gate array 500 to expose the top of the semiconductor channel 300, and then filling the openings with conductive material, A source contact electrode 600 and a drain contact electrode 700 are formed. The method for etching through holes or openings may be dry etching, atomic layer etching (ALE), or other suitable methods. The gate contact electrode 502, the source contact electrode 600, and the drain contact electrode 700 may be made of conductive materials such as Ti, Al, Ni, Au, or other suitable metal contact materials and structures.

In this embodiment, when a two-dimensional semiconductor material is used to form the semiconductor channel 300 on the insulating layer 200, a plurality of semiconductor channels 300 may be formed at the same time. The plurality of semiconductor channels 300 may be arranged in an array. The width of each semiconductor channel 300 may be 2-50 nm. The plurality of semiconductor channels 300 may be filled with a dielectric material to achieve isolation. When a plurality of nano carbon tubes 501 of a nano carbon tube gate array 500 are formed on the gate charge trapping structure 400, a plurality of groups of nano carbon tubes are arranged according to the positions of the plurality of semiconductor channels 300, so that each group is memorized. The carbon nanotubes 501 of the cell string are arranged on the corresponding semiconductor channel 300. The number of nanometer carbon tubes 501 of each group of memory cell strings can be designed according to actual needs. For example, one string selects the gate nanometer carbon tube and one ground selects the gate nanometer carbon tube, and the word line gate nanometer. The number of carbon tubes can be 24, 32, 48 or more.

In summary, the gate array non-contact semiconductor channel memory structure of the present invention uses a gate charge trapping method to replace the traditional silicon-doped channel with a two-dimensional semiconductor material channel, which makes the charge easier to control and improves. The gate charge capture performance adopts a metal nano carbon tube gate array, which significantly reduces the gate size. Compared with the existing vertical channel NAND structure, the present invention further improves the element performance and the element structure is further simplified. Memory array density is increased. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can work without departing from the spirit and scope of the present invention. Next, the above embodiments are modified or changed. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims (12)

A gate array non-contact semiconductor channel memory structure includes: a semiconductor substrate; an insulating layer on the semiconductor substrate; a semiconductor channel on the insulating layer using a two-dimensional semiconductor material; a gate charge trapping structure located in The semiconductor channel includes a tunnel layer, a charge trapping layer, and a barrier layer in order from bottom to top; a nano carbon tube gate array, which is located above the gate charge trapping structure, includes a plurality of nano carbon tubes, and each of which leads to the Multiple gate contact electrodes of multiple carbon nanotubes; source contact electrodes and drain contact electrodes are respectively located at both ends of the nano carbon tube gate array and are respectively connected to the semiconductor channel, wherein the gate charge trapping structure The material of the tunnel layer is silicon oxide, the material of the charge trapping layer is silicon nitride, and the material of the barrier layer is silicon oxide. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein the semiconductor substrate is a silicon substrate. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein the insulating layer is silicon oxide. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein the two-dimensional semiconductor material used for the semiconductor channel is MoS ₂ , WS ₂ , ReS ₂ or SnO. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein the nano carbon tube gate array adopts a metallic nano carbon tube, and each of the nano carbon tubes has a diameter of 0.75 to 3 nm and a length It is 100 nm to 50 μm. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein a surface of a plurality of nano carbon tubes of the nano carbon tube gate array is covered with a passivation layer. The gate array non-contact semiconductor channel memory structure according to claim 1, wherein the gate array non-contact semiconductor channel memory structure includes a plurality of the semiconductor channels, and each of the semiconductor channels corresponds to a group of memory cells. The nano carbon tube gate array includes a plurality of sets of nano carbon tubes respectively corresponding to a plurality of sets of memory cell strings; the nano carbon tubes of each set of memory cell strings are arranged on a corresponding semiconductor channel and include a plurality of word lines The gate nanometer carbon tube, the string selection gate nanometer carbon tube, and the ground selection gate nanometer carbon tube, wherein the string selection gate nanometer carbon tube and the ground selection gate nanometer carbon tube are respectively located in multiple characters. Wire gate ends of carbon nanotubes. A method for preparing a gate array non-contact semiconductor channel memory structure includes the following steps: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a semiconductor channel using a two-dimensional semiconductor material on the insulating layer; A gate charge trapping structure is formed on the semiconductor channel, and the gate charge trapping structure includes a tunnel layer, a charge trapping layer, and a barrier layer in order from bottom to top; a plurality of nanometer carbon nanotube gate arrays are formed on the gate charge trapping structure. Carbon nanotubes; covering the plurality of nano carbon tubes with a passivation layer; forming a plurality of gate contact electrodes respectively leading out of the plurality of nano carbon tubes; and being respectively located at both ends of the nano carbon tube gate array and A source contact electrode and a drain contact electrode connected to the semiconductor channel. According to the method for manufacturing a gate array non-contact semiconductor channel memory structure according to claim 8, when a two-dimensional semiconductor material is used to form a semiconductor channel on the insulating layer, a plurality of semiconductor channels are simultaneously formed. The method for preparing a gate array non-contact semiconductor channel memory structure according to claim 9, wherein when a plurality of nano carbon tubes of a nano carbon tube gate array are formed on the gate charge trapping structure, Multiple sets of nano carbon tubes are arranged at the positions of each semiconductor channel, so that each group of nano carbon tubes is located above the corresponding semiconductor channel. The method for preparing a gate array non-contact semiconductor channel memory structure according to claim 8, wherein the method for forming a plurality of gate contact electrodes includes the step of: etching the passivation layer to form a plurality of through holes to expose the respectively A plurality of nano carbon tubes are then filled with a conductive material in the through holes to form a plurality of gate contact electrodes. The method for preparing a gate array non-contact semiconductor channel memory structure according to claim 8, wherein the method of forming the source contact electrode and the drain contact electrode includes the steps of: at both ends of the nano carbon tube gate array The opening is etched to expose the top of the semiconductor channel, and then a conductive material is filled in the opening to form a source contact electrode and a drain contact electrode.