TWI611563B - A nano-tube memory structure and the method for preparing the same - Google Patents

Abstract

The invention provides a nanometer tube memory structure and a manufacturing method thereof. The structure includes: a semiconductor substrate having a heavily doped epitaxial layer on a surface; a first isolation dielectric layer on the semiconductor substrate; a ground selection gate electrode layer; Word line gate electrode layer, string selection gate electrode layer, multilayer second isolation dielectric layer between ground selection gate electrode layer, word line gate electrode layer and string selection gate electrode layer; select gate electrode layer, word The gate electrode layer and the semiconductor channel of the string selection gate electrode layer; the gate dielectric layer wrapped on the side wall of the semiconductor channel, and the semiconductor channel is a semiconductor nanotube on the heavily doped epitaxial layer. The memory structure of the present invention uses a semiconductor nano tube epitaxially grown on a heavily doped epitaxial layer as a vertical channel. Compared with the existing vertical channel NAND structure, the element structure is further simplified, the manufacturing process is easy to control, and the product The yield is high.

Description

Nano tube memory structure and manufacturing method thereof

The invention relates to the technical field of integrated circuit, in particular to a nano tube memory structure and a manufacturing method thereof.

For different architectures of NAND memory, the material of the memory layer can be divided into three-dimensional floating gate memory and three-dimensional charge trapping memory. For the former three-dimensional floating gate memory, because the polycrystalline silicon floating gate is used as the memory layer, the memory cell area is larger, and the process is more difficult when more layers of memory cells are stacked. Therefore, the peripheral circuit is mainly placed under the memory array. To achieve area reduction. For the latter three-dimensional charge trapping memory, it can be divided into vertical gate type and vertical channel type. The three-dimensional charge trapping flash memory structure based on the vertical gate structure is difficult to manufacture in the vertical channel type, and its mass production has not been announced. Vertical channel 3D charge trapping memory is the earliest flash memory product to achieve mass production. In August 2013, Samsung Electronics introduced the first 24-layer 3D vertical channel charge trapping 3D memory. July 2014 The second generation of 32-layer 128Gb products was launched in January, and 48-layer 256Gb products were launched in 2015.

The vertical channel type three-dimensional charge trapping flash memory introduced by Samsung Electronics uses vertical polycrystalline silicon cylinders as channels, and multiple layers of gates surround the polycrystalline silicon cylinders. Each layer of gates serves as a word line, so that the word line becomes horizontal. Layer, the bit line is connected on top of the vertical polycrystalline silicon cylinder. The common source lines are drawn out one by one by making heavily doped regions on the substrate. Gate mining A charge trapping method is used for memory. A tunneling layer, a charge trapping layer, and a blocking layer are provided between the polycrystalline silicon channel and the gate metal. For a detailed description of the element structure, please refer to the patent document with patent publication number CN104425511A.

The key technologies of this vertical channel type 3D charge trapping flash memory are ultra deep hole etching and high quality thin film process. The 32-layer ultra-deep hole has an aspect ratio close to 30: 1, and the diameter difference between the upper and lower holes must be less than 10-20nm. The gate dielectric multilayer film not only requires the thickness of the top layer and the bottom layer to be substantially the same, but also puts forward high requirements for the uniformity of the components. The channel material is generally a polycrystalline silicon thin film, which requires good crystallinity and large crystal grains, and also needs a low defect density interface with the gate dielectric. As a kind of charge trapping memory, there is almost no coupling effect between memory cells. Programming and erase operations use FN tunneling of electrons and holes, respectively. In order to increase the erasing speed, the tunneling layer usually uses a stacked structure based on silicon oxide and silicon oxynitride materials. The memory layer is generally a high trap density material based on silicon nitride. In order to reduce the gate reverse injection, the barrier layer uses materials such as silicon oxide or aluminum oxide.

However, in the existing vertical channel type three-dimensional charge trapping memory, the material of the channel of the device is polycrystalline silicon film, which requires good crystallinity and large crystal grains. At the same time, the thickness of the channel of the polycrystalline silicon film must be as thin as possible, and it is difficult to balance the manufacturing process. , Affecting product yield.

In view of the foregoing prior art, an object of the present invention is to provide a nano tube memory structure and a manufacturing method thereof, which are used to solve various problems in the prior art.

In order to achieve the above object and other related objects, the present invention provides a nano tube memory structure including: a semiconductor substrate, the surface of the semiconductor substrate having a heavily doped epitaxial layer; A first isolation dielectric layer on the semiconductor substrate; a ground selection gate electrode layer on the first isolation dielectric layer; a word line gate electrode layer on the ground selection gate electrode layer; The string selection gate electrode layer is located above the word line gate electrode layer; the multilayer second isolation dielectric layer is interposed between the ground selection gate electrode layer, the word line gate electrode layer, and the string selection gate electrode layer; a semiconductor A channel in contact with the heavily doped epitaxial layer and penetrating through the ground selection gate electrode layer, the word line gate electrode layer, and the string selection gate electrode layer; a gate dielectric layer wrapped on a sidewall of the semiconductor channel, Between the semiconductor channel and the string selection gate electrode layer, the word line gate electrode layer, and the ground selection gate electrode layer, a tunnel layer, a charge trapping layer, and A barrier layer; wherein the semiconductor channel is a semiconductor nano tube.

Optionally, the semiconductor channel is a III-V single crystal semiconductor nano tube.

Optionally, the semiconductor channel is a nano carbon tube.

Optionally, the semiconductor substrate includes a doped substrate having a second conductivity type and the heavily doped epitaxial layer of a first conductivity type grown on a surface of the doped substrate.

Optionally, the doping concentration of the heavily doped epitaxial layer is 10 ¹⁸ -5 × 10 ¹⁹ / cm ³ .

Optionally, the thickness of the heavily doped epitaxial layer is 1-5 μm.

Optionally, the semiconductor channel has the same conductivity type as the heavily doped epitaxial layer.

Optionally, a maximum width of a cross section of the semiconductor channel parallel to the semiconductor substrate is 2-50 nm.

Optionally, a bit line contact and a bit line electrode layer connected to the bit line contact are provided on the top of the semiconductor channel.

Further optionally, the nanometer tube memory structure includes a third isolation dielectric layer, the third isolation dielectric layer is located between the bit line electrode layer and the string selection gate electrode layer, and The top of the semiconductor channel is wrapped, and the bit line contact passes through the third isolation dielectric layer and contacts the top of the semiconductor channel.

Further optionally, the material of the bit line contact includes one or more of Ti, Al, Ni, and Au.

Optionally, the memory structure includes a plurality of the word line gate electrode layers, and the second isolation dielectric layer is provided between the plurality of word line gate electrode layers.

Optionally, in the gate dielectric layer, a material of the tunnel layer is silicon oxide, a material of the charge trapping layer is silicon nitride, and a material of the barrier layer is silicon oxide.

Optionally, the thickness of the gate dielectric layer is 2-50 nm.

In order to achieve the above object and other related objects, the present invention also provides a nanometer tube memory structure including: a heavily doped epitaxial layer as a common source line; and a ground disposed on the heavily doped epitaxial layer in order. A selection line, a multilayer word line, and a string selection line; and a plurality of semiconductor channels in contact with the heavily doped epitaxial layer and penetrating through the ground selection line, the multilayer word line, and the string selection line, each on the semiconductor channel A corresponding bit line contact and a bit line connected to the corresponding bit line contact are provided, wherein the semiconductor channel is a semiconductor nano tube.

Optionally, the semiconductor channel is a III-V single crystal semiconductor nano tube.

Optionally, the semiconductor channel is a nano carbon tube.

In order to achieve the above object and other related objects, the present invention also provides a nano tube A method for manufacturing a memory structure includes the steps of: providing a semiconductor substrate having a heavily doped epitaxial layer on a surface; forming a first isolation dielectric layer on the heavily doped epitaxial layer; A ground selection gate electrode layer, a word line gate electrode layer, a string selection gate electrode layer, and a second isolation dielectric interposed between the ground selection gate electrode layer, the word line gate electrode layer, and the string selection gate electrode layer are formed on the layers. A through hole formed by lithography and etching, the through hole penetrating downward through the string selection gate electrode layer, word line gate electrode layer, ground selection gate electrode layer, interposed between the ground selection gate electrode layer, word line A gate electrode layer, a second isolation dielectric layer between the gate electrode layers, and a first isolation dielectric layer, and exposing the heavily doped epitaxial layer; forming a gate dielectric in the via hole Layer, so that the gate dielectric layer covers the bottom surface and sides of the through hole, and the gate dielectric layer includes a tunnel layer, a charge trapping layer, and a barrier layer in a direction from the center of the through hole outward. ; Etching the gate dielectric layer to form an opening at the bottom of the through hole to expose the A heavily doped epitaxial layer; in the opening is exposed by the surface of a heavily doped semiconductor epitaxial layer is grown as a semiconductor nanotube channel filling the through hole.

Optionally, growing a semiconductor nano tube includes the following steps: depositing a catalyst on the surface of the heavily doped epitaxial layer exposed through the opening, and then epitaxially growing a group III-V single crystal semiconductor nano with the aid of the catalyst. Meter tube.

Further optionally, the material of the catalyst is selected from one or more of Au, Fe, Pt, Fe-Ni, Co-Ni, FeSi, NiB.

Further optionally, the method of epitaxially growing the III-V single crystal semiconductor nanometer tube The method is chemical vapor deposition of metal organic compounds or molecular beam epitaxy.

Further optionally, after the epitaxial growth is completed, the catalyst remains on the top of the III-V single crystal semiconductor nano tube as a part of the semiconductor channel.

Optionally, growing the semiconductor nano tube includes the following steps: depositing catalytic particles on the surface of the heavily doped epitaxial layer exposed through the opening, and then epitaxially growing the nano carbon tube with the assistance of the catalytic particles.

Further optionally, the material of the catalytic particles is selected from one or more of Fe, Co, Ni, Cu, Au, Ag, Pt, and Pd.

Further optionally, the method for epitaxially growing the carbon nanotubes is chemical vapor deposition.

Further optionally, after the epitaxial growth is completed, the catalytic particles remain on the top of the nano carbon tube as a part of the semiconductor channel.

Optionally, providing a semiconductor substrate having a heavily doped epitaxial layer on the surface includes the following steps: providing a doped substrate having a second conductivity type; and epitaxially growing on the doped substrate of the second conductivity type to form a first conductivity Type of heavily doped epitaxial layer.

Optionally, a plurality of word line gate electrode layers are formed, and the second isolation dielectric layer is formed between the plurality of word line gate electrode layers.

Optionally, the method for forming the first isolation dielectric layer, the ground selection gate electrode layer, the word line gate electrode layer, the string selection gate electrode layer, and the second isolation dielectric layer is selected from the group consisting of chemical vapor deposition and physical vapor phase. One or more of deposition, chemical vapor deposition of metal organic compounds, atomic layer deposition.

Optionally, the maximum width of the through-hole opening is 2-50 nm.

Optionally, the method for forming the gate dielectric layer is selected from the group consisting of chemical vapor deposition, gold It belongs to one or more of chemical vapor deposition, atomic layer deposition, and molecular beam epitaxy of organic compounds.

Optionally, the method for etching the gate dielectric layer to form an opening at the bottom of the via is dry etching or atomic layer deposition.

Optionally, the manufacturing method further includes the steps of: forming a third isolation dielectric layer covering the top of the semiconductor channel, forming a contact via in the third isolation dielectric layer to expose the top of the semiconductor channel, A bit line contact is formed in the contact via, a bit line electrode layer is formed on the third isolation dielectric layer where the bit line contact is formed, and the bit line electrode layer is in contact with the bit line contact through the bit line contact. The semiconductor channel is electrically connected.

Further optionally, the method for forming the third isolation dielectric layer is selected from one or more of chemical vapor deposition, physical vapor deposition, chemical vapor deposition of metal organic compounds, and atomic layer deposition.

As described above, the nanometer tube memory structure of the present invention and the manufacturing method thereof have the following beneficial effects: The technical solution of the present invention uses a heavily doped epitaxial layer as a common source line, and a ground selection line, Multi-layer word lines and string selection lines, vertical channels running through ground selection lines, multi-layer word lines and string selection lines use semiconductor nano tubes grown on the heavily doped epitaxial layer, and memory cells use gate charge trapping Memory, compared with the existing vertical channel NAND structure, the component structure has been further simplified, the manufacturing process is easy to control, and the product yield is high.

100‧‧‧ semiconductor substrate

101‧‧‧ heavily doped epitaxial layer

102‧‧‧ doped substrate

201‧‧‧The first isolation dielectric layer

202‧‧‧Second isolation dielectric layer

203‧‧‧Third isolation dielectric layer

301‧‧‧ground selection gate electrode layer

401‧‧‧Word line gate electrode layer

501‧‧‧string selection gate electrode layer

600‧‧‧Gate dielectric layer

601‧‧‧ Tunnel layer

602‧‧‧ charge trapping layer

603‧‧‧ barrier

701‧‧‧Semiconductor Nanotube

702‧‧‧ catalyst

801‧‧‧bit line electrode layer

802‧‧‧bit line contact

FIG. 1 is a schematic diagram of a nanometer tube memory structure according to an embodiment of the present invention.

Figures 2a-2g are schematic diagrams illustrating a manufacturing process of a nanometer tube memory structure according to an embodiment of the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the illustrations provided in the following embodiments are only a schematic illustration of the basic idea of the present invention, and the drawings only show the components related to the present invention and not the number, shape and For size drawing, the type, quantity, and proportion of each component can be changed at will in actual implementation, and the component layout type may be more complicated.

This embodiment provides a structure and a manufacturing method of a memory cell string that can be applied to a vertical channel type three-dimensional charge trapping NAND memory. Multiple memory cell strings can form a memory array. The memory cell string adopts a form in which a plurality of gateless contactless switching transistors share a vertical channel, and a plurality of gateless contactless switching transistors, that is, a ground selection transistor whose gate is connected to a ground selection line (GSL), The gates are respectively connected to a plurality of gate-controlled charge trapping memory cells of a plurality of word lines (WL), and the string selection transistors are connected to a string selection line (SSL).

Please refer to FIG. 1. This embodiment provides a nano tube memory structure that can be used as a memory cell string, which includes a semiconductor substrate 100 having a heavily doped epitaxial layer on the surface. 101; a first isolation dielectric layer 201 on the semiconductor substrate 100; a ground selection gate electrode layer 301 on the first isolation dielectric layer 201; a word line gate electrode layer 401 on the ground Select gate electrode layer 301; string select gate electrode layer 501 above the word line gate electrode layer 401; a plurality of second isolation dielectric layers 202 interposed between the ground select gate electrode layer 301 and the word line gate Between the electrode layer 401 and the string selection gate electrode layer 501; a semiconductor channel in contact with the heavily doped epitaxial layer 101 and penetrating the ground selection gate electrode layer 301, the word line gate electrode layer 401, and the string selection gate electrode layer 501; a gate dielectric layer 600 is wrapped on a sidewall of the semiconductor channel (not shown in the figure), interposed between the semiconductor channel and the string selection gate electrode layer 501, a word line gate electrode layer 401, and The ground selection gate electrode layer 301 includes a tunnel layer 601, a charge trapping layer 602, and a blocking layer 603 in this order in a direction outward from the center of the semiconductor channel. The semiconductor channel is a semiconductor nano tube 701, such as a III-V single crystal semiconductor nano tube or a nano carbon tube. The catalyst 702 used to form the semiconductor nano tube 701 may remain on top of the semiconductor nano tube 701 as part of the semiconductor channel.

In this embodiment, the semiconductor substrate 100 may have a double-layer material structure, a multilayer material structure, or other suitable structures. Preferably, the semiconductor substrate 100 may include a doped substrate 102 having a second conductivity type and grown on The heavily doped epitaxial layer 101 of the first conductivity type on the surface of the doped substrate 102. The doped substrate 102 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or other substrates suitable for growing epitaxial layers on the surface. The semiconductor channel has the same conductivity type as the heavily doped epitaxial layer 101 and is also a first conductivity type. The first conductivity type is opposite to the second conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type. The doping concentration of the heavily doped epitaxial layer 101 may be 10 ¹⁸ -5 × 10 ¹⁹ / cm ³ . The thickness of the heavily doped epitaxial layer 101 may be 1-5 μm.

In this embodiment, the memory cell string structure may include multiple layers of the word line gate. The electrode layer 401 is provided with the second isolation dielectric layer 202 between the multiple word line gate electrode layers 401 to achieve isolation. The present invention does not limit the number of layers of the word line gate electrode layer 401, and for example, it may be 24 layers, 32 layers, 48 layers or more.

In this embodiment, a maximum width of a cross section of the semiconductor channel parallel to the semiconductor substrate 100 is 2-50 nm.

A bit line contact 802 and a bit line electrode layer 801 connected to the bit line contact 802 may be provided on the top of the semiconductor channel. The bit line electrode layer 801 may be a patterned bit line. A third isolation dielectric layer 203 may be provided between the bit line electrode layer 801 and the string selection gate electrode layer 501 for isolation. The third isolation dielectric layer 203 may wrap the top of the semiconductor channel. A bit line contact 802 contacts the top of the semiconductor channel through the third isolation dielectric layer 203.

Specifically, a material of the first isolation dielectric layer 201, the second isolation dielectric layer 202, and the third isolation dielectric layer 203 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thicknesses of the first isolation dielectric layer 201, the second isolation dielectric layer 202, and the third isolation dielectric layer 203 may be different.

Specifically, the ground selection gate electrode layer 301 may include a conductive material such as a metal or a metal silicide. For example, the ground selection gate electrode layer 301 may include titanium, tantalum, tungsten, cobalt, titanium nitride, tantalum nitride, titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide, nickel silicide, or the like. The word line gate electrode layer 401 may include a metal silicide material. For example, the word line gate electrode layer 401 may include titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide, nickel silicide, or the like. The string selection gate electrode layer 501 may include a conductive material such as a metal or a metal silicide. For example, the string selection gate electrode layer 501 may include titanium, tantalum, tungsten, cobalt, titanium nitride, tantalum nitride, Titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide, nickel silicide, or the like. The bit line electrode layer 801 may include a conductive material, such as Ti, Al, Ni, Au, Cu, and the like. The bit line contact 802 may include one or more materials of Ti, Al, Ni, Au, or other suitable metal contact materials and structures.

Specifically, the gate dielectric layer 600 is an insulating material, for example, it may be an ONO dielectric material, that is, silicon oxide, silicon nitride, and silicon oxide. The tunnel layer 601 may include silicon oxide, the charge trapping layer 602 may include silicon nitride, and the blocking layer 603 may include silicon oxide or a high-k dielectric material having a high dielectric constant. The thickness of the gate dielectric layer 600 may be 2-50 nm.

In the above structure, the heavily doped epitaxial layer 101 can be used as the common source line (CSL) of the memory, the ground selection gate electrode layer 301 can be used as the ground selection line (GSL), and the multilayer word line gate electrode layer 401 can be used as multiple The word line (WL) and the string selection gate electrode layer 501 can serve as a string selection line (SSL). In this way, the common source lines, ground selection lines, and multilayer word lines are all horizontal layers. A plurality of vertical semiconductor channel arrays are arranged and interspersed in these horizontal layers. Bit lines (BL) are connected at the top of these semiconductor channels, that is, Can form a three-dimensional memory array.

This embodiment also provides a nano tube memory structure, which can be used as a memory array based on the above-mentioned memory cell string, including: a heavily doped epitaxial layer as a common source line, and sequentially disposed on the heavily doped epitaxial layer. Ground selection lines, multilayer word lines, and string selection lines thereon, and semiconductor channels that are in contact with the heavily doped epitaxial layer and pass through the ground selection lines, multilayer word lines, and string selection lines, wherein the semiconductor channels It is a semiconductor nano tube, such as a III-V single crystal semiconductor nano tube or a carbon nano tube. The nanometer tube memory structure may include a plurality of the semiconductor channels, and each semiconductor channel is provided with a corresponding bit line contact and a bit line connected to the corresponding bit line contact.

The structure of the nanometer tube memory provided in this embodiment is similar to the vertical communication in the prior art. The difference between the channel NAND structure is mainly that the common source line of the memory structure of this embodiment is a heavily doped epitaxial layer located under the semiconductor channel, and the common source line of the prior art usually needs to be formed on the substrate. In addition, the semiconductor channel of the memory structure of this embodiment uses a semiconductor nano tube, and the vertical channel structure of the prior art uses a polycrystalline silicon film, and the structure is also more complicated, usually including a multilayer film. There may be buried insulation layers and so on. The vertical channel uses a polycrystalline silicon thin film, which requires good crystallinity and large crystal grains. At the same time, the thickness of the polycrystalline silicon thin film channel must be as thin as possible, which is difficult to take into account. Therefore, compared with the existing vertical channel NAND, the memory cell string and the memory array provided in this embodiment have a simpler structure, and the corresponding manufacturing process is relatively simple and easy to control.

The method for manufacturing the nano tube memory structure provided in this embodiment is further described in detail below with reference to the accompanying drawings.

Referring to FIGS. 2a-2g, this embodiment provides a method for manufacturing a nanometer tube memory structure, including the following steps: First, as shown in FIG. 2a, a semiconductor substrate 100 having a heavily doped epitaxial layer 101 on a surface is provided. . Specifically, a doped substrate 102 having a second conductivity type may be provided first; then epitaxial growth is performed on the doped substrate 102 of the second conductivity type to form a heavily doped epitaxial layer 101 of a first conductivity type. The thickness of the heavily doped epitaxial layer 101 may be 1-5 μm, and the doping concentration may be 10 ¹⁸ -5 × 10 ¹⁹ / cm ³ .

As shown in FIG. 2b, a first isolation dielectric layer 201 is formed on the heavily doped epitaxial layer 101, and a ground selection gate electrode layer 301 and a word line gate electrode are formed on the first isolation dielectric layer 201. Layer 401, string selection gate electrode layer 501, and a second isolation dielectric layer 202 interposed between the ground selection gate electrode layer 301, word line gate electrode layer 401, and string selection gate electrode layer 501. In this embodiment, preferably, A multi-layer word line gate electrode layer 401 may be formed between the ground selection gate electrode layer 301 and a string selection gate electrode layer 501, and a second isolation dielectric layer 202 is formed between the multi-layer word line gate electrode layers 401 as isolation. Specifically, the method of forming the first isolation dielectric layer 201, the ground selection gate electrode layer 301, the word line gate electrode layer 401, the string selection gate electrode layer 501, and the second isolation dielectric layer 202 may be selected from a chemical vapor phase. One or more of deposition (CVD), physical vapor deposition (PVD), metal organic compound chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or other suitable processes.

As shown in FIG. 2c, a through hole is formed through lithography and etching, and the through hole penetrates the string selection gate electrode layer 501, the word line gate electrode layer 401, the ground selection gate electrode layer 301, and The ground selection gate electrode layer 301, the word line gate electrode layer 401, the second isolation dielectric layer 202 and the first isolation dielectric layer 201 between the string selection gate electrode layers 501, and the heavily doped epitaxial layer are made. 101 is exposed. Specifically, the maximum width of the through-hole opening may be 2-50 nm.

As shown in FIG. 2d, a gate dielectric layer 600 is formed in the via hole, so that the gate dielectric layer 600 covers the bottom surface and the side surface of the via hole. The gate dielectric layer 600 is formed by The through hole center includes a tunnel layer 601, a charge trapping layer 602, and a blocking layer 603 in the outward direction. Specifically, the tunnel layer 601 may be silicon oxide, the charge trapping layer 602 may be silicon nitride, and the blocking layer 603 may be silicon oxide. The method for forming the gate dielectric layer 600 may be selected from one or more of CVD, MOCVD, ALD, molecular beam epitaxy (MBE), or other suitable processes. The thickness of the formed gate dielectric layer 600 may be 2-50 nm.

As shown in FIG. 2e, the gate dielectric layer 600 is etched to form an opening at the bottom of the through hole to expose the heavily doped epitaxial layer 101. Specifically, a method of etching the gate dielectric layer 600 to form an opening at the bottom of the through hole may be dry etching or atomic layer etching (ALE).

Then, the surface of the heavily doped epitaxial layer 101 exposed through the opening is grown. The semiconductor nano tube 701 serves as a semiconductor channel filling the through hole.

In this embodiment, the semiconductor nanotube 701 is grown using a catalyst-assisted epitaxial growth method.

As a preferred solution of this embodiment, a III-V group single crystal semiconductor nano tube is grown as the semiconductor nano tube 701. As shown in FIG. 2f, a catalyst 702 may be deposited on the surface of the heavily doped epitaxial layer 101 exposed through the opening. The catalyst 702 may be granular or other suitable shapes, and the material may be selected from one or more of Au, Fe, Pt, Fe-Ni, Co-Ni, FeSi, and NiB. Then, with the assistance of the catalyst 702, a III-V single crystal semiconductor nano tube is epitaxially grown vertically upward. The III-V single crystal semiconductor nano tube grown in this embodiment is an InAs single crystal nano tube. The method for epitaxially growing the III-V single crystal semiconductor nano tube is MOCVD, MBE, or other suitable processes. During epitaxial growth, the catalyst 702 will be slowly topped by the material that grows vertically upwards. After the growth is finally completed, the catalyst 702 can remain on the top of the semiconductor nanotube 701 as a part of the semiconductor channel, such as Figure 2g.

As another preferred solution of this embodiment, a carbon nanotube can also be grown as the semiconductor nanotube 701. A catalyst particle 702 may be deposited on the surface of the heavily doped epitaxial layer 101 exposed through the opening as a catalyst 702. The material of the catalyst particle may be selected from Fe, Co, Ni, Cu, Au, Ag, Pt, and Pd. One or more of them. Then, carbon nanotubes were epitaxially grown vertically with the aid of catalytic particles. The method for epitaxially growing the carbon nanotube is CVD or other suitable processes. During epitaxial growth, the catalytic particles are slowly topped by a material that grows vertically upwards. After the growth is finally completed, the catalytic particles can remain on the top of the carbon nanotube as a part of the semiconductor channel.

Optionally, as shown in FIG. 1, after forming the semiconductor channel, the method further includes: Forming a third isolation dielectric layer 203 covering the top of the semiconductor channel, forming a contact via in the third isolation dielectric layer 203 to expose the top of the semiconductor channel, and forming a bit line in the contact via A contact 802, a bit line electrode layer 801 is formed on the third isolation dielectric layer 203 on which the bit line contact 802 is formed, so that the bit line electrode layer 801 is electrically connected to the semiconductor channel through the bit line contact . The bit line electrode layer 801 may be patterned to form a bit line. The method for forming the third isolation dielectric layer 203 may be selected from one or more of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, atomic layer deposition, or other suitable processes.

In addition, a plurality of through holes can be formed simultaneously by using the above method, and a plurality of semiconductor channels and a gate dielectric layer 600 surrounding a sidewall thereof can be grown in the plurality of through holes, thereby forming a memory array.

In summary, the nanometer tube memory structure of the present invention uses a heavily doped epitaxial layer as a common source line, and a ground selection line, a multilayer word line, and a string selection line are provided thereon, and the ground selection line and the multilayer The vertical channels of the word line and the string selection line use I semiconductor nano tubes grown on the heavily doped epitaxial layer. The memory cells are memorized by gate charge capture. Compared with the existing vertical channel NAND structure, the elements The structure is further simplified, the manufacturing process is easy to control, and the product yield is high. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

100‧‧‧ semiconductor substrate

101‧‧‧ heavily doped epitaxial layer

102‧‧‧ doped substrate

201‧‧‧The first isolation dielectric layer

202‧‧‧Second isolation dielectric layer

301‧‧‧ground selection gate electrode layer

401‧‧‧Word line gate electrode layer

501‧‧‧string selection gate electrode layer

600‧‧‧Gate dielectric layer

601‧‧‧ Tunnel layer

602‧‧‧ charge trapping layer

603‧‧‧ barrier

701‧‧‧Semiconductor Nanotube

702‧‧‧ catalyst

801‧‧‧bit line electrode layer

802‧‧‧bit line contact

Claims (33)

A nanometer tube memory structure includes: a semiconductor substrate having a heavily doped epitaxial layer on the surface of the semiconductor substrate; a first isolation dielectric layer on the semiconductor substrate; and a ground selection gate electrode layer on the semiconductor substrate. Above a first isolation dielectric layer; a word line gate electrode layer located above the ground selection gate electrode layer; a string selection gate electrode layer located above the word line gate electrode layer; a multilayer second isolation dielectric layer Between the ground selection gate electrode layer, the word line gate electrode layer, and the string selection gate electrode layer; a semiconductor channel in contact with the heavily doped epitaxial layer and passing through the ground selection gate electrode layer and word line A gate electrode layer and a string selection gate electrode layer; a gate dielectric layer is wrapped on a side wall of the semiconductor channel, interposed between the semiconductor channel and the string selection gate electrode layer, a word line gate electrode layer, and a ground selection gate Between the electrode layers, a tunnel layer, a charge trapping layer, and a blocking layer are sequentially included in a direction outward from the center of the semiconductor channel; wherein the semiconductor channel is a semiconductor nano tube and the semiconductor substrate includes a second conductive layer The type doped substrate and grown on the doped surface of the substrate of the first conductivity type heavily doped epitaxial layer. The nanometer tube memory structure according to claim 1, wherein the semiconductor channel is a III-V single crystal semiconductor nanometer tube. The nanometer tube memory structure according to claim 1, wherein the semiconductor channel is a nanometer carbon tube. The nanometer tube memory structure according to claim 1, wherein a doping concentration of the heavily doped epitaxial layer is 10 ¹⁸ -5 × 10 ¹⁹ / cm ³ . The nanometer tube memory structure according to claim 1, wherein a thickness of the heavily doped epitaxial layer is 1-5 μm. The nanometer tube memory structure according to claim 1, wherein the semiconductor channel has the same conductivity type as the heavily doped epitaxial layer. The nanometer tube memory structure according to claim 1, wherein a maximum width of a cross section of the semiconductor channel parallel to the semiconductor substrate is 2-50 nm. The nanometer tube memory structure according to claim 1, wherein a bit line contact layer and a bit line electrode layer connected to the bit line contact are provided on top of the semiconductor channel. The nanometer tube memory structure according to claim 8, further comprising a third isolation dielectric layer, the third isolation dielectric layer being located between the bit line electrode layer and the string selection gate electrode layer, and The top of the semiconductor channel is wrapped, and the bit line contact passes through the third isolation dielectric layer and contacts the top of the semiconductor channel. The nanometer tube memory structure according to claim 8, wherein the material in contact with the bit line comprises one or more of Ti, Al, Ni, and Au. The nanometer tube memory structure according to claim 1, wherein the memory structure includes a plurality of the word line gate electrode layers, and the second isolation dielectric layer is provided between the plurality of word line gate electrode layers. . The nanometer tube memory structure according to claim 1, wherein in the gate dielectric layer, a material of the tunnel layer is silicon oxide, and a material of the charge trapping layer is silicon nitride, The material of the barrier layer is silicon oxide. The nanometer tube memory structure according to claim 1, wherein a thickness of the gate dielectric layer is 2-50 nm. A nanometer tube memory structure, comprising: a heavily doped epitaxial layer as a common source line; a ground selection line, a multi-layer word line, and a string selection disposed on the heavily doped epitaxial layer in order. A plurality of semiconductor channels in contact with the heavily doped epitaxial layer and penetrating the ground selection line, the multilayer word line, and the string selection line, each of which has a corresponding bit line contact, and A bit line connected in contact with the corresponding bit line, wherein the semiconductor channel is a semiconductor nano tube. The nanometer tube memory structure according to claim 14, wherein the semiconductor channel is a III-V single crystal semiconductor nanometer tube. The nanometer tube memory structure according to claim 14, wherein the semiconductor channel is a carbon nanotube. A method for manufacturing a nanometer tube memory structure includes the steps of: providing a semiconductor substrate having a heavily doped epitaxial layer on a surface; forming a first isolation dielectric layer on the heavily doped epitaxial layer; An isolation dielectric layer is formed with a ground selection gate electrode layer, a word line gate electrode layer, a string selection gate electrode layer, and a first interposed between the ground selection gate electrode layer, the word line gate electrode layer, and the string selection gate electrode layer. Two isolation dielectric layers; through holes are formed by lithography and etching, the through holes penetrating downward through the string selection gate electrode layer, the word line gate electrode layer, the ground selection gate electrode layer, and the ground selection gate electrode Layer, word line A gate electrode layer, a second isolation dielectric layer between the gate electrode layers, and a first isolation dielectric layer, and exposing the heavily doped epitaxial layer; forming a gate dielectric in the via hole Layer, so that the gate dielectric layer covers the bottom surface and sides of the through hole, and the gate dielectric layer includes a tunnel layer, a charge trapping layer, and a barrier layer in a direction from the center of the through hole outward. ; Etching the gate dielectric layer to form an opening at the bottom of the through hole to expose the heavily doped epitaxial layer; growing a semiconductor nano tube as a fill on the surface of the heavily doped epitaxial layer exposed through the opening; A semiconductor channel of the through hole. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein growing a semiconductor nanometer tube comprises the step of: depositing a catalyst on the surface of the heavily doped epitaxial layer exposed through the opening, and then depositing the catalyst on the catalyst Assisted epitaxial growth of III-V single crystal semiconductor nanotubes. The method for manufacturing a nanometer tube memory structure according to claim 18, wherein a material of the catalyst is selected from one or more of Au, Fe, Pt, Fe-Ni, Co-Ni, FeSi, and NiB. The method for manufacturing a nanometer tube memory structure according to claim 18, wherein a method of epitaxially growing the III-V single crystal semiconductor nanometer tube is metal organic compound chemical vapor deposition or molecular beam epitaxy. The method for manufacturing a nanometer tube memory structure according to claim 18, wherein after the epitaxial growth is completed, the catalyst remains on the top of the III-V single crystal semiconductor nanometer tube as a part of the semiconductor channel . The method for preparing a nanometer tube memory structure according to claim 17, wherein the growth half The conductive nano tube includes the steps of: depositing catalytic particles on the surface of the heavily doped epitaxial layer exposed through the opening, and then epitaxially growing a nano carbon tube with the assistance of the catalytic particles. The method for preparing a nanometer tube memory structure according to claim 22, wherein a material of the catalytic particles is selected from one or more of Fe, Co, Ni, Cu, Au, Ag, Pt, and Pd. The method for preparing a nanometer tube memory structure according to claim 22, wherein the method of epitaxially growing the nanometer carbon tube is chemical vapor deposition. The method of claim 22, wherein after the epitaxial growth is completed, the catalytic particles remain on top of the carbon nanotube as a part of the semiconductor channel. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein providing a semiconductor substrate having a heavily doped epitaxial layer on a surface comprises the steps of: providing a doped substrate having a second conductivity type; A heavily doped epitaxial layer of a first conductivity type is formed by epitaxial growth on a conductive type doped substrate. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein a plurality of the word line gate electrode layers are formed, and the second isolation dielectric layer is formed between the plurality of word line gate electrode layers. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein the first isolation dielectric layer, a ground selection gate electrode layer, a word line gate electrode layer, a string selection gate electrode layer, and a second isolation dielectric are formed. The method of the electrical layer is selected from one or more of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, and atomic layer deposition. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein a maximum width of the through hole opening is 2-50 nm. The method of claim 17, wherein the method for forming the gate dielectric layer is selected from the group consisting of chemical vapor deposition, metal organic compound chemical vapor deposition, atomic layer deposition, and molecular beam deposition. One or more of the crystals. The method for manufacturing a nanometer tube memory structure according to claim 17, wherein a method of etching the gate dielectric layer to form an opening at the bottom of the through hole is dry etching or atomic layer deposition. The method for manufacturing a nanometer tube memory structure according to claim 17, after forming the semiconductor channel, further comprising the steps of: forming a third isolation dielectric layer covering the top of the semiconductor channel; A contact via is formed in the isolation dielectric layer to expose the top of the semiconductor channel, a bit line contact is formed in the contact via, and a bit line electrode layer is formed on the third isolation dielectric layer where the bit line contact is formed. , Enabling the bit line electrode layer to be electrically connected to the semiconductor channel through the bit line contact. The method for manufacturing a nanometer tube memory structure according to claim 27, wherein the method for forming the third isolation dielectric layer is selected from the group consisting of chemical vapor deposition, physical vapor deposition, metal organic compound chemical vapor deposition, atom One or more of the layer depositions.