JP2010135471A - Bipolar field effect transistor and semiconductor integrated circuit apparatus - Google Patents

Bipolar field effect transistor and semiconductor integrated circuit apparatus Download PDF

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JP2010135471A
JP2010135471A JP2008308349A JP2008308349A JP2010135471A JP 2010135471 A JP2010135471 A JP 2010135471A JP 2008308349 A JP2008308349 A JP 2008308349A JP 2008308349 A JP2008308349 A JP 2008308349A JP 2010135471 A JP2010135471 A JP 2010135471A
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field effect
bipolar
effect transistor
gate electrode
film
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Naoki Harada
直樹 原田
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Fujitsu Ltd
富士通株式会社
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<P>PROBLEM TO BE SOLVED: To prepare various functions to a field effect transistor (FET) by controlling polarity not during manufacturing but in use, with respect to the bipolar field effect transistor and semiconductor integrated circuit apparatus. <P>SOLUTION: On a channel region provided on a substrate, a gate electrode is provided, which controls the carrier density of the channel region, and at the same time, a voltage applying means which changes the polarity of the transistor seen from the gate electrode is provided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a bipolar field effect transistor and a semiconductor integrated circuit device. For example, the present invention relates to a configuration for controlling the polarity of a bipolar field effect transistor having a channel region made of a graphite thin film such as graphene. It is.

  Silicon semiconductors can be integrated into a single chip by improving the degree of integration by miniaturization. However, in recent years, due to limitations in processing technology and heat generation, an upper limit has been seen in the integration scale.

  Conventional silicon integrated circuit devices have realized a wide variety of functions by combining many parts having a single function called CMOS inverters. On the other hand, there is an approach called “functionalized device” in which the same function is realized with a small number of parts by giving functions to individual parts.

  An integrated circuit device based on such an approach is advantageous in that it operates at high speed and low power consumption due to the small number of components, and more functions can be integrated when the same number of components is assumed.

  As one of such functionalization, various types of transistors using materials other than silicon have been studied so far. Among them, it is known that field effect transistors (FETs) made of various organic semiconductor materials typified by pentacene and carbon-based materials such as carbon nanotubes and graphene have bipolar properties.

  For example, in an FET using an organic semiconductor material, a method of controlling the threshold voltage of the organic semiconductor FET by arranging a physical voltage control layer in contact with the channel has been proposed (for example, Patent Document 1). reference).

  On the other hand, the inventor of the present invention has confirmed the bipolar characteristics by making a prototype of an FET having graphene as a channel region. FIG. 16 is a drain current-gate voltage characteristic (transfer characteristic) diagram of a graphene channel FET manufactured by the present inventors. The direction in which the drain current changes is reversed at a certain gate voltage value. Such a characteristic is called a “bipolar” characteristic.

In the case of FIG. 16, when the gate voltage is −5V or more, it functions as an n-channel FET, and when it is −5V or less, it functions as a p-channel FET. Note that as a method for producing graphene, a method of growing directly on a substrate using a chemical vapor deposition method or the like (see, for example, Patent Document 2 or Patent Document 3), a method of attaching a graphene film peeled off from a graphite crystal, A method of transferring a graphene sheet grown on the tip of a carbon nanotube to an insulating substrate is known.
JP 2005-268721 A JP 07-002508 A Japanese Patent Laid-Open No. 08-260150

  However, this “bipolarity” has not been actively used so far, and FETs are used only in one of the n-channel and p-channel regions, and are called “functionalized devices”. The current situation is that the approach is not effectively utilized.

  In the case of the above-mentioned Patent Document 1, since the polarity of the FET is determined at the time of manufacture and is not changed thereafter, the FET operates only in either the n-channel type or the p-channel type when used. However, there is a problem that the bipolar characteristics are not utilized.

  Therefore, an object of the present invention is to give the FET various functions by controlling the polarity at the time of use, not at the time of production.

  From one aspect of the present invention, a channel region provided on a substrate, a gate electrode provided on the channel region to control carrier concentration of the channel region, and a polarity of the transistor as viewed from the gate electrode are changed. An bipolar characteristic field effect transistor having a voltage applying means is provided.

  According to another aspect of the present invention, a plurality of the above-mentioned bipolar characteristic field effect transistors are arranged on the same substrate, and at least two of the plurality of bipolar characteristic field effect transistors are connected to each other. In addition to providing a circuit function, the polarity of one bipolar characteristic field effect transistor of the at least two bipolar characteristic field effect transistors is different from the polarity of the other bipolar characteristic field effect transistors. Thus, a semiconductor integrated circuit device for controlling the voltage applying means is provided.

  According to the disclosed bipolar field effect transistor and semiconductor integrated circuit device, the single transistor can have a function by switching the polarity by the control input during use. As a result, the integrated circuit device greatly contributes to high functionality, low power consumption, high speed, and miniaturization and cost reduction by reducing the chip area.

Here, with reference to FIG. 1 thru | or FIG. 4, the bipolar characteristic field effect transistor of embodiment of this invention is demonstrated. FIG. 1 is a schematic cross-sectional view of a bipolar field effect transistor according to an embodiment of the present invention. An insulating film 12 such as a SiO 2 film serving as a second gate insulating film is formed on a substrate 11 serving also as a back gate electrode. Then, a graphene film 13 is formed on the insulating film 12.

  As a method for forming the graphene film, various known methods are used. For example, a method of growing directly on the substrate 11 using a chemical vapor deposition method, a method of attaching a graphene film peeled off from a graphite crystal, or a method of transferring a graphene sheet grown on the tip of a carbon nanotube to an insulating substrate Is used.

Next, a source electrode 14 and a drain electrode 15 having a Ti / Au structure or the like are provided at both ends of the graphene film 13. Next, a first gate insulating film 16 made of an HfO 2 film or the like is formed on the entire surface, and a top gate electrode 17 made of a Ti / Au structure or the like is provided on the first gate insulating film 16 to complete the basic structure of the bipolar characteristic field effect transistor. To do.

  A contact electrode 18 such as a Ti / Au structure is provided on the back surface of the substrate 11. This bipolar field effect transistor according to the embodiment of the present invention is characterized by having two gate electrodes.

  FIG. 2 is a transfer characteristic diagram of the bipolar field effect transistor, and shows the characteristic when voltage is applied simultaneously to the top gate and the back gate. At this time, an electric charge corresponding to the sum of the electric field from the top gate and the electric field from the back gate is induced in the channel.

That is, if the back gate voltage is Vc, the back gate capacitance is C b , the top gate voltage is V g , and the top gate capacitance is C t , the total charge Q is:
Q = C b · V c + C t · V g
It becomes. For example, when a positive electric field is applied to the back gate and a negative electric field is applied to the top gate, the whole is canceled and no charge is induced. If this phenomenon is used, the transfer characteristic of one gate can be controlled by the other gate.

FIG. 3 is an explanatory diagram of the dependency of the top gate transfer characteristic on the back gate voltage V c , and here schematically shows how the transfer characteristic of the top gate is shifted by the back gate voltage V c . If you look closely at the figure, you can see that there are two areas where the polarity of the transfer characteristic of the top gate is inverted by the back gate voltage, the positive side and the negative side (inside the dotted line in the figure).

FIG. 4 is a symbol diagram of the bipolar characteristic field effect transistor according to the embodiment of the present invention.
Here, the input signal V in is connected to the top gate, a control signal V c is connected to the back gate. Of course, conversely, operation is possible even if V in is input to the back gate and the control signal V c is input to the top gate.

  In the embodiment of the present invention, the substrate 11 may be a semiconductor substrate such as a p-type Si substrate or an n-type Si substrate, or a metal substrate such as a SUS substrate. Furthermore, an insulating substrate such as a glass substrate or a sapphire substrate may be used.

However, when an insulating substrate is used, a back gate electrode may be provided on the insulating substrate. When a plurality of bipolar characteristic field effect transistors are integrated, the control signal V for each bipolar characteristic field effect transistor is used. c can be applied independently. Also, when an insulating substrate having an insulating film formed on the surface of the Si substrate is used, a separate back gate may be provided for each bipolar characteristic field effect transistor on the insulating film.

  In the above embodiment, since the work function of the gate electrode material in contact with the gate insulating film is not particularly considered, for example, Ti is used. However, the transfer characteristics can be further controlled by considering the work function of the gate electrode material on the side in contact with the gate insulating film.

  Furthermore, the material or film thickness constituting the first gate insulating film and the second gate insulating film is arbitrary, and may be arbitrarily selected according to required electrical characteristics such as operation speed and breakdown voltage.

In the above description, a back gate is provided in order to control the bipolar characteristics. However, the bipolar characteristic control means is not limited to the back gate. For example, for a single gate electrode of the bipolar characteristic field effect transistor without the back gate, the capacitive coupling or resistive coupling the input signal V in and the control voltage V c may be applied in parallel connection.

  Based on the above, the bipolar graphene channel FET according to the first embodiment of the present invention will now be described with reference to FIGS. FIG. 5 is a configuration explanatory view of a bipolar graphene channel FET of Example 1 of the present invention, FIG. 5 (a) is a schematic plan view, and FIG. 5 (b) is an AA in FIG. 5 (a). It is a schematic sectional drawing along the dashed-dotted line which connects ′.

First, an SiO 2 film 22 having a thickness of, for example, 300 nm is formed on a p-type silicon substrate 21 having a thickness of, for example, 0.6 mm (= 600 μm) by thermal oxidation. The film thickness of the SiO 2 film 22 is arbitrary, but a film thickness of 300 nm or 90 nm is preferable in order to make it easy to visually confirm the graphene film using interference in a process described later.

Next, a graphene film having a thickness of four layers or less, for example, two layers, is formed on the SiO 2 film 22. Here, as a film formation method, a graphene film peeled from a graphite crystal using an adhesive tape is attached.

  Next, the graphene film is patterned into a size of 10 μm × 10 μm by, for example, a photolithography method and an oxygen ion etching method to form an island-shaped graphene film 23, and elements are separated from each other.

  Next, after forming a resist pattern (not shown) having an opening of, for example, 50 μm × 10 μm to be a source / drain electrode forming region by photolithography, the Ti film 24 having a thickness of, for example, 10 nm and the thickness For example, an Au film 25 of 50 nm is sequentially deposited by a vacuum evaporation method.

  Next, the Ti / Au film deposited on the resist pattern together with the resist pattern is removed by lift-off, thereby forming the source electrode 26 and the drain electrode 27 having a Ti / Au film structure. In addition, the space | interval of the source electrode 26 and the drain electrode 27 shall be 5 micrometers, for example.

Next, an HfO 2 film 28 having a thickness of, for example, 50 nm is formed by an atomic layer deposition (ALD) to form a gate insulating film. The film thickness of the HfO 2 film 28 in this case is arbitrary, but if it is thick, a high driving voltage is required, and if it is thin, the dielectric breakdown voltage is reduced due to the occurrence of pinholes and the like, so a highly accurate film forming process Is required.

  Next, using a lift-off process similar to the process for forming the source / drain electrodes, for example, a thickness of, for example, a 10 nm Ti film 29 and a thickness of, for example, a 50 nm thick Au film 30 are stacked, and the width is For example, a 1 μm top gate electrode 31 is formed.

Thereafter, after appropriately performing a wiring process, a Ti film 32 having a thickness of, for example, 10 nm and an Au film 33 having a thickness of, for example, 50 nm are sequentially deposited on the back surface of the p-type silicon substrate 21 by vacuum evaporation. Thus, a back gate electrode 34 having a Ti / Au structure is formed. Note that the effective back gate is the p-type silicon substrate 21, and the gate insulating film for the back gate is the SiO 2 film 22.

FIG. 6 is an explanatory diagram of the polarity control characteristics of the produced bipolar characteristic graphene channel FET.
As shown in FIG. 6, when the control voltage V c to be applied to the back gate electrode 34 to -20V is, FET acts as an n-channel type. On the other hand, when the control voltage V c to -40V is, FET was confirmed to act as a p-channel type.

Thus, the polarity of the FET can be switched by the control human power Vc after the device is manufactured. As is apparent from FIG. 6, with in order to control the bipolar characteristic requires a large voltage to the control voltage V c, the modulation of the drain current is small.

The former is due to the fact that the thickness of the SiO 2 film 22 serving as the gate insulating film with respect to the back gate is as thick as 300 nm. Therefore, if the SiO 2 film is thinned, the control voltage V c can be further reduced. The latter is because the carrier mobility of the graphene channel is as low as about 500 cm 2 / V · s, and can be improved by future progress in process technology.

As described above, in the bipolar characteristics graphene channel FET of the first embodiment of the present invention, by controlling the control voltage V c to be applied to the back gate electrode, the conductivity type of FET in the p-channel type or n-channel type It can be controlled arbitrarily.

Next, with reference to FIG. 7, the bipolar graphene channel FET according to the second embodiment of the present invention will be described. Since the basic manufacturing process and element size are the same as those in the first embodiment, only the structure will be described. . FIG. 7 is a schematic cross-sectional view of the bipolar graphene channel FET of Example 2 of the present invention. After the SiO 2 film 22 is formed on the p-type silicon substrate 21 by thermal oxidation, the thickness is, for example, 50 nm. A back gate electrode 35 made of a Ti film is formed by a lift-off method.

Next, for example, after depositing a back gate insulating film 36 made of an SiO 2 film, an island-shaped graphene film 23, a source electrode 26, a drain electrode 27, and a gate made of an HfO 2 film are performed in the same step as in the first embodiment. An insulating film 28 and a top gate electrode 31 are sequentially formed. Thereafter, the basic configuration of the bipolar graphene channel FET according to the second embodiment of the present invention is completed by appropriately performing a wiring process.

  In the second embodiment of the present invention, since the back gate is formed as a buried gate separated for each FET, isolation between elements is possible. Accordingly, since each FET can be operated as an FET of any conductive channel type, an arbitrary basic circuit can be configured, and an integrated circuit can be manufactured by appropriately combining these basic circuits.

Next, with reference to FIG. 8, the bipolar graphene channel FET according to the third embodiment of the present invention will be described. Since the basic manufacturing process and element size are the same as those in the first embodiment, only the structure will be described. . FIG. 8 is a schematic cross-sectional view of a bipolar graphene channel FET of Example 3 of the present invention. After an SiO 2 film 22 is formed on a p-type silicon substrate 21 by thermal oxidation, an island-shaped graphene film 23 and a source An electrode 26, a drain electrode 27, and a gate insulating film 28 made of an HfO 2 film, for example, a gate electrode 37 having a Ti / Au structure are sequentially formed.

Thereafter, the basic configuration of the bipolar graphene channel FET according to the third embodiment of the present invention is completed by appropriately performing a wiring process. At this time, the gate electrode 37, a control voltage V c and the input signal V in is formed a predetermined wiring to be connected in parallel by capacitive coupling.

In Example 3 of the present invention, without using a back gate, for a single gate electrode, since the input signal V in and the control voltage V c is only connected in parallel by capacitive coupling, production The process is simplified and the characteristics can be arbitrarily controlled for each FET.

Next, a bipolar characteristic graphene channel FET according to Example 4 of the present invention will be described with reference to FIG. 9. Since the basic manufacturing process and element size are the same as those in Example 1, only the structure will be described. . FIG. 9 is a schematic cross-sectional view of a bipolar graphene channel FET according to Example 4 of the present invention. After an SiO 2 film 22 is formed on a p-type silicon substrate 21 by thermal oxidation, an island-shaped graphene film 23 and a source An electrode 26, a drain electrode 27, and a gate insulating film 28 made of an HfO 2 film, for example, a gate electrode 37 having a Ti / Au structure are sequentially formed.

Thereafter, the basic configuration of the bipolar graphene channel FET according to the third embodiment of the present invention is completed by appropriately performing a wiring process. At this time, the gate electrode 37, a control voltage V c and the input signal V in is formed a predetermined wiring to be connected in parallel by resistive coupling.

In Example 4 of the present invention, without using a back gate, for a single gate electrode, since the input signal V in and the control voltage V c is only connected in parallel by resistive coupling, production The process is simplified and the characteristics can be arbitrarily controlled for each FET.

Next, with reference to FIG. 10, a common source circuit using a bipolar graphene channel FET according to Example 5 of the present invention will be described. FIG. 10A is a circuit diagram of a source grounding circuit using a bipolar graphene channel FET according to Example 5 of the present invention. The source of the bipolar graphene channel FET is grounded, and the drain is connected via a resistor R. connecting to a high voltage source V H.

Figure 10 (b) is a transfer characteristic diagram of a common source circuit in the case where the control voltage V c applied to the back gate to the high level, the control voltage Vc when the high level operates as an n-channel type FET Therefore, the transfer characteristic as an inverter is shown. On the other hand, FIG. 10 (c), a transfer characteristic diagram of a common source circuit in the case where the control voltage V c applied to the back gate to the low level, p-type Yaneru type when the control voltage V c is at a low level Since it operates as an FET, it exhibits a transfer characteristic as an amplifier.

In this way, different transfer characteristics can be obtained by controlling the control voltage V c with a simple basic circuit of one bipolar characteristic graphene channel FET and one resistor. By using this basic circuit, Various functions can be realized.

Next, a phase modulator according to a sixth embodiment of the present invention will be described with reference to FIG. 11. This phase modulator is an application example of the common source circuit according to the sixth embodiment of the present invention. Figure 11, a circuit configuration diagram of a phase modulator according to a sixth embodiment of the present invention, it is an explanatory diagram of input and output characteristics, using digital data as the control voltage V c, to apply the analog sine wave as an input signal V in . As shown in the figure, sine waves whose phases are different by 180 ° are obtained according to the digital data.

  As described above, in the sixth embodiment of the present invention, by using the bipolar characteristic graphene channel FET of the present invention, the binary phase modulator has a simple basic circuit composed of one bipolar characteristic graphene channel FET and one resistor. Can be realized.

  Next, a basic gate circuit according to the seventh embodiment of the present invention will be described with reference to FIG. FIG. 12A is a circuit configuration diagram of a basic gate circuit according to a seventh embodiment of the present invention, in which two bipolar characteristic graphene channel FETs are stacked in two stages, one connected to a positive power supply and the other connected to a ground potential. In addition, a so-called CMOS inverter having a common input terminal is employed. FIG. 12B is a symbol diagram of the basic gate circuit.

Here, the control voltage V c1 for one transistor FET 1 is set to a high level to operate as an n-channel FET, and the control voltage V c2 to the other transistor FET 2 is set to a low level to operate as a p-channel FET. By such control voltage setting, the same inverter (inversion) operation as in a normal CMOS is performed.

Conversely, when V c1 is set to a low level and V c2 is set to a high level, FET 1 becomes a p-channel type FET and FET 2 becomes an n-channel type FET, and transmits a signal as it is without being inverted. The basic gate circuit having such characteristics can be applied to various digital circuits.

  Next, a two-input basic gate circuit according to the eighth embodiment of the present invention will be described with reference to FIGS. FIG. 13A is a circuit configuration diagram of the two-input basic gate circuit according to the eighth embodiment of the present invention, and FIG. 13B is a symbol diagram of the two-input basic gate circuit.

FIG. 14 is a truth table of the two-input basic gate circuit according to the eighth embodiment of the present invention. FIG. 14A is a truth table when V c1 is set to the high level and V c2 is set to the low level. FIG. 14B is a truth table when V c1 is set to low level and V c2 is set to high level.

As is apparent from FIG. 14A, when V c1 is set to a high level and V c2 is set to a low level, a NOR operation is performed as in a normal CMOS circuit. Conversely, when V c1 is set to a low level and V c2 is set to a high level, the polarities are reversed, and an AND operation is performed as is apparent from FIG.

  As described above, logical operations such as switching between summation and product of data depending on a certain calculation result have been realized only by programming. However, by using the bipolar characteristic graphene channel FET of the present invention, it is possible to realize in hardware with a single gate circuit.

  Next, with reference to FIG. 15, a logic circuit that performs eight logic operations according to the ninth embodiment of the present invention will be described. FIG. 15A is a circuit configuration diagram of the logic circuit according to the ninth embodiment of the present invention, and FIG. 15B is a truth table of the logic circuit. As shown in FIG. 15A, the logic circuit of the ninth embodiment of the present invention is configured by combining three basic gate circuits of the seventh embodiment and one two-input basic gate circuit of the eighth embodiment.

In FIG. 15A, the output A ′ from one basic gate circuit in the preceding stage is A or A negation (“A bar” in the truth table) depending on the values of the control inputs D 1 and D 2 applied to the back gate. Display). The same applies to the output B ′ from the other basic gate circuit in the preceding stage.

The output C ′ from the two-input basic gate circuit provided in the middle stage is either NOR or AND of A ′ and B ′ depending on the values of the control inputs D 5 and D 6 applied to the back gate of the two-input basic gate circuit. Finally, the output C from the basic gate circuit provided in the subsequent stage is either C ′ or N ′ negative depending on the values of the control inputs D 7 and D 8 applied to the back gate of the basic gate circuit.

FIG. 15B is a truth table summarizing the above control input dependency of input and output. Eight control signals D 1 to D 8 applied to each back gate enable eight kinds of logic operations. I understand.

  In each of the above embodiments, the channel region is formed of a graphene film. However, the channel region is not limited to the graphene film, and carbon nanotubes may be used for the channel region.

It is a schematic sectional drawing of the bipolar characteristic field effect transistor of embodiment of this invention. It is a transfer characteristic figure of a bipolar characteristic field effect type transistor. It is an explanatory view of the back gate voltage V c dependent transfer characteristic of a top gate. It is a symbol figure of the bipolar characteristic field effect transistor of an embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration explanatory view of a bipolar graphene channel FET of Example 1 of the present invention. It is explanatory drawing of the polarity control characteristic of produced bipolar characteristic graphene channel FET. It is a schematic sectional drawing of the bipolar characteristic graphene channel FET of Example 2 of this invention. It is a schematic sectional drawing of the bipolar characteristic graphene channel FET of Example 3 of this invention. It is a schematic sectional drawing of the bipolar characteristic graphene channel FET of Example 4 of this invention. It is explanatory drawing of the source grounding circuit using bipolar characteristic graphene channel FET of Example 5 of this invention. It is explanatory drawing of the phase modulator of Example 6 of this invention. It is explanatory drawing of the basic gate circuit of Example 7 of this invention. It is explanatory drawing of the 2 input basic gate circuit of Example 8 of this invention. It is a truth table of the 2-input basic gate circuit of Example 8 of this invention. It is explanatory drawing of the logic circuit which performs eight kinds of logic operations of Example 9 of this invention. It is a transfer characteristic figure of graphene channel FET.

Explanation of symbols

11 substrate 12 insulating film 13 graphene film 14 source electrode 15 drain electrode 16 first gate insulating film 17 top gate electrode 18 contact electrode 21 p-type silicon substrate 22 SiO 2 film 23 island-like graphene film 24 Ti film 25 Au film 26 source electrode 27 Drain electrode 28 HfO 2 film 29 Ti film 30 Au film 31 Top gate electrode 32 Ti film 33 Au film 34 Back gate electrode 35 Back gate electrode 36 Back gate insulating film 37 Gate electrode

Claims (6)

  1. A channel region provided on the substrate;
    A gate electrode provided on the channel region to control a carrier concentration of the channel region;
    A bipolar field effect transistor having voltage application means for changing a polarity of the transistor as viewed from the gate electrode;
  2. 2. The bipolar field effect transistor according to claim 1, wherein the channel region is made of either a graphite thin film or a carbon nanotube.
  3. 3. The bipolar characteristic field effect transistor according to claim 1, wherein the voltage applying means for changing the polarity is a second gate electrode provided on a surface of the channel region opposite to the surface on which the gate electrode is provided.
  4. 4. The bipolar field effect transistor according to claim 1, wherein the substrate constitutes the second gate electrode. 5.
  5. 3. The bipolar characteristic field effect transistor according to claim 1, wherein the voltage applying means for changing the polarity is a voltage source coupled to the gate electrode by either capacitive coupling or resistive coupling.
  6. A plurality of bipolar characteristic field effect transistors according to claim 1 are arranged on the same substrate, and at least two of the plurality of bipolar characteristic field effect transistors are connected to each other. In addition to providing a circuit function, the polarity of one bipolar characteristic field effect transistor of the at least two bipolar characteristic field effect transistors is different from the polarity of the other bipolar characteristic field effect transistors. A semiconductor integrated circuit device for controlling the voltage applying means.
JP2008308349A 2008-12-03 2008-12-03 Bipolar field effect transistor and semiconductor integrated circuit apparatus Withdrawn JP2010135471A (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102361029A (en) * 2011-10-16 2012-02-22 西北大学 Common-gate common-source multi-drain carbon nanotube conducting channel field-effect transistor
CN102651397A (en) * 2011-02-24 2012-08-29 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN103578955A (en) * 2012-07-31 2014-02-12 国际商业机器公司 Semiconductor and forming method thereof
US8728880B2 (en) 2010-12-17 2014-05-20 Samsung Electronics Co., Ltd. Graphene electronic device and method of fabricating the same
JP2014207439A (en) * 2013-04-15 2014-10-30 ツィンファ ユニバーシティ Bipolar thin-film transistor
JP2014212308A (en) * 2013-04-03 2014-11-13 独立行政法人産業技術総合研究所 Connection structure, manufacturing method of the same, and semiconductor device
US8928080B2 (en) 2011-12-06 2015-01-06 Samsung Electronics Co., Ltd. Field-effect transistor having back gate and method of fabricating the same
JP2015119178A (en) * 2013-12-18 2015-06-25 アイメックImec Bilayer graphene tunneling field effect transistor
JP2018098500A (en) * 2016-12-07 2018-06-21 ツィンファ ユニバーシティ Digital circuit
CN108258054A (en) * 2016-12-28 2018-07-06 中芯国际集成电路制造(上海)有限公司 Graphene device and its manufacturing method
CN108649095A (en) * 2018-04-12 2018-10-12 深圳大学 Field-effect tube structure photoelectric device and preparation method thereof based on nano-crystal structure carbon film

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257528B2 (en) 2010-12-17 2016-02-09 Samsung Electronics Co., Ltd. Graphene electronic device and method of fabricating the same
US8728880B2 (en) 2010-12-17 2014-05-20 Samsung Electronics Co., Ltd. Graphene electronic device and method of fabricating the same
CN102651397A (en) * 2011-02-24 2012-08-29 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN102361029A (en) * 2011-10-16 2012-02-22 西北大学 Common-gate common-source multi-drain carbon nanotube conducting channel field-effect transistor
US8928080B2 (en) 2011-12-06 2015-01-06 Samsung Electronics Co., Ltd. Field-effect transistor having back gate and method of fabricating the same
CN103578955A (en) * 2012-07-31 2014-02-12 国际商业机器公司 Semiconductor and forming method thereof
JP2014212308A (en) * 2013-04-03 2014-11-13 独立行政法人産業技術総合研究所 Connection structure, manufacturing method of the same, and semiconductor device
JP2014207439A (en) * 2013-04-15 2014-10-30 ツィンファ ユニバーシティ Bipolar thin-film transistor
JP2015119178A (en) * 2013-12-18 2015-06-25 アイメックImec Bilayer graphene tunneling field effect transistor
JP2018098500A (en) * 2016-12-07 2018-06-21 ツィンファ ユニバーシティ Digital circuit
CN108258054A (en) * 2016-12-28 2018-07-06 中芯国际集成电路制造(上海)有限公司 Graphene device and its manufacturing method
CN108649095A (en) * 2018-04-12 2018-10-12 深圳大学 Field-effect tube structure photoelectric device and preparation method thereof based on nano-crystal structure carbon film

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