CN105118831B - A kind of dibit is without knot flash memories and its programming, erasing and read method - Google Patents
A kind of dibit is without knot flash memories and its programming, erasing and read method Download PDFInfo
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Abstract
The invention discloses a kind of dibit without knot flash memories, it is a SONOS flash memory using nodeless mesh body pipe structure, source, drain terminal and channel region with uniform heavily doped N-type impurity are without the use of PN junction in its substrate, its silicon nitride layer includes two storage positions, for storing charge, heavily doped region have make SONOS flash memories when off can the completely depleted regional Electronic thickness；It is programmed is carried out using band-to-band-tunneling hot hole injection mode, erasing is carried out using raceway groove FN tunnellings erasing mechanism, reading is carried out using reverse read mode, it is complicated can to solve circuit structure existing for conventional floating gate multidigit memory technology, read, write-in, erasing speed it is slower, it is higher to reliability requirement the defects of.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of dibit without knot flash memories and its programming,
Erasing and read method.
Background technology
As distance has arrived the Asia 50nm stages between the PN junction of modern cmos device, high doping concentration gradient very must
Will, this considerably increases the difficulty of technique manufacture.In the case where device channel length is less than 50nm, ultra-shallow junctions technology is for suppression
Short channel effect processed is highly effective, but controls the depth of PN junction and its section highly difficult.Also, due to thermal annealing it is high into
This so that it is a bottleneck to form ultra-shallow junctions for the technique of following 3D multiple-level stack devices.
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride-oxide-silicon)
It is that a kind of and flash memory contacts more close nonvolatile memory.The main distinction of it and mainstream flash memory is that it is used
Silicon nitride (Si3N4) rather than polysilicon serve as storage material.Its branch is SHINOS (silicon-high dielectric-nitridation
Object-oxide-silicon).SONOS allows the program voltage lower than polysilicon flash memory and higher programming-erasing cycle-index, is
One more active research, exploitation hot spot.
SONOS has better data retention characteristics, silicon nitride layer is localization relative to conventional floating gate transistor flash
Charge storage elements, from conventional floating gate transistor using conductor polysilicon storage electronics it is different, have a small amount of defect in oxide layer
When, the unexpected loss of total data will not be caused.
Traditional multidigit memory technology brief introduction：Memory Storage Unit relies on the electron number different instructions 0 stored in floating boom
With 1, there is higher reliability, at the erasing period of up to 1e5, the threshold voltage difference of Memory Storage Unit remains to reach
4V.This feature makes it possible using multiple level cell (multidigit storage) technology.So-called multiple level
Cell technologies are exactly according to the difference that electron amount is stored in Memory Storage Unit floating boom, are divided into four grades,
For representing 00,01,10,11 4 storage state respectively, cell (unit) storage two bits are realized.Original
Single level cell technologies, electron number is about 250 in floating boom, and threshold voltage remains at low levels, and represents storage shape
State 1；And electron number be 4000 to 6000 when, threshold voltage is higher, represents storage state 0.And multiple level cell
Technology in addition to two kinds of original situations represent storage state 00 and 11 respectively, newly adds two medians, i.e. electron number is
1500 to 2500 represent storage state 00, and electron number represents storage state 10 for 3000 to 3500.It thereby realizes at one
Two bits are stored in cell, has in integrated level more originally and increases exponentially.
But traditional floating boom multidigit memory technology has its inherent shortcoming：
First, it is desirable that stable charge storage.Charge number differs between multiple level cell four states of technology
It is smaller, so requiring higher to leakage rate, leakage rate is about required to be less than 1 electronics daily；
Second, it is desirable that accurate data reading circuit.Multiple level cell technologies require higher electric charge induction with
00,01,10,11 4 state is distinguished, generally to be realized by very complicated circuit, so reading speed is also relatively slow；
Third, it is desirable that accurate electron injection mechanism.The electronics of multiple level cell technologies requirement injection floating boom
Number is more accurate, and to carry out more complicated verification, it is ensured that the correctness of data is stored, so circuit structure is more multiple
Miscellaneous, the speed of write-in and erasing is also relatively slow.
The article that nodeless mesh body pipe was published in 2010 on Nature first by Jean-Pierre Colinge et al.
" Nanowire transistors without junctions " is proposed.Its operation principle is to use Uniform Doped substrate
Instead of source-drain structure, so as to eliminate the structure of the original PN junction of transistor, reduce process complexity and improve crystal
The performance of pipe.In this transistor without PN junction, the electric conductivity using the on-off action controlling transistor of grid reaches switch
Effect.Gate voltage is less than threshold voltage during shutdown, and intermediate channel part is depleted and turns off.Gate voltage is more than during break-over of device
Equal to threshold voltage, intermediate channel part forms and can be conductive.Traditional nodeless mesh body tube lining bottom is Uniform Doped without source
The structure of the PN junction of leakage, therefore it can save the technological process to form source and drain and ion diffusion thermal process, and be not required to increase new
Light shield, thus processing step and cost is greatly saved.
Therefore, it is more to solve conventional floating gate how using a kind of new SONOS flash memory structures of nodeless mesh body pipe structure design
Circuit structure existing for the memory technology of position is complicated, read, write-in, erasing speed it is slower, it is higher to reliability requirement the defects of, into
For one subject treated with solution of industry.
Invention content
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of dibit is provided without knot flash memories
And its programming, erasing and read method, circuit structure complexity existing for conventional floating gate multidigit memory technology can be solved, reads, write
Enter, erasing speed it is slower, it is higher to reliability requirement the defects of.
To achieve the above object, technical scheme is as follows：
A kind of dibit without knot flash memories, including：
P type substrate has source, drain terminal and the channel region of uniform heavily doped N-type impurity in the substrate；And
Establish the SONOS flash memory structures on the substrate between the source, drain terminal, the SONOS flash memory structures
From bottom to top successively include substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, p-type heavy doping polysilicon control grid, institute
State silicon nitride layer include for store charge first, second storage position, the heavily doped region have make the SONOS flash memories
When off can the completely depleted regional Electronic thickness；
Wherein, when the described first storage position programming, by applying negative grid voltage to the control gate, to the leakage
End applies positive drain terminal voltage, and the source is grounded, to generate highfield between the control gate and drain terminal, causes to be formed
Hot hole band-to-band-tunneling effect, hole injects the silicon nitride layer under the action of the grid voltage by the drain terminal,
And the trap of the silicon nitride layer described in drain terminal side at the first storage position captures and is stored in and wherein completes programming；When described
During the second storage position programming, by applying negative grid voltage to the control gate, apply positive source voltage terminal to the source,
The drain terminal is grounded, to generate highfield between the control gate and source, causes the band-to-band-tunneling for the hot hole to be formed
The silicon nitride layer is injected, and second described in source side in effect, hole under the action of the grid voltage by the source
The trap of the silicon nitride layer at storage position captures and is stored in and wherein completes programming.
Preferably, the source, drain terminal and channel region are uniformly heavily doped with N-type impurity arsenic.
Preferably, the doping concentration of the arsenic is 1E-19~1.5E-19/cm3。
Preferably, the thickness of the uniform heavily doped region is no more than 20nm.
Preferably, the grid length of the control gate is no more than 40nm.
Programming, erasing and read method of a kind of dibit without knot flash memories, the dibit is without knot flash memories packet
It includes：P type substrate has source, drain terminal and the channel region of uniform heavily doped N-type impurity in the substrate；And it establishes in institute
The SONOS flash memory structures on the substrate between source, drain terminal are stated, the SONOS flash memory structures include successively from bottom to top
Substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, p-type heavy doping polysilicon control grid, the silicon nitride layer include use
In first, second storage position of storage charge, the heavily doped region, which has, makes the SONOS flash memories that can consume completely when off
The thickness of the regional Electronic to the greatest extent；
The programmed method includes：It is carried out using band-to-band-tunneling hot hole injection mode, in the described first storage position programming,
Apply negative grid voltage to the control gate, apply positive drain terminal voltage to the drain terminal, the source is grounded, in institute
It states and highfield is generated between control gate and drain terminal, cause the band-to-band-tunneling effect for the hot hole to be formed, hole is in grid electricity
The silicon nitride layer, and the silicon nitride layer described in drain terminal side at the first storage position are injected by the drain terminal under the action of pressure
Trap capture and be stored in wherein complete programming；In the described second storage position programming, apply negative grid to the control gate
Pole tension applies the source positive source voltage terminal, the drain terminal is grounded, to be generated between the control gate and source
Highfield, causes the band-to-band-tunneling effect for the hot hole to be formed, and hole is noted under the action of the grid voltage by the source
Enter the silicon nitride layer, and the trap of the silicon nitride layer described in source side at the second storage position is captured and is stored in wherein
Complete programming；
The method for deleting includes：It is carried out using raceway groove FN tunnellings erasing mechanism, applies positive grid electricity to the control gate
Pressure, applies the source and drain identical negative voltage respectively, strong to be generated between the control gate and source and drain and substrate
Electric field forms a spatially uniform FN tunneling mechanism, the work of highfield between the control gate and source and drain and substrate
Under, the electronics in raceway groove has carried out the gate oxide FN tunnellings and has injected described the first and second of the silicon nitride layer depositing
Erasing is completed in storage space；
The read method includes：Read operation is carried out using reverse read mode, when the state for needing the first storage of reading position
When, apply positive source voltage terminal to the source, the drain terminal is grounded, and the control gate is made to suspend；When needing reading
During the state of two storage positions, apply positive drain terminal voltage to the drain terminal, the source is grounded, and hang the control gate
It is floating.
Preferably, in the described first storage position programming, apply the grid voltage of -6~-4v to the control gate, to institute
The drain terminal voltage that drain terminal applies 4~6v is stated, the source is grounded；In the described second storage position programming, to the control gate
Apply the grid voltage of -6~-4v, apply the source voltage terminal of 4~6v to the source, the drain terminal is grounded.
Preferably, during erasing, apply the grid voltage of 13~16v to the control gate, the source and drain is applied respectively
Add the identical voltage of -4~-2v.
Preferably, when needing to read the state of the first storage position, apply the source voltage terminal of 1.6v to the source, to institute
Drain terminal ground connection is stated, and the control gate is made to suspend；When needing to read the state of the second storage position, 1.6v is applied to the drain terminal
Drain terminal voltage, the source is grounded, and the control gate is made to suspend.
Preferably, the source, drain terminal and channel region are uniformly heavily doped with N-type impurity arsenic, the doping concentration of the arsenic
For 1E-19~1.5E-19/cm3, Implantation Energy is 2.5~4kev, and implantation dosage is 1E14~2E19/cm2, formation it is described
The thickness of even heavily doped region is no more than 20nm, and the grid length of the control gate is no more than 40nm.
The beneficial effects of the present invention are：
First, in the structure of SONOS flash memories, using the transistor arrangement of no PN junction, without using small size MOSFET and
Small size flash memory can greatly reduce sub- below 50nm sizes SONOS to reduce ultra-shallow junctions technology used in short channel effect
The processing step and cost of flash memories；
Second, because without using PN junction, reduce the short channel effect of small size SONOS flash memories, it is thus possible to further contracting
Small critical size；
Third reduces the coarse caused mobil-ity degradation problem of silicon face of traditional SONOS flash memories；
4th, reduce needs of traditional SONOS flash memories to diminution electrical equivalent oxidated layer thickness；
5th, using low-power consumption program/erase method, program/erase power consumption can be reduced；
6th, using the storage of silicon nitride layer dibit (i.e. first and second storage position), considerably increase storage density and storage is held
Amount since the local electronic of silicon nitride layer stores, carries out the volume of the first storage position and the second storage position in drain terminal and source respectively
Journey, first and second storage position is spatially apart from each other, does not influence mutually, therefore can accurately read the first storage position or second
Store position information, so as to solve conventional floating gate multidigit memory technology circuit structure complexity, read, write-in, erasing speed compared with
Slowly, the defects of higher to reliability requirement.
Description of the drawings
Fig. 1 is a kind of structure diagram of the dibit of a preferred embodiment of the present invention without knot flash memories；
Fig. 2 is the principle schematic that a preferred embodiment of the present invention is programmed the first storage position；
Fig. 3 is the principle schematic that a preferred embodiment of the present invention is programmed the second storage position；
Fig. 4 is the principle schematic that a preferred embodiment of the present invention is wiped using raceway groove FN tunnellings erasing mechanism.
Specific embodiment
Below in conjunction with the accompanying drawings, the specific embodiment of the present invention is described in further detail.
It should be noted that in following specific embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special not draw to the structure in attached drawing according to general proportion, and carried out part
Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In specific embodiment of the invention below, referring to Fig. 1, Fig. 1 is one kind of a preferred embodiment of the present invention
Structure diagram of the dibit without knot flash memories.As shown in Figure 1, the present invention a kind of dibit without knot flash memories, including：
P type substrate 1, has source 2, drain terminal 5 and 6 region of raceway groove of uniform heavily doped N-type impurity in the substrate 1 and establishes and exist
The SONOS flash memory structures on the substrate 1 between the source 2, drain terminal 5.The SONOS flash memory structures are from bottom to top successively
Including substrate silicon layer, gate oxide, silicon nitride layer 4, oxide layer and the polysilicon control grid 3 of p-type heavy doping.Silicon nitride layer 4 rises
The effect of charge is stored, first, second storage position 4-1,4-2 including being used to storing charge, the first storage position 4-1 are close
5 side of drain terminal, the second storage position 4-2 is close to 2 side of source.First and second storage position 4-1,4-2 is spatially apart from each other, mutually
It does not influence mutually.
Please continue to refer to Fig. 1.The present invention uses for reference Jean-Pierre Colinge et al. and was published on Nature in 2010
Article " Nanowire transistors without junctions " propose the concept without junction nanowire transistor, move
It plants on SONOS flash memory device structures, it is proposed that a kind of new SONOS flash memory structures using nodeless mesh body pipe structure.The present invention
Dibit without knot flash memories structure it is critical that source 2, drain terminal 5 and 6 region of raceway groove formed the heavily doped region
Domain must it is sufficiently thin so that the SONOS flash memories when off can the completely depleted N-type heavily doped region electronics.As one
Preferred embodiment, the thickness H of the uniform heavily doped region should be no more than 20nm.The grid length of the control gate 3 can not surpass
Cross 40nm.
It is using the reason of N-type heavily doped region, SONOS flash memories must be enabled there are enough electric currents to pass through in ON state, and
And source and drain has sufficiently small contact resistance.It is worth noting that, in order to reduce process complexity, there is no use nanometer by the present invention
Cable architecture.Ideal threshold voltage in order to obtain, N-type channel SONOS flash memories must carry out the p-type heavy doping of grid, P-type channel
SONOS flash memories must carry out the N-type heavy doping of grid.In this way, using the work function difference between polysilicon gate and silicon, grid voltage can be made
SONOS flash memories when being zero, which can be depleted, to be turned off.
The above-mentioned this novel SONOS flash memory structures of the present invention are not using PN junction, all sources, drain terminal and raceway groove
All it is the region of Uniform Doped N-type impurity, is formed in P type substrate.As a preferred embodiment, raceway groove and source and drain N-type
The implanted dopant of heavily doped region can be arsenic (Arsenic), and doping concentration can be 1E-19~1.5E-19/cm3, such as can be
1E-19/cm3Uniform Doped；Implantation Energy can be 2.5~4kev, such as can be 3KeV, implantation dosage can be 1E14~
2E19/cm2, such as can be 1E 14/cm2.By the injection, the thickness H that can make N-type heavily doped region is only to be no more than
20nm, it is ensured that can be depleted when SONOS flash memories turn off.
Due to small-sized, the usually less than 50nm of the SONOS flash memories proposed by the present invention using nodeless mesh body pipe structure,
Therefore the programming mechanism of traditional CHE (Channel Hot Electron, channel hot electron) injections due to power consumption very it is big not
It is suitble to.Article " the PHINES that we were delivered using C.C.Yeh et al. in 2002:A novel low power
The low-power consumption program/erase side that program/erase, small pitch, 2-bit per cell Flash memory " are mentioned
Method, that is, improve threshold voltage using raceway groove FN erasings (Channel Fowler-Nordheim Erase).Programming then according to
By BTBHHI (Band to Band Hot Hole Injection, the injection of band-to-band-tunneling hot hole).
Please refer to Fig. 1.Specifically, the programmed method that the present invention takes includes：It is carried out using BTBHHI modes,
During the first storage position 4-1 programmings, apply negative grid voltage to the control gate 3, positive drain terminal is applied to the drain terminal 5
Voltage is grounded the source 2, to generate highfield between the control gate 3 and drain terminal 5, causes the hot hole to be formed
The silicon nitride layer 4 is injected, and by drain terminal in band-to-band-tunneling effect, hole under the action of the grid voltage by the drain terminal 5
The trap of the silicon nitride layer 4 described in side at the first storage position 4-1 captures and is stored in and wherein completes programming；Described second
When storing position 4-2 programmings, apply negative grid voltage to the control gate 3, positive source voltage terminal is applied to the source 2, it is right
The drain terminal 5 is grounded, and to generate highfield between the control gate 3 and source 2, causes the band-to-band-tunneling for the hot hole to be formed
The silicon nitride layer 4 is injected, and described in source side in effect, hole under the action of the grid voltage by the source 2
The trap of the silicon nitride layer 4 at two storage position 4-2 captures and is stored in and wherein completes programming.
Referring to Fig. 2, Fig. 2 is the principle schematic that a preferred embodiment of the present invention is programmed the first storage position.Such as
It,, can be right when the described first storage position 4-1 programmings in above-mentioned programmed method as an optional embodiment shown in Fig. 2
The control gate applies the grid voltage of -6~-4v, applies the drain terminal voltage of 4~6v to the drain terminal, and the source is grounded.
In the present embodiment, using grid voltage Vg=-5v, drain terminal voltage Vd=5v, source ground voltage Vs=0v.At this point, in grid
Under forceful electric power field action between leakage, drain terminal energy band is bent strongly, and BTBT holes are tunneling to conduction band (arrow institute as shown from valence band
Refer to), then under the raceway groove electric field action of source Vs=0v, it is accelerated to form hot hole in raceway groove depletion region.In -5v grid voltages
Under effect, this hole possesses enough energy and crosses potential barrier between silicon and gate oxide, and be injected into the of silicon nitride layer
Programming is completed in one storage position 4-1.During to the first storage position 4-1 programmings, electric hole is caught by the trap of the silicon nitride layer of drain terminal side
It obtains and is stored in wherein.
Referring to Fig. 3, Fig. 3 is the principle schematic that a preferred embodiment of the present invention is programmed the second storage position.Such as
It,, can be right when the described second storage position 4-2 programmings in above-mentioned programmed method as an optional embodiment shown in Fig. 3
The control gate applies the grid voltage of -6~-4v, applies the source voltage terminal of 4~6v to the source, and the drain terminal is grounded.
In the present embodiment, using grid voltage Vg=-5v, source voltage terminal Vs=5v, drain terminal ground voltage Vd=0v.At this point, in grid
Under forceful electric power field action between source, source energy band is bent strongly, and BTBT holes are tunneling to conduction band (arrow institute as shown from valence band
Refer to), then under the raceway groove electric field action of drain terminal Vd=0v, it is accelerated to form hot hole in raceway groove depletion region.In -5v grid voltages
Under effect, this hole possesses enough energy and crosses potential barrier between silicon and gate oxide, and be injected into silicon nitride layer second
It stores and programming is completed in the 4-2 of position.During to the second storage position 4-2 programmings, electric hole is captured by the trap of the silicon nitride layer of source side
And it is stored in wherein.It can be seen that the forceful electric power between grid and leakage or between grid and source from the electron energy band figure that Fig. 2, Fig. 3 are shown
Under field action, hole from valence band be tunneling to conduction band when, more downward, the energy in hole is higher.
Please refer to Fig. 1.The method for deleting that the present invention takes includes：It is carried out using raceway groove FN tunnellings erasing mechanism, it is right
The control gate 3 applies positive grid voltage, applies identical negative voltage respectively to the source and drain 2,5, in the control
Highfield is generated between grid 3 and source and drain 2,5 and substrate 1, a spatially uniform FN tunneling mechanism is formed, in the control
Between grid and source and drain and substrate processed under the action of highfield, the electronics in raceway groove has carried out FN tunnellings to the gate oxide
And it injects in described first and second storage position 4-1,4-2 of the silicon nitride layer 4 and completes erasing.
Referring to Fig. 4, Fig. 4 is the principle that a preferred embodiment of the present invention is wiped using raceway groove FN tunnellings erasing mechanism
Schematic diagram.As shown in figure 4, as an optional embodiment, in above-mentioned method for deleting, during erasing, the control gate is applied
Add the grid voltage of 13~16v, apply the identical voltage of -4~-2v respectively to the source and drain.In the present embodiment, it uses
Control-grid voltage Vg=15v, drain terminal voltage Vd=-3v, source voltage terminal Vs=-3v.This is a spatially uniform FN tunnelling
Mechanism.Between grid and source and drain and substrate under the forceful electric power field action of 18v voltages (15v+3v), energy band becomes to be bent very much, in raceway groove
Electronics carried out FN tunnellings to gate oxide and fallen into complete erasing (as shown arrow signified) in silicon nitride layer 4.It is shown from Fig. 4
The electron energy band figure shown can be seen that more upward, then the energy of electronics is higher.
We are so defined threshold voltage vt h, as drain terminal voltage Vd=1.6v, for each memory cell (first
Or the second storage position), the voltage of control gate during Id=1E-7A/ μm of drain terminal electric current is as threshold voltage vt h.At the beginning, to device
Part carries out FN erasings, Vg=15v, Vd=Vs=-3v.In this way, the first storage position and the second storage position are all in high threshold voltage
State " 0 ", total state are " 00 ".If to the first storage position programming, threshold voltage is lower, for state " 1 ", total state
For " 10 ".If to the second storage position programming, threshold voltage is lower, and is state " 1 ", and total state is " 01 ".It is if successively right
First storage position and the second storage position programming, then their state is all " 1 ", and total state is " 11 ".
Please refer to Fig. 1.The read method that the present invention takes includes：Using reverse read (reverse read
Scheme) mode carries out read operation, specifically, when needing to read the state of the first storage position 4-1, the source 2 is applied
Positive source voltage terminal is grounded the drain terminal 5, and the control gate 3 is made to suspend；When the shape for needing the second storage of reading position 4-2
During state, apply positive drain terminal voltage to the drain terminal 5, the source 2 is grounded, and the control gate 3 is made to suspend.
As an optional embodiment, in above-mentioned read method, when the state for needing the first storage of reading position 4-1
When, apply source voltage terminal Vs=1.6V, drain terminal voltage Vd=0V ground connection, and control-grid voltage Vg=is made to suspend；When needing to read
During the state of the second storage position 4-2, apply drain terminal voltage Vd=1.6V, source voltage terminal Vs=0V ground connection, and make control-grid voltage
Vg=suspends.If drain terminal electric current Id, more than 1E-7/ μm, the state of the storage position is " 1 ", if drain terminal electric current Id is less than 1E-7/ μ
M, then the state of the storage position is " 0 ".By the read operation to two storage positions, the information of four kinds of different conditions can be sensed
" 00 ", " 01 ", " 10 ", " 11 ".
In the above-mentioned this novel SONOS flash memory structures for making the present invention, using n-type doping arsenic impurities
(Arsenic) it injects raceway groove and source and drain forms heavily doped region, doping concentration can be 1E-19~1.5E-19/cm3, Implantation Energy
Can be 2.5~4kev, implantation dosage can be 1E14~2E19/cm2.By the injection, all sources, drain terminal and raceway groove all into
Region for Uniform Doped N-type impurity.Also, by above-mentioned injection technology, the thickness of N-type heavily doped region can be made not surpass only
Cross 20nm, it is ensured that can be depleted when SONOS flash memories turn off.The grid length of the SONOS flash memories is only to be no more than 40nm.
Dibit SONOS flash memories proposed by the present invention using nodeless mesh body pipe structure, there is no increase standard CMOS process
In light shield number, reduce the complexity and cost of technique instead, therefore can be compatible with existing CMOS technology well, and can
In present Semiconductor Manufacturing Company's scale of mass production.
The above-mentioned SONOS flash memory structures using nodeless mesh body pipe structure disclosed by the invention, can greatly reduce sub- 50nm
The processing step and cost of following size SONOS flash memories reduce the short channel effect of small size SONOS flash memories, reduce tradition SONOS
The silicon of flash memory and the coarse caused mobil-ity degradation problem of oxide interface, reduce tradition SONOS flash memories to reducing electrical equivalent
The needs of oxidated layer thickness；Low-power consumption program/erase method of the present invention, can reduce program/erase power consumption, using nitrogen
The dibit storage of SiClx layer, can greatly increase storage density and memory capacity；Meanwhile the dibit storage of silicon nitride layer possesses relatively
The characteristics of more superior is stored in the dibit of floating boom, since the local electronic of silicon nitride layer stores, is carried out respectively in source and drain terminal
First storage position and the programming of the second storage position, the first storage position and the second storage position are spatially apart from each other, mutually not shadow
It rings, it is thus possible to the accurate information for reading the first storage position or the second storage position.So as to.The present invention solves conventional floating gate multidigit
Memory technology circuit structure is complicated, read, write-in, erasing speed it is slower, it is higher to reliability requirement the defects of.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present invention
Range, therefore the equivalent structure variation that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of dibit is without knot flash memories, which is characterized in that including：
P type substrate has source, drain terminal and the channel region of uniform heavily doped N-type impurity in the substrate；And
The SONOS flash memory structures on the substrate between the source, drain terminal are established, the SONOS flash memory structures are under
On and successively include substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, p-type heavy doping polysilicon control grid, the nitrogen
SiClx layer includes the first, second storage position for storing charge, and the heavily doped region, which has, is closing the SONOS flash memories
The thickness of the completely depleted regional Electronic of energy when disconnected；
Wherein, when the described first storage position programming, by applying negative grid voltage to the control gate, the drain terminal is applied
Add positive drain terminal voltage, the source is grounded, to generate highfield between the control gate and drain terminal, causes the heat to be formed
The silicon nitride layer is injected in the band-to-band-tunneling effect in hole, hole under the action of the grid voltage by the drain terminal, and by
The trap of the silicon nitride layer described in drain terminal side at the first storage position captures and is stored in and wherein completes programming；When described second
When storing position programming, by applying negative grid voltage to the control gate, apply positive source voltage terminal to the source, to institute
Drain terminal ground connection is stated, to generate highfield between the control gate and source, causes the band-to-band-tunneling effect for the hot hole to be formed,
The silicon nitride layer, and the second storage position described in source side are injected in hole under the action of the grid voltage by the source
The trap of the silicon nitride layer at place captures and is stored in and wherein completes programming.
2. dibit according to claim 1 is without knot flash memories, which is characterized in that the source, drain terminal and channel region
Domain is uniformly heavily doped with N-type impurity arsenic.
3. dibit according to claim 2 is without knot flash memories, which is characterized in that the doping concentration of the arsenic is 1E-
19~1.5E-19/cm3。
4. dibit according to claim 1 or 2 is without knot flash memories, which is characterized in that the uniform heavily doped region
Thickness be no more than 20nm.
5. dibit according to claim 1 is without knot flash memories, which is characterized in that the grid length of the control gate is no more than
40nm。
6. programming, erasing and read method of a kind of dibit without knot flash memories, which is characterized in that the dibit is without knot flash memory
Memory includes：P type substrate has source, drain terminal and the channel region of uniform heavily doped N-type impurity in the substrate；And
The SONOS flash memory structures on the substrate between the source, drain terminal are established, the SONOS flash memory structures are from bottom to top
Successively include substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, p-type heavy doping polysilicon control grid, the silicon nitride
Layer include for store charge first, second storage position, the heavily doped region have make the SONOS flash memories when off
The thickness of the completely depleted regional Electronic of energy；
The programmed method includes：It is carried out using band-to-band-tunneling hot hole injection mode, in the described first storage position programming, to institute
It states control gate and applies negative grid voltage, apply positive drain terminal voltage to the drain terminal, the source is grounded, in the control
Highfield is generated between grid and drain terminal processed, causes the band-to-band-tunneling effect for the hot hole to be formed, hole is in the grid voltage
The silicon nitride layer is injected by the drain terminal under effect, and the silicon nitride layer described in drain terminal side at the first storage position is sunken
Trap captures and is stored in and wherein completes programming；In the described second storage position programming, apply negative grid electricity to the control gate
Pressure applies the source positive source voltage terminal, the drain terminal is grounded, to generate forceful electric power between the control gate and source
, cause the band-to-band-tunneling effect for the hot hole to be formed, institute is injected in hole under the action of the grid voltage by the source
Silicon nitride layer is stated, and the trap of the silicon nitride layer described in source side at the second storage position captures and is stored in and wherein completes
Programming；
The method for deleting includes：It is carried out using raceway groove FN tunnellings erasing mechanism, applies positive grid voltage to the control gate, it is right
The source and drain applies identical negative voltage respectively, to generate highfield between the control gate and source and drain and substrate,
A spatially uniform FN tunneling mechanism is formed, between the control gate and source and drain and substrate under the action of highfield,
Electronics in raceway groove has carried out the gate oxide FN tunnellings and has injected in the first and second storage position of the silicon nitride layer
Complete erasing；
The read method includes：Read operation is carried out using reverse read mode, it is right when needing to read the state of the first storage position
The source applies positive source voltage terminal, and the drain terminal is grounded, and the control gate is made to suspend；It is stored when needing reading second
During the state of position, apply positive drain terminal voltage to the drain terminal, the source is grounded, and the control gate is made to suspend.
7. programming according to claim 6, erasing and read method, which is characterized in that in the described first storage position programming
When, to the grid voltage of -6~-4v of control gate application, apply the drain terminal voltage of 4~6v to the drain terminal, to the source
Ground connection；In the described second storage position programming, apply the grid voltage of -6~-4v to the control gate, 4 are applied to the source
The source voltage terminal of~6v is grounded the drain terminal.
8. programming according to claim 6, erasing and read method, which is characterized in that during erasing, applied to the control gate
Add the grid voltage of 13~16v, apply the identical voltage of -4~-2v respectively to the source and drain.
9. programming according to claim 6, erasing and read method, which is characterized in that store position when needing reading first
State when, apply the source voltage terminal of 1.6v to the source, the drain terminal be grounded, and the control gate is made to suspend；When need
When reading the state of the second storage position, apply the drain terminal voltage of 1.6v to the drain terminal, the source is grounded, and make described
Control gate suspends.
10. programming according to claim 6, erasing and read method, which is characterized in that the source, drain terminal and raceway groove
Region is uniformly heavily doped with N-type impurity arsenic, and the doping concentration of the arsenic is 1E-19~1.5E-19/cm3, Implantation Energy 2.5
~4kev, implantation dosage are 1E14~2E19/cm2, the thickness of the uniform heavily doped region of formation is no more than 20nm, described
The grid length of control gate is no more than 40nm.
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| CN101728394A (en) * | 2009-12-01 | 2010-06-09 | 清华大学 | Groove type non-volatilisation memory for multi-digit storage |
| CN102709291A (en) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | SONOS storage unit, operation method of SONOS and SONOS storage |
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