CN117794245A - Floating gate memory, preparation method thereof and logic device - Google Patents
Floating gate memory, preparation method thereof and logic device Download PDFInfo
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- CN117794245A CN117794245A CN202311204750.6A CN202311204750A CN117794245A CN 117794245 A CN117794245 A CN 117794245A CN 202311204750 A CN202311204750 A CN 202311204750A CN 117794245 A CN117794245 A CN 117794245A
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Abstract
The invention provides a floating gate memory, which comprises a substrate layer, a channel layer, a blocking insulating layer, a floating gate layer, a tunneling insulating layer, a control gate and source electrodes and drain electrodes, wherein the channel layer, the blocking insulating layer, the floating gate layer, the tunneling insulating layer and the control gate are sequentially arranged on the substrate layer, the source electrodes and the drain electrodes are arranged on two sides of the blocking insulating layer on the channel layer, and the thickness of the blocking insulating layer is larger than that of the tunneling insulating layer.
Description
Technical Field
The invention belongs to the field of memories, and particularly relates to a floating gate memory with top gate regulation and control, a preparation method thereof and a logic device comprising the floating gate memory.
Background
Floating gate memories, also known as floating gate transistors, which are a member of the non-volatile memory family, have wide application in integrated circuits. Referring to a schematic structure of a prior art floating gate memory shown in fig. 1, it includes a substrate 7 and a channel layer 5, a tunnel insulating layer 4, a floating gate layer 3, a blocking insulating layer 2 and a control gate (top gate) 1 sequentially arranged on the substrate 7, and a source 6 and a drain 8 arranged on both sides of the tunnel insulating layer 4 above the channel layer 5. The storage mechanism of the floating gate memory in the prior art mainly comprises: when a voltage pulse is applied to the control gate 1, the voltage difference between the control gate 1 and the source/drain causes carriers in the channel layer 5 to tunnel into the floating gate layer 3 through the tunneling insulating layer 4 and to be blocked by the blocking insulating layer 2, thereby storing a large number of carriers in the floating gate layer 3; when the voltage pulse is removed, the local electric field generated by the floating gate layer 3 modulates the semiconductor material of the channel layer 5. For example, for an n-type doped semiconductor (such as phosphorus, arsenic, etc.), when a positive voltage pulse is applied to the control gate 1, electrons in the channel layer 5 tunnel into the floating gate layer 3 through the tunneling insulating layer 4, so that a large amount of electrons are stored in the floating gate layer 3, and after the voltage pulse is removed, the electrons in the floating gate layer 3 perform electrostatic regulation on the channel layer 5, so that the upper surface of the semiconductor is in a depletion state, and at this time, the channel layer 5 is in an off state, wherein the off state refers to that the current of the channel layer 5 is in an off state, that is, in a current non-conducting state; when a negative voltage pulse is applied to the control gate 1, holes in the channel layer 5 tunnel into the floating gate layer 3 through the tunneling insulating layer 4, so that a large number of holes are stored in the floating gate layer 3, after the voltage pulse is removed, the holes in the floating gate layer 3 carry out electrostatic regulation and control on the channel layer 5, the surface of the semiconductor presents an accumulation state, and at the moment, the channel layer 5 is in an on state, and the on state refers to that the current of the channel layer 5 is in an on state, namely, a current conduction state. Although the floating gate memory can store data for a long time and has a relatively high programming speed, for the same doping type semiconductor, after the positive/negative pulse voltage is applied, the channel current uniformly reaches a low/high state, so that an effective logic state cannot be realized, which is unfavorable for the application of the floating gate memory in an integrated circuit. Technicians have attempted to implement wells of different conductivity types by varying the doping of different types of impurities, but this makes the process more cumbersome and complex.
Disclosure of Invention
It is therefore an object of the present invention to overcome the above-mentioned drawbacks of the prior art by providing a floating gate memory comprising a substrate layer, a channel layer, a blocking insulating layer, a floating gate layer, a tunneling insulating layer and a control gate, which are sequentially arranged above the substrate layer, and further comprising source and drain electrodes arranged on both sides of the blocking insulating layer above the channel layer, wherein the thickness of the blocking insulating layer is greater than the thickness of the tunneling insulating layer.
According to the floating gate memory of the present invention, preferably, the substrate layer is Si.
Preferably, the channel layer is MoS 2 Two-dimensional materials or silicon semiconductors.
The floating gate memory according to the present invention preferably has the barrier layer or the tunneling layer made of hBN two-dimensional material or SiO 2 。
According to the floating gate memory of the present invention, preferably, the floating gate layer is an MLG two-dimensional material or polysilicon.
According to the floating gate memory of the present invention, preferably, the control gate, the source and the drain are metal.
According to the floating gate memory of the present invention, preferably, the control gate, the source and the drain are of a Cr/Au double-layer structure.
According to the floating gate memory of the present invention, preferably, the control gate has an area smaller than that of the floating gate layer.
The invention also provides a preparation method of the floating gate memory, which comprises the following steps:
preparing a channel layer on a substrate;
sequentially stacking a blocking insulating layer, a floating gate layer and a tunneling insulating layer on the channel layer;
preparing a control gate on the tunneling insulating layer; and
and respectively preparing a source electrode and a drain electrode on two sides of the blocking insulating layer above the channel layer.
The invention also provides a logic device, which comprises a substrate and a channel layer arranged on the substrate, and
the first blocking insulating layer, the first floating gate layer, the first tunneling insulating layer and the first control gate are sequentially arranged on the first region of the channel layer, and the thickness of the first blocking insulating layer is larger than that of the first tunneling insulating layer;
the second tunneling insulating layer, the second floating gate layer, the second blocking insulating layer and the second control gate are sequentially arranged on the second region of the channel layer, and the thickness of the second blocking insulating layer is larger than that of the second tunneling insulating layer;
a source and a drain respectively disposed outside the first region and the second region over the channel layer; and
an output disposed over the channel layer between the first region and the second region.
Compared with the prior art, the floating gate memory is based on the stacking of two-dimensional semiconductor materials, and the novel floating gate memory complementary with the traditional silicon-based floating gate memory technology is realized through the structural design of the floating gate memory regulated and controlled by the top gate, so that the floating gate memory manufactured by utilizing a single doped semiconductor can realize logic functions.
Drawings
Embodiments of the invention are further described below with reference to the accompanying drawings, in which:
fig. 1 is a schematic structure diagram of a floating gate memory according to the prior art.
Fig. 2 shows a schematic structure of a floating gate memory according to an embodiment of the present invention.
Fig. 3 shows a transfer characteristic of a floating gate memory according to an embodiment of the present invention.
Fig. 4 and 5 illustrate the nonvolatile memory function of the floating gate memory according to the embodiment of the present invention, respectively.
Fig. 6 illustrates a multi-value storage function of a floating gate memory according to an embodiment of the present invention. And
Fig. 7 shows a schematic diagram of a logic device structure according to an embodiment of the present invention.
Detailed Description
For the purpose of making the technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 2, a schematic structure of a floating gate memory according to an embodiment of the present invention includes a substrate layer 207, a channel layer 205, a blocking insulating layer 202, a floating gate layer 203, a tunneling insulating layer 204, and a control gate (top gate) 201 sequentially disposed on the substrate layer 207, and a source 206 and a drain 208 disposed on both sides of the blocking insulating layer 202 over the channel layer 205. The floating gate memory of the embodiment of the invention exchanges the positions of the tunneling insulating layer and the blocking insulating layer on the basis of the floating gate memory of the prior art shown in fig. 1.
The storage mechanism of the floating gate memory of this embodiment is mainly: when a voltage pulse is applied to the control gate 201, carriers (electrons or holes) in the floating gate layer 203 (usually a conductor) tunnel through the tunneling insulating layer 204 to the control gate 201 and are transferred away under the action of an electric field, and meanwhile, carriers in the channel layer 205 tunnel through the blocking insulating layer 202 to the floating gate layer 203 under the action of an electric field, because the thickness of the blocking insulating layer 202 is larger than that of the tunneling insulating layer 204, for example, the tunneling insulating layer 204 is SiO with a thickness of 5nm 2 The barrier insulating layer 202 is SiO with a thickness of 8nm 2 Carriers tunneled from the floating gate layer 203 to the control gate 201 through the tunnel insulating layer 204 are much larger than carriers tunneled from the channel layer 205 to the floating gate layer 203 through the blocking insulating layer 202A large number of carriers (holes or electrons) are eventually left in the floating gate layer 3, corresponding to "net" carriers being able to be blocked by the blocking insulating layer by tunneling through the insulating layer; when the voltage pulse is removed, the "net" carrier local electric field in the floating gate layer 203 modulates the semiconductor material of the channel layer 205. For example, for an n-type doped semiconductor, when a positive voltage pulse is applied to the control gate 201, electrons in the floating gate layer 203 enter the control gate 201 through the tunneling insulating layer 204, a very small amount of electrons in the channel layer 5 enter the floating gate layer 3 through the blocking insulating layer 202, a large amount of holes are finally stored in the floating gate layer 203, and after the voltage pulse is removed, the holes in the floating gate layer 203 carry out electrostatic regulation and control on the channel layer 205, so that the upper surface of the semiconductor presents an accumulation state, and the channel layer 205 is in an on state; when a negative voltage pulse is applied to the control gate 201, holes in the floating gate layer 203 enter the control gate 201 through the tunneling insulating layer 204, a very small amount of holes in the channel layer 205 tunnel into the floating gate layer 203 through the blocking insulating layer 202, a large amount of electrons are finally stored in the floating gate layer 203, after the voltage pulse is removed, the electrons in the floating gate layer 203 carry out electrostatic regulation and control on the channel layer 205, the upper surface of the semiconductor presents a depletion state, and the channel layer 205 is in an off state.
It can be seen that, for the floating gate memory according to the embodiment of the present invention, by applying different pulse voltages to the control gate 201, different types of carriers can be stored in the floating gate layer 203, so that the current of the channel layer 205 can be converted between the on state and the off state. Because the tunneling insulating layer 204 and the blocking insulating layer 202 have higher electron and hole barriers than the floating gate layer 203, carriers can be stored in the floating gate layer 203 without leakage, so that the memory has the characteristic of non-volatility. By inputting pulse voltages of different polarities at the control gate 201, the channel layer 205 can be realized to be transitioned in different current states. This is in contrast to the storage mechanism of conventional floating gate memories, thus enabling the reverse program/erase operation of conventional floating gate memories.
According to the embodiment of the present invention, the area of the control gate 201 is preferably smaller than the area of the floating gate layer 203, so that the control gate 201 cannot directly participate in the regulation of the channel layer 205, thereby ensuring the accuracy of regulation.
In one embodiment of the present invention, the channel layer is a silicon semiconductor, the tunnel insulating layer and the blocking insulating layer are silicon oxide, the floating gate layer is polysilicon, and the control gate is metal. For example, the control gate 201 is polysilicon and the tunneling insulating layer 204 is SiO 2 The floating gate layer 203 is polysilicon, and the blocking insulating layer is SiO 2 The channel layer 205 is silicon, the source 206 and drain 208 are metal, and the substrate layer 207 is heavily doped silicon.
In another embodiment of the present invention, the channel layer, the tunneling insulating layer, the blocking insulating layer, and the floating gate layer are all two-dimensional materials, thereby reducing interface trap charge density. For example, the control gate 201 is a metal, such as a Cr/Au bilayer structure, including Cr with a thickness of 6nm and Au with a thickness of 60nm, wherein Cr can increase adhesion between the metal and the two-dimensional material, while Au can facilitate the needle insertion test, the tunneling insulating layer 204 is hBN two-dimensional material, the floating gate layer 203 is MLG two-dimensional material, the blocking insulating layer 202 is hBN two-dimensional material, and the channel layer 205 is MoS 2 The two-dimensional material, source 206 and drain 208, are metal, such as a Cr/Au bilayer structure comprising Cr having a thickness of 6nm and Au having a thickness of 60nm, and the substrate layer 207 is a Si substrate whose surface is typically oxidized to form SiO 2 Structure of Si. Adopting two-dimensional material as tunneling insulating layer, compared with SiO 2 The tunneling layer has a lower critical tunneling field strength; the two-dimensional material is adopted as the floating gate layer, the interface is van der Waals force, and compared with a silicon oxide interface in a silicon process, fewer dangling bonds are arranged, and the data storage time is longer.
See FIG. 3 for a transfer characteristic of the floating gate memory of this embodiment, where V cg Representing the voltage applied to the control gate 201, I ds Representing channel current, channel material selection MoS 2 . When V is cg When the voltage is between-16V and +9V, the current flows out in the cut-off state; when Vcg is between +9V and-16V, the current is in an on state; it can be seen that its transfer curve presents a counter-clockwise storage window.
Fig. 4 and 5 illustrate the nonvolatile memory function of the floating gate memory according to the embodiment of the present invention, respectively. FIG. 4 shows data of a floating gate memoryThe storage capacity, the abscissa indicates time, and the ordinate indicates source-drain current I ds . As can be seen from fig. 4, the current state of the floating gate memory can be maintained for more than 6,000 seconds, which indicates that the floating gate memory has excellent data retention capability. FIG. 5 shows the endurance of a floating gate memory, with the abscissa representing the number of cycles and the ordinate representing the source-drain current I ds . As can be seen from fig. 5, the current state of the floating gate memory remains unchanged after more than 1000 cycles, indicating that the floating gate memory has excellent endurance.
Fig. 6 shows a multi-value storage function of the floating gate memory of this embodiment. The abscissa of FIG. 6 represents time, and the ordinate represents source-drain current I ds . As can be seen from fig. 6, the floating gate memory has 16 stable memory states, illustrating the capability of the floating gate memory device to have multi-valued memory.
The preparation method of the floating gate memory according to one embodiment of the invention comprises the following steps:
step 1: providing a silicon wafer as a substrate, and treating the surface of the silicon wafer by utilizing plasma so as to reduce hanging bonds and clean the surface of the silicon wafer;
step 2: growing, for example MoS, on the surface of a silicon wafer by Chemical Vapor Deposition (CVD) 2 A channel layer;
step 3: sequentially stacking an hBN barrier insulating layer, an MLG floating gate layer and an hBN tunneling insulating layer, which are mechanically stripped on PDMS in advance, on a MoS by using a transfer table 2 On the channel layer;
step 4: in MoS 2 Source and drain electrodes are prepared on the channel layer, and the source and drain electrodes are respectively connected with the parts of the channel material at two sides of the longitudinal heterojunction.
Step 5: and preparing a control gate electrode above the hBN tunneling insulating layer, wherein the control gate electrode is aligned above the floating gate layer.
According to another embodiment of the present invention, in step 2, the channel layer, which has been mechanically stripped in advance, is stacked on the Si substrate.
According to a further embodiment of the invention, the use of a needle tip to scribe the channel layer into strips facilitates the fabrication of subsequent devices.
Yet another embodiment of the present invention provides a logic device that interconnects a conventional floating gate memory with the novel floating gate memory of the embodiments of the present invention to achieve complementation of high and low current states and to achieve different output logic by applying pulse voltages of different polarities. As shown in a schematic structural diagram of a logic device of this embodiment in fig. 7, a conventional floating gate memory and a novel floating gate memory share a substrate 707 and a channel layer 705, the channel layer 705 is disposed over the substrate 707, a first blocking insulating layer 7041, a first floating gate layer 7031, a first tunneling insulating layer 7021, and a first control gate 7011 are sequentially disposed over a first region of the channel layer 705, a second tunneling insulating layer 7022, a second floating gate layer 7032, a second blocking insulating layer 7042, and a second control gate 7012 are sequentially disposed over a second region of the channel layer 705, a source 7061 and a drain 7062 are disposed outside the first region and the second region, respectively, over the channel layer 705, and an output electrode 708 is disposed between the first region and the second region over the channel layer 705. When a positive pulse voltage is applied to the control gates 7011 and 7012, the current of the channel layer 705 (i.e., the current of the first region) of the novel floating gate memory in the embodiment of the present invention is in a high state, and the current of the channel layer 705 (i.e., the current of the second region) of the conventional floating gate memory is in a low state, where the potential of the output electrode 708 is the same as the potential of the source 7061; when a negative pulse voltage is applied to the control gates 7011 and 7012, the current of the channel layer 705 of the novel floating gate memory of the present invention is in a low state, and the current of the channel 705 of the conventional floating gate memory is in a high state, and at this time, the potential of the output electrode 708 is the same as that of the drain electrode 7062, and when a driving voltage is applied to the source electrode 7061 and the drain electrode 7062, the output electrode 708 changes according to the change of the polarity of the pulse voltage applied to the control gates 7011 and 7022.
Embodiments of the present invention provide a novel top gate regulated floating gate memory with program/erase operations that are contrary to conventional floating gate memories. In the process of applying the control gate voltage pulse, the floating gate device undergoes a tunneling process twice, and the number of carriers reaching the floating gate through the blocking layer is far smaller than the number of carriers reaching the control gate through the tunneling layer, so that the storage mechanism of the floating gate memory is changed, and a novel floating gate transistor is realized. The novel floating gate memory of the embodiment of the invention has the following main structure and functions: (1) a device structure having a floating gate memory. (2) The material composing the channel is an n-type semiconductor, and the conduction mechanism is electron conduction. (3) The transfer curve is a counter-clockwise hysteresis, i.e. when a voltage is applied to the control gate and the source drain current is read, a counter-clockwise memory window occurs. (4) When a positive voltage pulse is applied to the control gate, the device presents a high current state; when a negative voltage pulse is applied to the control gate, the device assumes a low current regime.
In addition, the novel floating gate memory has a device structure compatible with a silicon process, can be connected in series with the memory taking the traditional polysilicon as the floating gate at the same time, and realizes the storage and logic change of the device in different states of high and low currents by using pulse voltage applied to the control gate.
While the invention has been described in terms of preferred embodiments, the invention is not limited to the embodiments described herein, but encompasses various changes and modifications that may be made without departing from the scope of the invention.
Claims (10)
1. The floating gate memory comprises a substrate layer, a channel layer, a blocking insulating layer, a floating gate layer, a tunneling insulating layer, a control gate, a source electrode and a drain electrode, wherein the channel layer, the blocking insulating layer, the floating gate layer, the tunneling insulating layer and the control gate are sequentially arranged on the substrate layer, the source electrode and the drain electrode are arranged on two sides of the blocking insulating layer on the channel layer, and the thickness of the blocking insulating layer is larger than that of the tunneling insulating layer.
2. The floating gate memory of claim 1, wherein the substrate layer is Si.
3. The floating gate memory of claim 1 wherein the channel layer is MoS 2 Two-dimensional materials or silicon semiconductors.
4. The floating gate memory of claim 1, wherein the blocking layer or the tunneling layer is hBN two-dimensional material or SiO 2 。
5. The floating gate memory of claim 1, wherein the floating gate layer is an MLG two-dimensional material or polysilicon.
6. The floating gate memory of claim 1, wherein the control gate, the source, and the drain are metal.
7. The floating gate memory of claim 6, wherein the control gate, the source and the drain are Cr/Au bilayer structures.
8. The floating gate memory of any of claims 1-7, wherein an area of the control gate is smaller than an area of the floating gate layer.
9. A method of manufacturing a floating gate memory according to any one of claims 1-8, comprising the steps of:
preparing a channel layer on a substrate;
sequentially stacking a blocking insulating layer, a floating gate layer and a tunneling insulating layer on the channel layer;
preparing a control gate on the tunneling insulating layer; and
and respectively preparing a source electrode and a drain electrode on two sides of the blocking insulating layer above the channel layer.
10. A logic device includes a substrate and a channel layer disposed over the substrate, an
The first blocking insulating layer, the first floating gate layer, the first tunneling insulating layer and the first control gate are sequentially arranged on the first region of the channel layer, and the thickness of the first blocking insulating layer is larger than that of the first tunneling insulating layer;
the second tunneling insulating layer, the second floating gate layer, the second blocking insulating layer and the second control gate are sequentially arranged on the second region of the channel layer, and the thickness of the second blocking insulating layer is larger than that of the second tunneling insulating layer;
a source and a drain respectively disposed outside the first region and the second region over the channel layer; and
an output disposed over the channel layer between the first region and the second region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2022111987115 | 2022-09-29 | ||
| CN202211198711 | 2022-09-29 |
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