KR20100123250A - Non-volatile memory device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a method for manufacturing the same are provided to improve the reliability of a device by increasing a possibility of charging nano-crystal through formation of a memory having nano-crystal layer on an organic layer. CONSTITUTION: A first organic layer(30) is located on the surface a first electrode. A nano-crystal layer(50) is located on the surface of the first organic layer. A second organic layer(60) is located on the surface the nano-crystal layer. The second electrode is located on the surface the second organic layer.

Description

Non-volatile memory device and manufacturing method thereof {NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including an organic material layer having two conductive states at the same voltage, and a method of manufacturing the same.

Current memory devices are volatile Dynamic-Ramdon Access Memory (D-RAM) and nonvolatile flash memory.

The DRAM adjusts the channel width under the gate according to the voltage applied to the gate to form a channel between the source and drain terminals, and charges or discharges electrons in a capacitor connected to the source terminal. Afterwards, the device reads the charge and discharge states of the capacitor and separates the data of 0 and 1. This DRAM has a disadvantage of continuously recharging the capacitor, which is called a volatile memory device, and when power is not applied, there is a problem in that power consumption is lost because data input to the device is lost due to leakage current. .

In addition, the NAND flash memory generates an F-N tunneling phenomenon due to a voltage applied to the control gate and the channel region, and charges or discharges electrons in the floating gate through the F-N tunneling phenomenon. It is a device that distinguishes data between 0 and 1 by changing the threshold voltage of the channel region according to the state of charge and discharge, and reading the change of the threshold voltage. This flash memory uses FN tunneling, so the voltage used in the device becomes very large. Flash memory requires charging or discharging electrons to the floating gate through FN tunneling made of polysilicon. This results in a slow data processing rate of μ-sec.

In addition, in order to implement the above-described conventional memory device, since the memory cell size is rather large (8F ² ) and at least several tens of steps or more, the integration degree of the device is difficult to be improved, and the unit cost is high and it is difficult to maintain high yield.

Currently, researches are being actively conducted to overcome the disadvantages of DRAM and flash memory and to implement next-generation memory devices having the advantages thereof.

The research areas of the next-generation memory devices have been separated in various ways according to the materials constituting the cells which are basic units therein. That is, when the material is cooled after applying a current to the phase change material, data 0 and 1 are generated by using the difference of resistance depending on whether the material becomes a solid state with low resistance or a large amorphous state or a voltage is applied to the conductive organic material. Memory device using bidirectional conduction characteristics with high resistance and low resistance at the same voltage appearing at the same voltage, or by applying power to the material using ferroelectric material to have residual polarization property, or to use as memory device Attempts have been made to store data using ferromagnetic materials of the N and S poles. In addition, research is being actively conducted on nonvolatile memory devices in which planar floating gates replace quantum dots of metal, silicon, or compound semiconductors in planar silicon.

However, finding the process conditions for applying these materials to highly integrated memory devices by utilizing their properties remains a common problem of current generation memory devices.

In particular, the nonvolatile memory using organic materials (ie, organic materials) of the next-generation memory has not been applied to actual mass production, and it is difficult to find accurate process conditions for manufacturing the memory device. In particular, it is difficult to develop an organic material having stable bistable characteristics, and there is a disadvantage in that the reliability of the device is deteriorated due to a decrease in charge transfer efficiency through the organic material.

Accordingly, the present invention provides a non-volatile memory device that can improve the reliability of the device by increasing the probability of charge charging the nanocrystals by fabricating an organic material layer that can increase the charge transfer efficiency and charge transfer speed to solve the above problems; The manufacturing method is provided.

According to the present invention, there is provided a first electrode, a first organic material layer on the first electrode, a nanocrystal layer on the first organic material layer, a second organic material layer on the nanocrystal layer, and the second A second electrode is disposed on the organic material layer, and the first organic material layer or the second organic material layer provides a nonvolatile memory device including a donor material and an acceptor material.

The donor material or the acceptor material may be a high molecular organic material or a low molecular organic material, respectively.

The donor material is P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy-4- (0-dispersed1) -2,5-phenylene -Vinylene), polyindole, pericarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof It is possible to include more than one.

The acceptor material may be fullerene or a derivative thereof.

The donor material is P3HT, and the acceptor material may be PCBM ([6,6] -phenyl-C61 butyric acid methyl ester).

The nano crystal layer preferably includes a nano crystal and a barrier material surrounding the nano crystal.

The nanocrystals may be at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof.

The barrier material may be any one selected from oxides of the nanocrystal material, Al 2 O 3, TiO 2, and carbazole terminated thiol (CB).

According to the input data voltages applied across the first and second electrodes, various resistance states may be changed, and a multi-level output current may be generated during a read operation.

As described above, the present invention can fabricate a memory device in which a nanocrystal layer is formed on an organic material layer including a donor material and an acceptor material, thereby increasing the charge charging probability of the nanocrystal to improve reliability of the device.

In addition, the present invention can repeatedly perform read, write and erase operations through an organic material layer having bistable conductive properties, maintain data stored in a cell even when power is not applied, and manufacture a multilevel memory. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Like numbers refer to like elements in the figures.

1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a nonvolatile memory device according to a modification of the embodiment.

Referring to FIG. 1, a nonvolatile memory device according to an embodiment of the present invention may include a first and second bistable conduction characteristics between upper and lower electrodes 20 and 70 and upper and lower electrodes 20 and 70. The nano organic layer 30 is disposed between the second organic layer 30 and 60 and the first and second organic layer 30 and 60. In one embodiment of the present invention, the nano crystal layer 50 is formed as a single layer, the nano crystal layer 50 may be formed in a plurality of layers.

As the substrate 10, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used, that is, a plastic substrate, a glass substrate, an Al ₂ O ₃ substrate, a SiC substrate, a ZnO substrate, a Si substrate, a GaAs substrate, or a GaP substrate. At least one of a LiAl ₂ O ₃ substrate, a BN substrate, an AlN substrate, an SOI substrate, and a GaN substrate may be used. When using a semiconductive substrate and a conductive substrate should be separated by an insulator between the lower electrode (20).

The upper and lower electrodes 20 and 70 may use any material having electrical conductivity. The electrode is preferably metal such as Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof having low electrical resistance and excellent interfacial properties with conductive organic materials.

The first and second organic material layers 30 and 60 may include a donor material and an acceptor material. Here, the donor material refers to a molecule that gives an electron, and the acceptor material refers to a molecule that receives an electron. The donor material or the acceptor material may be a high molecular material or a low molecular material, respectively. In this embodiment, a high molecular material is used as the donor material and a low molecular material is used as the acceptor material.

Wherein the donor material is P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy-4- (0-dispersed1) -2,5-phenyl Ethylene-vinylene), polyindole, pericarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof Any one or more materials may be used.

As the acceptor material, fullerene or a derivative thereof is used. For example, PCBM ([6,6] -phenyl-C61 butyric acid methyl ester) can be used.

As described above, according to the exemplary embodiment of the present invention, the organic material memory characteristics may be improved by using the organic material including the donor material and the acceptor material as the first and second organic material layers 30 and 60. This is because the first and second organic material layers 30 and 60 form a charge transfer complex by the donor material and the acceptor material. The charge transfer complex changes to an excited state due to two or more intermolecular attraction, which stabilizes the states of the two molecules while generating charge transfer between them.

When using a single organic material, electrons are conducted through hopping in the organic material. However, when forming a charge transfer complex using a donor material and an acceptor material as in one embodiment of the present invention, charge transfer occurs not only through hopping but also through charge transfer. Therefore, not only the overall charge transfer efficiency in the organic layers 30 and 60 but also the charge transfer due to the rapid charge transfer between the donor material and the acceptor material are also increased. As such, by increasing the transfer efficiency of the charge, the probability of charging the nanocrystal 20 generated in the organic material layers 30 and 60 may be increased, thereby enabling more reliable and improved nonvolatile memory behavior. . In addition, the organic layer has bistable characteristics, that is, two conductivity at the same voltage.

In an embodiment of the present invention, the organic material layer is formed by mixing the donor material and the acceptor material. Alternatively, the organic material layer may be formed to include the donor material layer and the acceptor material layer.

The nanocrystal layer 50 includes a plurality of crystalline nanocrystals 50a and a barrier material 50b surrounding the nanocrystals 50a. The nanocrystal layer 50 is formed by depositing a metal layer and plasma or thermal oxidation of the deposited metal layer to include a nanocrystal 50a including a metal layer material and a barrier material 50b including an oxide of a metal layer material. It can be formed to.

Here, at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof may be used as the metal layer. Then, the oxidation process may be carried out to O ₂ plasma oxidation process.

Of course, the present invention is not limited thereto, and nanocrystals may be formed through oxidation of a metal in the deposition chamber. However, it is preferable to use a process of forced oxidation through an O ₂ plasma process along grain boundaries to form stable nanocrystals having a constant and uniform size.

In the present embodiment, the nanocrystal layer 50 was formed using Ni. Here, the crystalline material (ie nano crystal) is Ni nano crystal and the barrier material is Ni _x O _y (eg, NiO). This is because the Ni nanocrystal layer is formed by oxidizing the surface of the Ni metal layer.

Here, the thickness of the nanocrystal layer 50 is preferably 1 to 40nm. In FIG. 1, a single nanocrystal layer 50 is shown. However, the present invention is not limited thereto, and a multilayer nanocrystal layer may be formed. The uniformity of the thickness of the surface oxidized nanocrystal layer 50 refers to the formation of a nanocrystal layer having a thickness in the range of about -30 to + 30% of the target nanocrystal layer thickness.

As described above, the nanocrystal layer 50 of the present embodiment is formed with a uniform thickness of 1 to 40 nm or less between the first and second organic material layers 30 and 60, so that the surface of the nanocrystal has oxidized surface between organic materials. The energy gap becomes larger, which can improve the device's data retention. In addition, when the nanocrystals 50 are formed in the organic layers 30 and 60, the device may have various resistance states and output various levels of current according to voltages applied to the upper and lower electrodes 20 and 70. Therefore, one or more bits of data may be stored in the unit cell.

And as shown in FIG. 2, a basic laminated structure can also be formed in multiple times. That is, the lower electrode 20 is positioned on the substrate 10, the first organic layer 30 is positioned on the lower electrode 20, and the first nanocrystal layer 50 is disposed on the first organic layer 30. The second organic material layer 60 is positioned on the first organic material layer 30 including the first nano crystal layer 50, and the intermediate electrode 80 is positioned on the second organic material layer 60. The third organic material layer 90 is positioned on the 80, the second nanocrystal layer 100 is positioned on the third organic material layer 90, and the fourth organic material layer 110 is disposed on the second nanocrystal layer 100. The upper electrode 120 is positioned on the fourth organic material layer 110.

Hereinafter, a method of manufacturing the above-described nonvolatile memory device will be described with reference to the drawings.

3 to 8 are diagrams for describing a method of manufacturing a nonvolatile memory device according to the present embodiment. In the figure, (a) is a plan view for explaining the manufacturing method of the nonvolatile memory device, (b) is a cross-sectional view taken along the line A-A of (a).

9 is a conceptual cross-sectional view for explaining a method for manufacturing a nanocrystal layer according to the present embodiment.

Referring to FIG. 3, the lower electrode 20 is formed on the substrate 10. That is, the lower electrodes 20 arranged in one direction are formed by using evaporation. At this time, a silicon substrate or a glass substrate may be used as the substrate 10.

In more detail, first, the substrate 10 is loaded into a chamber (not shown) for metal deposition, and then a region where the lower electrode 20 is to be formed is formed by using a first shadow mask (not shown). Expose Subsequently, the exposed area of the substrate 10 by evaporating a metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining a pressure of 10 ^-6 to 10 ^-3 Pa and maintaining a deposition rate of 2 to 7 Pa / s. The lower electrode 20 of metal is formed in it. In this embodiment, Al is used as the lower electrode 20. However, the present invention is not limited thereto, and may be manufactured using at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, or an alloy thereof. The lower electrode 20 may have a thickness of about 50 nm to about 100 nm. A predetermined washing process may be performed before and after the lower electrode 20 deposition process.

Referring to FIG. 4, the first organic material layer 30 is formed on the substrate 10 on which the lower electrode 20 is formed.

To this end, first, an organic raw material for manufacturing the first organic material layer 30 is manufactured. The donor and acceptor materials described above are prepared for the preparation of organic raw materials. The donor material and the acceptor material are placed in an organic solvent and blended.

In the present embodiment, P3HT was used as a donor material and PCBM was used as an acceptor material.

Subsequently, the prepared organic material is coated on the substrate 10 on which the lower electrode 20 is formed to form the first organic material layer 30.

In this case, the first organic material layer 30 may be coated through various coating methods. In an embodiment of the present invention, the first organic layer 30 is formed through spin coating, and may be annealed in a nitrogen atmosphere after spin coating.

In this case, the thickness of the first organic material layer 30 coated on the substrate 10 may be 10 to 100 nm.

In addition to the above-described method, the first organic material layer 30 may be formed on the substrate 10 by various methods in addition to the above-described coating method. For example, it may be formed on a substrate by a printing method such as printing or screen printing.

5, 6, and 9, the metal layer 40 is deposited on the first organic material layer 30. To this end, the substrate 10 on which the first organic layer 30 is formed is loaded into a chamber (not shown) for metal deposition. The first organic material layer 30 on which the nanocrystal layer 40 is to be formed is exposed using a third shadow mask (not shown). Then, the first organic material layer exposed by evaporating the metal material at a temperature of 800 to 1500 degrees Celsius while maintaining a pressure of 10 ^-6 to 10 ^-3 Pa and maintaining a deposition rate of 0.1 to 7.0 Pa / s. 30 to 1 to 40nm to form a metal layer 40 of thickness.

At this time, the metal layer 40 is not formed in the form of nanocrystals because of the high deposition rate, and is formed of a metal thin film having a grain boundary as shown in FIG.

Then, the substrate 10 on which the metal layer 40 is formed is loaded into a chamber for oxidation. RF power of 50 to 300 W is applied to the chamber, an AC bias of 100 to 200 V is applied, and an oxidation process is performed by injecting O ₂ gas at a pressure of 0.5 to 3.0 Pa. At this time, the process time is preferably carried out for about 50 to 500 seconds.

As described above, when the oxidation process using the O ₂ plasma is performed, the nanocrystal layer 50 including the nanocrystal 50a and the barrier material 50b surrounding the nanocrystal 50a is formed. Here, the barrier material 50b is formed of an oxide of metal. In one embodiment of the present invention to form a Ni nano crystal layer.

In detail, as shown in FIG. 9C, the O ₂ plasma penetrates along the boundary of the metal layer 40 having the grain boundary and oxidizes along the boundary as shown in FIG. 9B. Ni nanocrystals of size are formed. In this case, the nanocrystal layer 50 may be formed in a thickness of 1 to 40 nm according to the thickness of the metal layer 40. Of course, the thickness of the metal layer 40 may be formed to be thick, but when the metal layer 40 becomes too thick (50 nm or more), the O ₂ plasma does not sufficiently penetrate into the grain boundary of the metal layer 40 so that the nano crystal layer 50 may be formed. ) May not be effectively formed. As shown in (d) of FIG. 9, the nanocrystal layer 50 after the oxidation process is completed is formed by oxidizing a nanocrystal of a crystalline material of Ni nanocrystal and a nanocrystalline surface of Ni0 amorphous material.

Here, the above-described deposition and oxidation processes of the metal layer 40 may be repeated a plurality of times to form a multilayer nanocrystal layer 50.

In one embodiment of the present invention, the nano crystal layer 50 may be manufactured through various processes in addition to the oxidation process using the above-described plasma.

For example, in order to fabricate the nanocrystal layer 50, first, a first barrier material layer, a metal layer, and a second barrier material layer are sequentially deposited on the first organic material layer 30. Then, the curing process is performed for 0.5 to 4 hours at a temperature of 150 to 300 degrees. This allows the first and second barrier material layers to enclose the nanocrystals of the metal in the metal layer. In this case, Al ₂ O ₃ or TiO ₂ may be used as the barrier material. Through this, the nanocrystal layer 50 including the nanocrystal 50a and the barrier material 50b may be manufactured. In addition, the nanocrystals surrounded by the barrier material may be prepared, and then dispersed in an organic material and spin coated to form a nanocrystal dispersed layer in the organic material layer. In this case, the barrier material may be CB (carbazole terminated thiol).

Referring to FIG. 7, the second organic material layer 60 is formed on the first organic material layer 30 on which the nanocrystal layer 50 is formed in the same manner as the first organic material layer 30.

Referring to FIG. 8, the upper electrode 70 is formed on the substrate 10 including the second organic layer 60. In this case, the upper electrode 70 may be formed in a direction crossing each other with the lower electrode 30.

To this end, first, the substrate 10 formed up to the second organic layer 60 is loaded into a chamber for metal deposition, and then a region where the upper electrode 70 is to be formed is exposed using a fourth shadow mask. Thereafter, the pressure inside the chamber is set to 10 ⁻⁶ to 10 ⁻³ Pa, and the second organic layer 60 exposed by evaporating the metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining the deposition rate at 2 to 7 μs / s. ) And a metal electrode in the region of the substrate 10. In this embodiment, Al is preferably used as the upper electrode 70, and the thickness of the electrode may be 60 to 100 nm.

Subsequently, although not shown, a separate metal wiring process may be performed to connect each of the upper electrode 70 and the lower electrode 30 to an external electrode. Through this, the upper electrode 70 and the lower electrode 30 are electrically connected to separate pads. Then, driving means for applying various input power sources to these pads is connected. Accordingly, various input power sources may be applied to the electrodes to have various output current levels according to the resistance state of the device. Such device characteristics are described below.

Although a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention has been described, the manufacturing method is not limited thereto and may be manufactured by various methods.

For example, the electrode and the nano crystal layer may be formed through an E-beam deposition process, a sputtering process, a CVD process, an ALD process, and the like in addition to a thermal evaporation process.

In addition, the electrode may be formed on the entire structure, and then the shape may be manufactured through a patterning process. That is, after forming a conductive material on the substrate, the electrode may be formed by removing the conductive material in the region except the electrode through an etching process using a mask. The oxidation process may also be carried out using wet and dry oxidation methods.

The following describes the operation and characteristics of the memory device of this embodiment produced by the above-described configuration and manufacturing method.

10 is a graph illustrating current voltage characteristics of a memory device according to an exemplary embodiment.

Here, FIG. 10 is a graph illustrating voltage and current characteristics of a nonvolatile memory device having a Ni nanocrystal layer using an organic material in which P3HT and PCBM are mixed as an organic material layer.

Referring to FIG. 10, when a voltage is applied to a nonvolatile memory device according to an embodiment of the present invention, as shown in the graph of FIG. 10, various current states (or resistance states) are provided within a predetermined voltage range.

For example, when the lower electrode is connected to the ground and the upper electrode is connected to a predetermined voltage source to sequentially increase the voltage of the voltage source in the positive direction, the current gradually increases exponentially to a certain level of the voltage V _th . _Has a high resistance state (I _off ). Thereafter, when a voltage of a predetermined level or more (that is, a threshold voltage or a threshold voltage V _th ) or more is applied, the current has a low resistance state I _{on in} which the current rapidly rises. In addition, when the voltage is continuously increased and the maximum current supply voltage V _p is applied, the current has a negative resistance (NDR) state in which the current decreases as the voltage increases. Continuously increasing the voltage has a low resistance state in which the current increases again from the constant voltage (V _e ). That is, it can be seen that the nonvolatile memory device according to the present embodiment has various resistance states. Here, the maximum current voltage power supply (V _p ) refers to the point where the current flow of the device is maximized. Alternatively, the voltage may refer to a voltage at which the negative resistance occurs.

Accordingly, the memory device according to an embodiment of the present invention may implement a multi-level cell in a single memory cell by using the negative resistance state.

If the carrier (ie, charge) is not charged in the nanocrystal whose surface is oxidized by the energy level difference between the nanocrystal layer 50 and the organic layer 30, 60, the current flow increases slightly at a predetermined voltage level. do. However, if the voltage across the organic layers 30 and 60 is greater than or equal to the threshold voltage V _th , the current flows rapidly as the carrier is charged in the nanocrystals whose surface is oxidized. When the carrier is charged in the nanocrystal, the current flow is tens of times to tens of thousands of times as compared with the case where the carrier is not charged. When the voltage across the organic layers 30 and 60 is a negative resistance region voltage, the carrier is partially discharged (or partially charged) in the nanocrystal, which is lower than when the carrier is fully charged and is not charged. It is possible to have a high current flow in an intermediate resistance state. Here, when a voltage (erasing voltage: V _e ) equal to or greater than the negative resistance region NDR is applied, the carrier charged in the nanocrystal layer is discharged to change to an uncharged state.

Furthermore, the organic material layers 30 and 60 of this embodiment are made of an organic material in which a donor material and an acceptor material are mixed. Thus, the movement of carriers in the organic layers 30 and 60 is caused by hopping and carrier transfer. Thus, carrier mobility can be increased by increasing carrier mobility. In addition, it is possible to improve the electrical reliability of the device by increasing the probability of filling the charge charged in the nanocrystal.

In addition, if the voltage of the voltage source is sequentially increased in the negative direction, the current increases with respect to the voltage up to a certain level of voltage, and when the voltage (threshold voltage: V _th ) above the predetermined level is applied, the current rapidly increases. . That is, when a voltage equal to or greater than the threshold voltage V _th is applied, the negative resistance state NDR occurs, and then a current increases with respect to the voltage equal to or greater than the erase voltage V _e . This is due to the symmetrical structure of the device, which has the same mechanism as in the case of the positive directional voltage described above.

11 and 12 are graphs illustrating retention and endurance test results of a nonvolatile memory device according to example embodiments.

As shown in FIG. 11, a nonvolatile memory device using an organic material layer in which P3HT and PCBM are mixed, stores a single resistance state, and reads it several times, thereby stably maintaining each state for 10 ⁵ cycles. At this time, it can be seen that both the low resistance state Ion and the high resistance state Ioff remain stable. In addition, the difference between the low resistance and high resistance states (Ion / Ioff ratio) is also 0.39 × 10 ² .

In addition, as shown in FIG. 12, even when the data is written, read, erased, and read in the nonvolatile memory device as a cycle, the resistance state is applied when each read voltage is applied, even if the cycle is repeated through the endurance test. It can be seen that the current levels are clearly separated.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms. That is, the above embodiments are provided to make the disclosure of the present invention complete and to fully inform those skilled in the art the scope of the present invention, and the scope of the present invention should be understood by the claims of the present application. .

1 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.

2 is a cross-sectional view of a nonvolatile memory device according to another embodiment of the present invention.

3 to 8 illustrate a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

9 is a conceptual cross-sectional view for explaining a method for manufacturing a nanocrystal layer according to an embodiment of the present invention.

10 is a graph illustrating current voltage characteristics of a memory device according to an exemplary embodiment of the present invention.

11 and 12 are graphs showing retention and endurance test results of a nonvolatile memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 substrate 20 lower electrode

30: first organic material layer 50: nano crystal layer

50a: nanocrystal 50b: barrier material

60: second organic material layer 70: upper electrode

Claims (9)

A first electrode; A first organic material layer on the first electrode; A nano crystal layer positioned on the first organic material layer; A second organic material layer on the nanocrystal layer; And A second electrode positioned on the second organic material layer, The first organic material layer or the second organic material layer comprises a donor material and an acceptor material. The method of claim 1, The donor material or the acceptor material is a high molecular organic material or a low molecular organic material, respectively. The method of claim 1, The donor material is P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy-4- (0-dispersed1) -2,5-phenylene -Vinylene), polyindole, pericarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof A nonvolatile memory device comprising one or more. The method of claim 1, And the acceptor material is a fullerene or derivative thereof. The method of claim 1, The donor material is P3HT, and the acceptor material is PCBM ([6,6] -phenyl-C61 butyric acid methyl ester). The method of claim 1, The nano crystal layer includes a nano crystal and a barrier material surrounding the nano crystal. The method of claim 6, The nanocrystal is at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof. The method of claim 6, The barrier material is any one selected from oxides of the nano-crystalline material, Al2O3, TiO2, carbazole terminated thiol (CB). The method of claim 1, The nonvolatile memory device changes into various resistance states according to input data voltages applied across the first and second electrodes, and generates a multi-level output current during a read operation.

Images