KR101433273B1 - Non-volatile memory device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a method of manufacturing the same. The nonvolatile memory device includes a first electrode and a second electrode, an organic material layer provided between the first electrode and the second electrode and including a donor material and an acceptor material, A nonvolatile memory device including at least one layer of a nano-crystal layer, and a method of manufacturing the same.

As described above, the present invention can improve the reliability of a device by increasing the probability of charging a nanocrystal by fabricating a memory device in which a nanocrystal layer is formed between an organic material layer including a donor material and an acceptor material.

Memory, organic, donor acceptor, bistable, nanocrystal layer, oxidation, multi-level, multiple lamination, negative resistance,

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile memory device,

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including an organic layer capable of having two conductive states at the same voltage, and a method of manufacturing the nonvolatile memory device.

Current memory devices are mainly composed of volatile dynamic random access memory (DRAM) and non-volatile flash memory.

The DRAM controls the channel width under the gate according to the voltage applied to the gate to form a channel between the source and the drain terminal and charges or discharges electrons to the capacitor connected to the source terminal. Thereafter, the charge and discharge state of the capacitor is read to distinguish the data of 0 and 1. Such a DRAM has a drawback in that it is required to constantly recharge the capacitor, and it is referred to as a volatile memory device. When the power is not applied, the data inputted to the device is lost due to the leakage current, .

In the NAND flash memory, FN tunneling occurs due to the voltage applied to the control gate and the channel region, and electrons in the floating gate are charged or discharged through the F-N tunneling phenomenon. The threshold voltage of the channel region is changed according to the charging and discharging states, and the threshold voltage change is read to distinguish between the data of 0 and 1. Since such a flash memory utilizes FN tunneling, there is a disadvantage that the voltage used in the device becomes very large. In the flash memory, writing and reading data requires charging or discharging electrons to the floating gate through FN tunneling made of polysilicon The data processing speed is slow in the order of μ-sec (sec).

In order to realize the above-described conventional memory device, the size of the memory cell is rather large (8F ² ) and requires at least several tens of steps, so it is difficult to improve the integration degree of the device, and it is difficult to maintain a high yield and a high yield.

At present, researches are actively carried out to overcome the disadvantages of such DRAM and flash memory and to realize a next generation memory device having advantages of these.

The research fields of this next generation memory device are variously divided according to the material constituting the cell which is the basic unit of the memory device. That is, when the phase-change material is cooled and then cooled, it is possible to make data 0 and 1 by using the resistance difference depending on whether the material becomes a solid state having a low resistance or an amorphous state having a high resistance, , A memory element using a bipolar conductive property in which a high resistance and a low resistance exist at the same voltage appearing at the same voltage, or a ferroelectric material, There is an active attempt to store data using ferromagnetic materials having N-pole and S-pole characteristics. Also, studies have been actively made on a nonvolatile memory device in which flat floating gates are replaced with quantum dots of metal, silicon, or compound semiconductor in silicon having a flat plate structure.

However, in order to utilize the characteristics of these materials and to find the process conditions for applying them to a highly integrated memory device, it is a common task of present-day memory devices.

Particularly, the nonvolatile memory using the organic material (i.e., organic material) in the next generation memory has not been applied to actual mass production, and it is difficult to find an accurate process condition for manufacturing the memory device. In particular, it is difficult to develop an organic material having stable bistable characteristics, and the reliability of the device is deteriorated due to a decrease in the charge transfer efficiency through the organic material.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a nonvolatile memory device and a method of manufacturing the same, which can improve the reliability of a device by increasing the charge charging probability of the nano-crystal by fabricating an organic layer capable of increasing charge transfer efficiency and charge transfer rate, And a manufacturing method thereof.

A first electrode according to the present invention; a first organic material layer disposed on the first electrode; a nanocrystal layer disposed on the first organic material layer; a second organic material layer disposed on the nanocrystal layer; And a second electrode located on the organic material layer, wherein the first organic material layer or the second organic material layer includes a donor material and an acceptor material.

The donor material or the acceptor material may be a polymeric organic material or a low molecular organic material, respectively.

The donor material may be selected from the group consisting of P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy- At least one of polyvinylidene fluoride, polyvinylidene fluoride, polyvinylidene fluoride, polyvinylidene fluoride, polypyridine, polystyrene, polystyrene, polystyrene, It is possible to include one or more.

The acceptor material may be fullerene or a derivative thereof.

The donor material may be P3HT and the acceptor material may be PCBM ([6,6] -phenyl-C61 butyric acid methyl ester).

The nanocrystal layer may include nanocrystals and a barrier material surrounding the nanocrystals.

The nano-crystal may be at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof.

The barrier material may be any one selected from oxides of the nanocrystalline material, Al2O3, TiO2, and CB (carbazole terminated thiol).

And changes into various resistance states according to an input data voltage applied across the first and second electrodes, and a multi-level output current can be generated in a read operation.

As described above, the present invention can improve the reliability of a device by increasing the probability of charging the nanocrystals by fabricating a memory device in which a nanocrystal layer is formed on an organic material layer including a donor material and an acceptor material.

Further, the present invention can repeatedly perform the read, write and erase operations through the organic material layer having the bistable conductive property, maintain the data stored in the cell even if the power source is not applied, .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Wherein like reference numerals refer to like elements throughout.

FIG. 1 is a cross-sectional view of a non-volatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a non-volatile memory device according to a modification of the embodiment.

Referring to FIG. 1, a nonvolatile memory device according to an embodiment of the present invention includes upper and lower electrodes 20 and 70, first and second electrodes 20 and 70 having bistable conduction characteristics between upper and lower electrodes 20 and 70, A second organic layer 30 and 60 and a nanocrystal layer 50 located between the first and second organic layers 30 and 60. In one embodiment of the present invention, the nanocrystal layer 50 is formed of a single layer, but the nanocrystal layer 50 may be formed of a plurality of layers.

A glass substrate, an Al ₂ O ₃ substrate, a SiC substrate, a ZnO substrate, a Si substrate, a GaAs substrate, a GaP substrate, a GaAs substrate, or the like can be used as the substrate 10. , A LiAl ₂ O ₃ substrate, a BN substrate, an AlN substrate, an SOI substrate, and a GaN substrate can be used. When the semiconducting substrate and the conductive substrate are used, they must be separated by an insulator between the lower electrodes 20.

The upper and lower electrodes 20 and 70 may be made of any material having electrical conductivity. The electrode is preferably a metal such as Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof, which are low in electrical resistance and excellent in conductive organic materials and interface characteristics.

The first and second organic layers 30 and 60 may include a donor material and an acceptor material. Here, the donor material refers to a molecule that gives electrons and the acceptor material refers to molecules that receive electrons. The donor material or the acceptor material may be a polymer material or a low molecular material, respectively. In this embodiment, a polymer material is used as a donor material and a low molecular material is used as an acceptor material.

Wherein the donor material is selected from the group consisting of P3HT (poly (3-hexylthiophene)), polysiloxane carbazole, polyaniline, polyethylene oxide, (poly (1-methoxy- At least one of poly (vinylene), poly (indole), pericarbazole, polypyridazine, polyisothianaphthalene, polyphenylene sulfide, polyvinylpyridine, polythiophene, polyfluorene, polypyridine, polystyrene and derivatives thereof Any one or more materials may be used.

As the acceptor material, fullerene or a derivative thereof is used. For example, PCBM ([6,6] -phenyl-C61 butyric acid methyl ester) can be used.

As described above, according to the embodiment of the present invention, the organic material memory characteristics can be improved by using the organic material including the donor material and the acceptor material as the first and second organic material layers 30 and 60. This is because the first and second organic layers 30 and 60 form a charge transfer complex by the donor and acceptor materials. The Charge Transfer Complex is shifted to Excited State due to two or more intermolecular attractive forces, which stabilizes the state of the two molecules while causing charge transfer between the molecules.

When a single organic material is used, the electrons are conducted through hopping in the organic material. However, in the case of forming the charge transporting complex using the donor material and the acceptor material as in the embodiment of the present invention, not only the hopping but also the charge transfer occurs. Therefore, not only the overall charge transfer efficiency in the organic layers 30 and 60 but also the charge mobility increases due to the rapid charge transfer between the donor material and the acceptor material. By increasing the charge transfer efficiency, it is possible to increase the probability of charging the nanocrystals 20 formed in the organic layers 30 and 60, thereby enabling more reliable and improved nonvolatile memory behavior . Further, the organic material layer has two bistable characteristics, that is, two kinds of conductivity at the same voltage.

In one embodiment of the present invention, the donor material and the acceptor material are mixed to form the organic material layer. Alternatively, the organic material layer may be formed to include the donor material layer and the acceptor material layer.

The nanocrystal layer 50 includes a plurality of crystalline nanocrystals 50a and a barrier material 50b surrounding the nanocrystals 50a. The nanocrystal layer 50 includes a nanocrystal 50a including a metal layer material and a barrier material 50b including an oxide of a metal layer material by depositing a metal layer and forming a deposited metal layer by plasma or thermal oxidation As shown in FIG.

At least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof may be used as the metal layer. The O ₂ plasma oxidation process can be performed as the oxidation process.

However, the present invention is not limited to this, and nano-crystals may be formed through oxidation of metal in the deposition chamber. However, it is preferable to use a process of forced oxidation through an O ₂ plasma process along a grain boundary to form a stable nanocrystal having a uniform and uniform size.

In this embodiment, Ni is used for the nanocrystal layer 50. Here, the crystalline material (i.e., nanocrystal) is Ni nanocrystal and the barrier material is Ni _x O _y (e.g., NiO). This is because the Ni nanocrystal layer is formed by oxidizing the surface of the Ni metal layer.

Here, the thickness of the nanocrystal layer 50 is preferably 1 to 40 nm. 1, a layer of nanocrystal 50 is shown. However, the present invention is not limited to this, and a multi-layered nanocrystal layer may be formed. The uniformity of the thickness of the surface oxidized nanocrystal layer 50 indicates that a nanocrystal layer having a thickness within a range of about -30 to + 30% is formed from the target nanocrystal layer thickness.

As described above, the nano-crystal layer 50 of the present embodiment is formed between the first and second organic layers 30 and 60 to have a uniform thickness of 1 to 40 nm or less, The energy gap becomes large, and the data retention of the device can be improved. In addition, when the nanocrystals 50 are formed in the organic layers 30 and 60, the devices can have various resistance states according to voltages applied to the upper and lower electrodes 20 and 70, and can output currents of various levels. Therefore, more than one bit of data can be stored in the unit cell.

Then, as shown in Fig. 2, the basic laminated structure may be formed repeatedly a plurality of times. That is, the lower electrode 20 is located on the substrate 10, the first organic layer 30 is located on the lower electrode 20, the first nanocrystal layer 50 is formed on the first organic layer 30, And a second organic layer 60 is disposed on the first organic layer 30 including the first nanocrystal layer 50. The intermediate electrode 80 is located on the second organic layer 60, The third organic layer 90 is positioned on the first nanocrystal layer 80 and the second nanocrystal layer 100 is positioned on the third organic layer 90 and the fourth organic layer 110 is formed on the second nanocrystal layer 100 And the upper electrode 120 is positioned on the fourth organic layer 110. [

Hereinafter, a method of manufacturing the above-described nonvolatile memory element will be described with reference to the drawings.

FIGS. 3 to 8 are views for explaining a method of manufacturing the nonvolatile memory device according to the present embodiment. (A) is a plan view for explaining a method of manufacturing a nonvolatile memory device, and (b) is a cross-sectional view taken along line A-A of (a).

FIG. 9 is a conceptual cross-sectional view illustrating a method of manufacturing the nanocrystal layer according to the present embodiment.

Referring to FIG. 3, a lower electrode 20 is formed on a substrate 10. That is, the lower electrode 20 arranged in one direction is formed by evaporation. At this time, as the substrate 10, a silicon substrate or a glass substrate can be used.

First, the substrate 10 is loaded into a chamber (not shown) for metal deposition, and then a first shadow mask (not shown) is used to form a region where the lower electrode 20 is to be formed Exposed. Thereafter, the pressure inside the chamber is set to 10 ^-6 to 10 ^-3 Pa, the metal material is evaporated at a temperature of 1000 to 1500 degrees Celsius while the deposition rate is maintained at 2 to 7 angstroms / A metal lower electrode 20 is formed. At this time, Al is used for the lower electrode 20 in this embodiment. However, the present invention is not limited thereto, and the lower electrode can be manufactured using at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, The thickness of the lower electrode 20 may be 50 to 100 nm. A predetermined cleaning process may be performed before or after the lower electrode 20 deposition process.

Referring to FIG. 4, a first organic layer 30 is formed on a substrate 10 on which a lower electrode 20 is formed.

First, an organic material material for manufacturing the first organic material layer 30 is prepared. After preparing the donor and acceptor materials described above for the production of organic materials, The donor and acceptor materials are placed in an organic solvent and blended.

In this embodiment, P3HT is used as a donor material and PCBM is used as an acceptor material.

Next, the prepared organic material is coated on the substrate 10 on which the lower electrode 20 is formed to form the first organic layer 30.

At this time, the first organic layer 30 may be coated through various coating methods. In an embodiment of the present invention, the first organic layer 30 is formed by spin coating, and then annealed in a nitrogen atmosphere after spin coating.

At this time, the thickness of the first organic layer 30 coated on the substrate 10 may be 10 to 100 nm.

In addition to the above-described methods, the first organic layer 30 may be formed on the substrate 10 by various methods other than the coating method described above. For example, a printing method such as printing or screen printing.

Referring to FIGS. 5, 6 and 9, a metal layer 40 is deposited on the first organic layer 30. To this end, the substrate 10 on which the first organic layer 30 is formed is loaded into a chamber (not shown) for metal deposition. The first organic layer 30 on which the nanocrystal layer 40 is to be formed is exposed using a third shadow mask (not shown). Thereafter, the pressure inside the chamber is set to 10 ^-6 to 10 ^-3 Pa, the metal material is evaporated at a temperature of 800 to 1500 degrees Celsius while the deposition rate is maintained at 0.1 to 7.0 Å / s to expose the exposed first organic material layer 30 to form a metal layer 40 having a thickness of 1 to 40 nm.

At this time, since the metal layer 40 has a high deposition rate, it is not formed in the form of nanocrystals, but is formed of a metal thin film having a grain boundary as shown in FIG. 9A.

Then, the substrate 10 on which the metal layer 40 is formed is loaded into a chamber for oxidation. An RF power of 50 to 300 W is applied to the chamber, an AC bias of 100 to 200 V is applied, and an O ₂ gas is injected at a pressure of 0.5 to 3.0 Pa to perform an oxidation process. At this time, the process time is preferably about 50 to 500 seconds.

As described above, when the oxidation process using the O ₂ plasma is performed, a nanocrystal layer 50 including the nanocrystals 50a and the barrier material 50b surrounding the nanocrystals 50a is formed. Here, the barrier material 50b is formed of an oxide of a metal. In one embodiment of the present invention, a Ni nanocrystal layer was formed.

9 (b), the O ₂ plasma is infiltrated along the boundary of the metal layer 40 having grain boundaries and is oxidized along the boundary, as shown in FIG. 9 (c) Sized Ni nanocrystals are formed. At this time, the nanocrystal layer 50 may be formed within a range of 1 to 40 nm in thickness depending on the thickness of the metal layer 40. Of course, the thickness of the metal layer 40 may be increased. However, when the metal layer 40 is too thick (50 nm or more), the O ₂ plasma can not sufficiently penetrate into the crystal grain boundaries of the metal layer 40, ) May not be formed effectively. As shown in FIG. 9 (d), the nanocrystal layer 50 after the oxidation process is formed by oxidizing the nanocrystal of a crystalline material of Ni nanocrystals and the amorphous material of the nanocrystal surface of Ni0.

Here, the multi-layered nanocrystal layer 50 may be formed by repeating the deposition and oxidation of the metal layer 40 a plurality of times.

In one embodiment of the present invention, the nanocrystal layer 50 may be fabricated through various processes other than the above-described oxidation process using plasma.

For example, in order to fabricate the nanocrystal layer 50, a first barrier material layer, a metal layer, and a second barrier material layer are sequentially deposited on the first organic layer 30. Then, the curing process is performed at a temperature of 150 to 300 degrees for 0.5 to 4 hours. Whereby the first and second barrier material layers enclose the nanocrystals of the metal in the metal layer. At this time, Al ₂ O ₃ or TiO ₂ may be used as the barrier material. Through this, a nanocrystal layer 50 including the nanocrystals 50a and the barrier material 50b can be fabricated. In addition, nanocrystals surrounded by a barrier material may be prepared, then dispersed in an organic material and spin-coated to form a layer in which nanocrystals are dispersed in the organic material layer. The barrier material may be CB (carbazole terminated thiol).

Referring to FIG. 7, a second organic layer 60 is formed on the first organic layer 30 having the nanocrystal layer 50 formed thereon in the same manner as the first organic layer 30.

Referring to FIG. 8, an upper electrode 70 is formed on a substrate 10 including a second organic layer 60. At this time, it is preferable that the upper electrode 70 is formed in a direction intersecting with the lower electrode 30.

To this end, the substrate 10 formed up to the second organic layer 60 is first loaded into the chamber for metal deposition, and then the region where the upper electrode 70 is to be formed is exposed using the fourth shadow mask. Thereafter, the pressure inside the chamber is set to 10 ^-6 to 10 ^-3 Pa, the metal material is evaporated at a temperature of 1000 to 1500 ° C while the deposition rate is maintained at 2 to 7 Å / s to expose the exposed second organic layer 60 And a metal electrode is formed on the substrate 10 region. At this time, in this embodiment, it is preferable to use Al as the upper electrode 70, and the thickness of the electrode may be 60 to 100 nm.

Although not shown, a separate metallization process may be performed to connect the upper electrode 70 and the lower electrode 30 to the external electrodes. Whereby the upper electrode 70 and the lower electrode 30 are electrically connected to separate pads. Driving means for applying various input power to these pads is connected. Therefore, various input power sources can be applied to the electrodes to have various output current levels according to the resistance state of the device. Such device characteristics will be described later.

Although a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention has been described, the manufacturing method is not limited thereto and can be manufactured through various methods.

For example, the electrode and the nanocrystal layer may be formed through an E-beam deposition process, a sputtering process, a CVD process, an ALD process, or the like in addition to a thermal evaporation process.

Further, the electrode may be formed on the entire structure, and then the shape may be formed through a patterning process. That is, an electrode may be formed by forming a conductive material on an upper portion of a substrate, and then removing a conductive material in an area excluding the electrode through an etching process using a mask. In addition, an oxidation process may be performed using a wet and dry oxidation method.

The operation and characteristics of the memory device of this embodiment fabricated by the above-described structure and manufacturing method will be described below.

10 is a graph showing a current-voltage characteristic of a memory device according to an embodiment.

10 is a graph illustrating voltage current characteristics of a nonvolatile memory device having an Ni nanocrystal layer using an organic material in which P3HT and PCBM are mixed with an organic material layer.

Referring to FIG. 10, when a voltage is applied to a nonvolatile memory device according to an embodiment of the present invention, the device has various current states (or resistance states) within a constant voltage range as shown in the graph of FIG.

For example, when the lower electrode is connected to the ground and the upper electrode is connected to a predetermined voltage source to sequentially increase the voltage of the voltage source in the positive direction, the current gradually increases up to the voltage (V _th ) Resistance state (I _off ). Thereafter, when the voltage equal to or higher than a certain level (that is, the threshold voltage or the threshold voltage V _th ) is applied, the current has a low resistance state (I _on ) in which the current abruptly rises. When the voltage is continuously increased and the maximum current supply voltage (V _p ) or more is applied, a negative differential resistance (NDR) state is obtained in which the current decreases as the voltage increases. When the voltage is continuously increased, it has a low resistance state in which the current again increases from a constant voltage (V _e ). That is, it can be seen that the nonvolatile memory device according to the present embodiment has various resistance states. Here, the maximum current voltage power source (V _p ) refers to the point where the current flow of the device becomes maximum. Or a voltage at the time when the negative resistance occurs.

Thus, a memory device according to an embodiment of the present invention may implement a multi-level cell in a single memory cell using such a low resistance state.

When the carrier (i.e., charge) is not charged in the surface-oxidized nanocrystal due to the difference in energy level between the nanocrystal layer 50 and the organic layers 30 and 60, the current flow is slightly increased do. However, if the voltage applied to both ends of the organic material layers 30 and 60 is equal to or higher than the threshold voltage V _th , the carriers are charged in the surface-oxidized nanocrystals, and the current flow increases sharply. When the carrier is filled in the nanocrystal, the current flow is several tens to several tens of thousands times larger than the case where the carrier is not charged. If the voltage across both ends of the organic material layers 30 and 60 is the negative resistance region voltage, the carrier is partially discharged (or partially charged) in the nano-crystal and is lower than when the carrier is fully charged It is possible to have a high current flow in an intermediate resistance state. Here, when a voltage equal to or higher than the negative resistance region NDR (erase voltage: V _e ) is applied, carriers charged in the nanocrystal layer are discharged and changed to a non-charged state.

Furthermore, the organic material layers 30 and 60 of the present embodiment are made of an organic material in which a donor material and an acceptor material are mixed. Therefore, movement of carriers in the organic layer 30, 60 occurs by hopping and carrier transfer. Therefore, the carrier mobility can be increased to increase the carrier transmission efficiency. In addition, it is possible to improve the electrical reliability of the device by increasing the filling probability of the charge filled in the nano crystal.

Also, when the voltage of the voltage source is sequentially increased in the negative direction, the current increases with respect to the voltage up to a certain level, and the current sharply increases when a voltage higher than a certain level (threshold voltage: V _th ) is applied . That is, when a voltage equal to or higher than the threshold voltage V _th is applied, the negative resistance state NDR is generated and thereafter the current increases with respect to the voltage equal to or higher than the erase voltage V _e . This is due to the symmetrical structure of the device, which has the same mechanism as in the case of positive directional voltages as described above.

11 and 12 are graphs showing retention and endurance test results of a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 11, a nonvolatile memory device using an organic layer in which P3HT and PCBM are mixed has a single resistance state, which is read out several times. As a result, each state is stably maintained for 10 ⁵ cycles. At this time, it can be seen that both the low resistance state Ion and the high resistance state Ioff are stably maintained. It is also seen that the ratio of the low resistance to the high resistance state (Ion / Ioffration) is also 0.39 × 10 ² , which is largely maintained.

As shown in FIG. 12, when the data is read, erased, and read in the nonvolatile memory device, the endurance test is performed repeatedly, The current level is clearly divided.

The present invention is not limited to the above-described embodiments, but may be embodied in various forms. In other words, the above-described embodiments are provided so that the disclosure of the present invention is complete, and those skilled in the art will fully understand the scope of the invention, and the scope of the present invention should be understood by the appended claims .

1 is a cross-sectional view of a non-volatile memory device according to one embodiment of the present invention;

2 is a cross-sectional view of a non-volatile memory device according to another embodiment of the present invention.

3 to 8 are views for explaining a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

9 is a conceptual cross-sectional view illustrating a method of manufacturing a nanocrystal layer according to an embodiment of the present invention.

10 is a graph showing a current-voltage characteristic of a memory device according to an embodiment of the present invention.

11 and 12 are graphs showing retention and endurance test results of the nonvolatile memory device according to the present embodiment of the present invention.

Description of the Related Art

10: substrate 20: lower electrode

30: first organic layer 50: nanocrystal layer

50a: nano crystal 50b: barrier material

60: second organic material layer 70: upper electrode

Claims (9)

A first electrode; A first organic layer disposed on the first electrode; A nanocrystal layer located on the first organic layer; A second organic material layer disposed on the nanocrystal layer; And And a second electrode located on the second organic layer, Wherein the first organic material layer and the second organic material layer each include a donor material and an acceptor material, Wherein the nanocrystal layer comprises a barrier material layer and a plurality of crystalline nanocrystals formed in the barrier material layer such that the barrier material layer surrounds the plurality of nanocrystals, Wherein the donor material comprises P3HT and the acceptor material comprises PCBM ([6,6] -phenyl-C61 butyric acid methyl ester) Resistance state in which the current increases as the voltage difference between the first and second electrodes increases, and a negative resistance state in which the current decreases as the voltage difference increases. delete delete delete delete delete The method according to claim 1, Wherein the nano-crystal is at least one of Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof. The method according to claim 1, Wherein the barrier material is any one selected from the group consisting of oxides of the nanocrystals, Al2O3, TiO2, and carbazole terminated thiol (CB). The method according to claim 1, Wherein the first and second electrodes are changed to various resistance states according to an input data voltage applied to both ends of the first and second electrodes, and a multi-level output current is generated in a read operation.

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