KR100652135B1 - Organic non-volatile memory fabricated by multi-layer of quantum dots and method for manufacturing the same - Google Patents

Abstract

An organic nonvolatile memory device and its manufacturing method are provided to decrease a power consumption and to improve a processing rate by using a stable multilayer structure composed of quantum dot layers. An organic nonvolatile memory device comprises upper and lower conductive layers(20,70), a conductive organic layer, and at least one or more quantum dot layers. The conductive organic layer(30,60) is formed between the upper and the lower conductive layer. The conductive organic layer has bi-stable conductive characteristics. The quantum dot layers(50) are formed in the conductive organic layer. The thickness of one quantum dot layer is in a predetermined range of 1 to 20 nm.

Description

Organic non-volatile memory fabricated by a stable multi-layer quantum dots and a method for manufacturing the same {Organic non-volatile memory fabricated by multi-layer of quantum dots and method for manufacturing the same}

1A and 1B are cross-sectional views of a nonvolatile memory device according to an embodiment of the present invention.

Figure 2 is a quantum dot layer (Al ₂ O ₃ ) high voltage (300KV) TEM photograph according to the present invention.

3A to 5B are TEM photographs of a nonvolatile memory device and a quantum dot layer according to an embodiment of the present invention.

6 to 8 are I-V graphs for explaining the operation of the nonvolatile memory device according to the present embodiment.

9 to 14 illustrate a method of manufacturing a nonvolatile memory device according to the present embodiment.

15 is a conceptual cross-sectional view for explaining a method for manufacturing a quantum dot layer according to the present invention.

16A to 16C are graphs of analysis results of a nonvolatile memory device according to the present embodiment including a multilayered quantum dot layer using an Auger electron spectrometer (Auger).

<Explanation of symbols for main parts of the drawings>

10: substrate 20, 70: conductive layer

30, 60: organic material layer 50: quantum dot layer

The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and to a nonvolatile memory device and a method for manufacturing the same using an organic material having two conductive states at the same voltage.

Currently, memory devices include volatile D-RAM (D-RAM) devices and nonvolatile flash devices.

The DRAM device adjusts the channel width under the gate according to the voltage applied to the gate to form a channel between the source and drain terminals, and charges or discharges electrons in a capacitor connected to the source terminal. Afterwards, the device reads the charge and discharge states of the capacitor and separates the data of 0 and 1. The DRAM device has a disadvantage in that the capacitor must be continuously recharged, and when power is not applied, there is a problem in that data input to the device is lost due to leakage current.

In addition, the flash device generates an F-N tunneling shape by a voltage applied to the control gate and the channel region, and charges or discharges electrons in the floating gate through the F-N tunneling phenomenon. It is a device that distinguishes data between 0 and 1 by changing the threshold voltage of the channel region according to the state of charge and discharge, and reading the change of the threshold voltage. Such a flash device uses FN tunneling, so the voltage used in the device becomes very large, and the flash memory needs to charge or discharge electrons to the floating gate through FN tunneling made of polysilicon to write and read data. The disadvantage is that the data processing speed is slow at μ-sec.

In addition, in order to implement the above-described conventional memory device, it is difficult to improve the integration degree of the device because it requires at least several tens of steps or more, and it is difficult to maintain high yield and high yield.

At present, many research institutes and companies have been conducting researches to overcome the disadvantages of DRAM and flash devices and to implement next-generation memory devices with the advantages thereof.

The research areas of the next-generation memory devices have been separated in various ways according to the materials constituting the cells which are basic units therein. In other words, when a current is applied to a specific material and the material becomes a solid state with low resistance or a liquid state with high resistance, data is stored or high resistance and low resistance exist at the same voltage when voltage is applied to the conductive organic material. A memory device using bidirectional conduction characteristics or a material of ferroelectric material is applied to the device to have residual polarization properties and to be used as a memory device, or to use ferromagnetic materials having properties of N and S poles using magnetic fields. Attempts have been made to store data using data. In addition, research is being actively conducted on nonvolatile memory devices in which planar floating gates replace quantum dots of metal silicon compound semiconductors in planar silicon.

However, finding the process conditions for applying these materials to highly integrated memory devices by utilizing their properties remains a common problem of current generation memory devices.

In particular, in the case of using the organic material, not only is there no actual mass production, but it is difficult to find the exact process conditions for manufacturing the memory device. That is, in general, in the vacuum deposition method for depositing the organic material, the quantum dots are formed in the conductive organic material by controlling the evaporation rate, but it is difficult to maintain the uniform deposition rate in the chamber, thereby preventing the formation of quantum dots of uniform size distribution. Due to this, there is a disadvantage that the threshold voltage of the device and the Ion / Ioff ratio are uneven.

Therefore, in order to solve the above problems, there is no data loss, low power consumption, high integration, and high bi-stable characteristics of organic materials. It is an object of the present invention to provide a nonvolatile memory device capable of making uniform the threshold voltage and Ion / Ioff rate characteristics in the device, and a method of manufacturing the same.

A conductive organic material layer having a bistable conductive property formed between the upper and lower conductive layers and the upper and lower conductive layers and at least one or more quantum dot layers in the conductive organic layer according to the present invention, wherein one layer of quantum dot layers is 1 to 20 nm It provides a nonvolatile memory device having a thickness of.

Here, it is preferable that the thickness of the said one layer of quantum dot layer is 5-10 nm. The quantum dot layer is preferably formed of 1 to 10 layers. It is effective that the quantum dot layer contains at least one of Al, Mg, Zn, Fe, Ni and alloys thereof. The quantum dot layer preferably includes a crystalline material of γ-Al ₂ O ₃ .

It is effective to use at least one conductive organic material of IDCN, α-NPD, and Alq ₃ as the conductive organic material layer.

The above-described nonvolatile memory device preferably performs a read operation within a range of 0.5 to 2V, a write operation to a range of 2 to 10V or more, and an erase operation to 0V or less. That is, the read operation is performed at the threshold voltage or more, the read operation is performed at the threshold voltage between 0 V, and the erase operation is performed at 0 V or less.

In addition, forming a lower conductive layer on a substrate according to the present invention, forming a first conductive organic material layer on the substrate on which the lower conductive layer is formed, and overlapping a portion of the lower conductive layer. Forming a metal layer on the conductive organic layer, oxidizing the metal layer through an oxidation process to form a quantum dot layer, forming a second conductive organic material on the first conductive organic material on which the quantum dot layer is formed, and 2. A method of manufacturing a nonvolatile memory device including forming an upper conductive layer on a conductive organic material such that the quantum dot layer and a portion thereof overlap each other.

Herein, the first and second conductive organic layers may use conductive organic materials such as IDCN, α-NPD, and Alq ₃ , and may use the first and second conductive organic layer thickness ranges in which the Ion / Ioff ratio may be 10 or more. Do.

The forming of the metal layer may include: evaporating a metal material at a deposition rate of 1 to 7.0 kW / s at a pressure of 10 ⁻⁵ to 10 ⁻³ Pa and a temperature of 800 to 1500 degrees Celsius, and then on the first conductive organic material layer. It is effective to form a metal layer having a thickness of 1 to 30 nm. That is, after the shadow mask is mounted in the vacuum deposition chamber, a metal layer is formed under the above conditions, and an oxidation process is performed.

In this case, the oxidation process is preferably an oxidation process using an O ₃ plasma. This oxidation process is effective to perform 50 to 500 seconds by injecting O ₂ gas at a pressure of 0.5 to 3.0pa in the atmosphere of RF power of 50 to 300W and AC bias of 100 to 200V. As described above, the quantum dots are formed in the O ₃ plasma chamber, and then moved to an evaporation deposition chamber, which is a multi-chamber system, to form a conductive organic layer and a conductive layer.

The conductive layer and the conductive organic material layer are preferably formed through a vacuum evaporation method.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A and 1B are cross-sectional views of a nonvolatile memory device according to an embodiment of the present invention. 2 is a high voltage (300KV) TEM photograph of a quantum dot layer according to the present invention.

3A to 5B are high-magnification (300 KV) TEM photographs of a nonvolatile memory device and a quantum dot layer according to an embodiment of the present invention.

3A is a TEM photograph of a nonvolatile memory device having a single quantum dot layer having a thickness of 5 nm, and FIG. 3B is a high resolution TEM photograph of the quantum dot layer region of FIG. 3A. 4A is a TEM image of a nonvolatile memory device having a single quantum dot layer having a thickness of 10 nm, and FIG. 4B is a high resolution TEM image of the quantum dot region of FIG. 4A. FIG. 5A is a TEM photograph of a nonvolatile memory device having five quantum dot layers having a thickness of 10 nm, and FIG. 5B is a high resolution photograph of the quantum dot layer region of FIG. 5A. In the photograph, 1 represents an upper conductive layer 70, 2 represents a second conductive organic layer 60, 3 represents a quantum dot layer 50 region, 4 represents a first organic layer 30, and 5 represents a lower conductive layer 20. .

1A through 5B, the nonvolatile memory device of the present invention may have an organic material layer 30 having bistable characteristics between upper and lower conductive layers 20 and 70 and upper and lower conductive layers 20 and 70. 60 and a quantum dot layer 50 having quantum dots uniformly distributed between the organic material layers 30 and 60.

In this case, the conductive organic layers 30 and 60 may be formed in multiple layers, and a single layer or multiple quantum dot layers 50 may be formed between the conductive organic layers 30 and 60. That is, as shown in FIGS. 1A and 1B, the lower conductive layer 20 is positioned on the substrate 10, the first conductive organic layer 30 is positioned on the lower conductive layer 20, and the first conductive organic layer is disposed. A single or multiple quantum dot layer 50 is positioned on the 30, a second conductive organic layer 60 is positioned on the first conductive organic layer 30 including the quantum dot layer 50, and a second conductive organic layer An upper conductive layer 70 is positioned on 60.

The material layers described above may be manufactured using various patterning processes used in the manufacturing process of the semiconductor device. Preferably, in the present embodiment, it is effective to form the conductive layer 70, the conductive organic material layers 30 and 60, and the quantum dot layer 60 through an evaporation deposition process.

As the substrate 10, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used, that is, a plastic substrate, a glass substrate, an Al ₂ O ₃ substrate, a SiC substrate, a ZnO substrate, a Si substrate, a GaAs substrate, or a GaP substrate. At least one of a LiAl ₂ O ₃ substrate, a BN substrate, an AlN substrate, an SOI substrate, and a GaN substrate may be used. When using a semiconductive substrate and a conductive substrate should be separated by an insulator between the lower conductive layer (20).

The upper and lower conductive layers 20 and 70 may use any material having electrical conductivity. The conductive layer is preferably a metal such as Al, Cu, Ag, Pt, Au having low electrical resistance and excellent interfacial properties with the conductive organic material.

It is preferable to use at least one of AIDCN, α-NPD, and Alq ₃ as the first and second organic material layers 30 and 60.

AIDCN is represented by the following Chemical Formula 1.

α-NPD is represented by the following Chemical Formula 2.

Alq ₃ is represented by the following Chemical Formula 3.

The organic material described above has bistable properties, that is, two conductivity at the same voltage. This will be described later.

The quantum dot layer 50 uses at least one of Al, Mg, Zn, Fe, Ni and alloys thereof to deposit the metal on the first conductive organic material 30 in an evaporation deposition chamber, and to perform an O ₃ plasma oxidation process. To form. In this embodiment, the quantum dot layer 50 is preferably formed using Al. In this case, the quantum dot layer 50 includes a quantum dot, which is a crystalline material, and an amorphous material surrounding the crystalline material, as shown in FIG. 2. In this case, the crystalline material is γ-Al ₂ O ₃ , the amorphous material is preferably Al _x O _y .

In addition, the quantum dot layer 50 may be formed as a single layer as shown in FIG. 1A, or may be formed as a multilayer as shown in FIG. 1B. In addition, in the present embodiment, a quantum dot layer 50 having a plurality of quantum dots having a uniform size distribution is formed between the first and second conductive organic layers 30 and 60, thereby causing a threshold voltage and ion between unit elements. Reduce the spread of the / Ioff rate. At this time, it is preferable that the thickness of the quantum dot layer 50 which comprises a single layer is 1-20 nm. In addition, the quantum dot layer 50 of the above-described single layer may be laminated in one to ten layers. Furthermore, as shown in Figs. 3A to 4B, the thickness of the quantum dot layer 50 is more preferably 5 to 10 nm, and the number of layers of the quantum dot layer 50 to be stacked is preferably 2 to 8. At this time, it is preferable to form the same thickness of the quantum dot layer 50 of each layer stacked as shown in Figure 5a and 5b. At this time, the same thickness of the quantum dot layer 50 refers to the formation of a quantum dot layer having a thickness in the range of about -30 to + 30% of the target quantum dot layer thickness. Of course, the size of the quantum dot may be the same as the thickness of the quantum dot layer 50 described above.

As described above, the quantum dot layer 50 of the present embodiment is formed to have a uniform thickness of 15 nm or less between the first and second conductive organic material layers 30 and 60 to increase the energy gap of the quantum dots between the organic material layers. The data retention of the device can be improved. In addition, the quantum dot layer may be formed of a plurality of layers to lower the threshold voltage for data writing.

The operation of the memory device of the present embodiment having the above-described configuration will be briefly described as follows.

6 to 8 are I-V graphs for explaining the operation of the memory device according to the present embodiment.

FIG. 6 is a graph illustrating voltage and current characteristics of a nonvolatile memory device having a 5 nm thick single layer quantum dot layer, and FIG. 7 is a graph illustrating voltage and current characteristics of a 10 nm thick single layer quantum dot layer. 8 is a graph showing current characteristics of a nonvolatile memory device having five quantum dot layers having a thickness of 10 nm.

6 to 8, as described above, the nonvolatile structure of the present embodiment has a structure in which conductive organic material layers / quantum viscous layers / conductive organic material layers 30, 40, and 50 are formed between upper and lower conductive layers 20 and 70. When a voltage is applied to the conductive layers 20 and 70, the memory device has two current states within a predetermined voltage range as shown in the drawing.

For example, when the lower conductive layer 20 is connected to the ground and the upper conductive layer 70 is connected to a predetermined voltage source to sequentially increase the voltage level of the voltage source in the positive direction, the voltage up to a predetermined level is exponential. Therefore, when a high resistance state (see a in FIG. 6) and a voltage higher than a threshold voltage (see b in FIG. 6) are applied, the current rapidly rises to a low resistance state (see FIG. 6C). Subsequently, even if the voltage level of the upper conductive layer 70 is lowered below the threshold voltage, the flow of current decreases rapidly, but the set state is exponentially low in the set state.

This is because when the low voltage is applied and the carrier is not charged through the tunneling in the quantum dot due to the energy level difference between the quantum dot layer 50 and the conductive organic layers 30 and 60, the current flow becomes minute at a predetermined voltage level. do. However, if the voltage across the conductive organic layers 30 and 60 is greater than or equal to the threshold voltage, tunneling of the conductive organic layer occurs and current flows rapidly as the carrier accumulates in the quantum dots. Subsequently, when carriers are accumulated in the quantum dots, the current flows up to several tens of times as compared to when discharged (set state). On the other hand, when a low voltage in the reverse direction is applied (see d in FIG. 6), the carrier charged in the quantum dot is discharged (reset state).

That is, when a voltage of 1 V is applied as shown in the graph of FIG. 6, a current of about 10 ⁻⁸ A flows, and electrons accumulate in the quantum dots of γ-Al ₂ O ₃ when a voltage of 5 V or more is applied. In this case, a write state is set in which a current of 10 ^-5 A or more flows. Even when the voltage falls back below the threshold voltage (5V), a current of 10 ^-8 A is maintained to maintain a low resistance state, and when 1V is applied again, '1' data (1), which is a memory low resistance state (Ion), is memorized. Read On the other hand, when -0.5 to -1V is applied, the carriers accumulated in the quantum dots are discharged, resulting in a high resistance state of -10 ^-7 to -10 ^-8 . After that, when 1V is applied again, '0' data (data 0), which is a memorized resistance state, is read. In order to apply the threshold voltage to a giga bit class nonvolatile memory device, a threshold voltage of 3V or less and Ion / Ioff are preferably 10 times or more. The threshold voltage and the Ion / Ioff ratio change according to the thickness of the quantum dot layer 50 and the number of layers in which the quantum dot layer 50 is stacked.

That is, as shown in FIG. 6, when the quantum dot layer 50 is a single layer and its thickness is 5 nm, a write operation may be performed at about 5 V or more, and as shown in FIG. 7, the quantum dot layer 50 may be If it is a single layer and the thickness is 10nm, the write operation may be performed at about 2.2V or more, and as shown in FIG. 8, the quantum dot layer 50 is five layers, and when the thickness is 10nm, about 1.5V. The write operation may be performed as described above. Preferably, the threshold voltage for writing is effectively in the range of 1V to 5.5V, more preferably in the range of 1.1 to 2.5V. On the other hand, once written data is not erased even when power is not applied to the memory device, and the state is maintained.

As shown in FIG. 6, when the quantum dot layer 50 is a single layer and has a thickness of 5 nm, the bistable conductive property is exhibited at a voltage between 0.1 and 4.9 V, and thus the threshold voltage may be used at 5 V or more. As shown in FIG. 7, when the quantum dot layer 50 is a single layer and has a thickness of 10 nm, the bistable conductive property is exhibited at a voltage between 0.1 and 2.1V, thereby enabling the memory operation to have a threshold voltage of 2V. As shown in FIG. 8, when the quantum dot layer 50 has five layers, and the thickness thereof is 10 nm, the bistable conductive properties are exhibited at a voltage between 0.1 and 1.4 V. Thus, the threshold voltage may be 1.4 V to operate the memory. have. Therefore, in order to operate as a nonvolatile memory device, the Ion / Ioff ratio is 10 times or more, and the lower the threshold voltage, the better. The operating voltage for reading is effectively in the range of 0.1 to 4.9V, more preferably in the range of 0.1 to 1.4.

Next, when an erase voltage is applied to the memory device, the carrier is discharged in the quantum dot to erase data in the memory to a logic low '0'. Here, the operating voltage for erasing is preferably a voltage between -4 and -0.1V. In addition, the thickness of the quantum dot layer 50 and the number of layers on which the quantum dot layer 50 is stacked may be variously changed. Of course, lower negative voltages can reduce device power consumption.

Here, the logic value described above may be changed according to the direction of the measured current.

In the nonvolatile memory device of the present embodiment capable of performing such an operation, its operating characteristics are changed according to the manufacturing conditions and methods of the quantum dot layer and the organic material layer, and its operating voltage is greatly increased according to the manufacturing method and structure of the quantum dot layer. Change.

Hereinafter, process conditions and a manufacturing method for manufacturing the nonvolatile memory device having the binocular conductive characteristics described above will be described.

9 to 14 are diagrams for describing a method of manufacturing a nonvolatile memory device according to the present embodiment. In the figure, (a) is a plan view for explaining the manufacturing method of the nonvolatile memory device, (b) is a cross-sectional view taken along the line A-A of (a).

Referring to FIG. 9, the lower conductive layer 20 is formed on the substrate 10. That is, the lower conductive layer 20 having a linear shape is formed by using evaporation. In this case, it is effective to use a silicon substrate or a glass substrate as the substrate 10, and when the silicon substrate is used, the insulating film must be entirely deposited thereon. It is preferable to use an oxide film or a nitride film-based material film as the insulating film.

First, the substrate 10 is loaded into a chamber (not shown) for metal deposition, and then a region where the lower conductive layer 20 is to be formed is exposed using a first shadow mask (not shown). Subsequently, the exposed area of the substrate 10 by evaporating a metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining a pressure of 10 ^-5 to 10 ^-3 Pa and maintaining a deposition rate of 2 to 7 Pa / s. A metal conductive layer 20 is formed on the substrate. At this time, it is preferable to use Al as the conductive layer 20 in this embodiment, and it is effective that the thickness of the conductive layer 20 is 50-100 nm. The lower conductive layer 20 is preferably manufactured in a straight line shape extending in the vertical direction. A predetermined cleaning process may be performed before or after the lower conductive layer 20 deposition process.

Referring to FIG. 10, the first conductive organic layer 30 is formed on the substrate 10 on which the lower conductive layer 20 is formed.

In order to form the first conductive organic material layer 30, the substrate 10 on which the lower conductive layer 20 is formed is loaded into a chamber (not shown) for organic material deposition. An area of the substrate 10 on which the first organic material layer 30 is to be formed is exposed using a second shadow mask (not shown). In this case, a portion of the exposed area is formed in a shape surrounding the lower conductive layer 20, and as shown in FIG. 10, the lower conductive layer 20 is exposed to a central portion thereof. Of course, the present invention is not limited thereto and may be a figure shape including a circle, an ellipse, a triangle, a polygon, and the like. Subsequently, the substrate 10 exposed by evaporating the organic material at a temperature of 150 to 200 degrees Celsius while maintaining a pressure of 10 ^-5 to 10 ^-3 Pa and maintaining a deposition rate of 0.2 to 0.8 Pa / s. The first conductive organic layer 30 is formed on the lower conductive layer 20. In the present embodiment, it is preferable to use AlDCN as the organic material layer, and it is effective that the thickness of the first conductive organic material layer 30 is 10 to 100 nm.

15 is a conceptual cross-sectional view for explaining a method for manufacturing a quantum dot layer according to the present invention.

11, 12, and 15, a quantum dot layer 50 is formed on the first conductive organic layer 30, and a portion of the quantum dot layer 50 overlaps with a portion of the lower conductive layer 20. do. In this case, in order for the quantum dot layer 50 to have a uniform thickness distribution of 1 to 20 nm or less, the metal layer 40 is deposited on the first conductive organic material layer 30 and then subjected to an oxidation process using an oxygen plasma to perform a quantum dot layer. To form (50).

To this end, the substrate 10 on which the first conductive organic layer 30 is formed is loaded into a chamber (not shown) for metal deposition. The first conductive organic layer 30 on which the quantum dot layer 40 is to be formed is exposed using a third shadow mask (not shown). As mentioned above, a portion of the first conductive organic layer 30 is exposed, so that at least a portion of the lower conductive layer 10 under the first conductive organic layer 30 and the quantum dot layer 50 may overlap. In this case, the shape of the region exposed by the third shadow mask is preferably formed in the same shape as the first conductive organic material layer 30. Then, the first conductivity exposed by evaporating the metal material at a temperature of 800 to 1500 degrees Celsius while maintaining a pressure of 10 ^-5 to 10 ^-3 Pa and maintaining a deposition rate of 1 to 7.0 Pa / s. The metal layer 40 having a thickness of 1 to 30 nm is formed on the organic layer 30.

At this time, the metal layer 40 is not formed in the form of quantum dots because of the high deposition rate, and is formed of a metal thin film having a grain boundary as shown in FIG.

Next, the substrate 10 on which the metal layer 40 is formed is loaded into a chamber for oxidation. RF power of 50 to 300 W is applied to the chamber, an AC bias of 100 to 200 V is applied, and an oxidation process is performed by injecting O ₂ gas at a pressure of 0.5 to 3.0 Pa. At this time, the process time is preferably carried out for about 50 to 500 seconds.

As a result, the O ₃ plasma penetrates along the boundary of the metal layer 40 having the grain boundary as shown in FIG. 15 (b) and oxidizes along the boundary, thereby protons having the same size as shown in FIG. 15 (c). Dots are formed. In this case, the quantum dot layer 50 may be formed within a thickness of 1 to 20 nm depending on the thickness of the metal layer 40. Of course, the thickness of the metal layer 40 may be formed to be thick, but when the metal layer 40 becomes very thick (50 nm or more), the O ₃ plasma may not sufficiently penetrate into the grain boundary of the metal layer 40, thereby causing the quantum dot layer 50 to be formed. This may not be formed effectively. FIG quantum gradation 50 after completion of the oxidation process, as shown in 15 (d) is made of a non-crystalline material of the quantum dots and the crystalline material of _{γ-Al 2 O 3, Al0} x O y.

Here, the deposition and oxidation processes of the metal layer 40 described above may be repeated a plurality of times to form a multilayer quantum dot layer 50. In this case, all of the quantum dot layers 50 may be formed to have the same thickness or may have different thicknesses according to the deposition thickness of the metal layer 40. Preferably, it is effective to form 1 to 10 quantum dot layers 50 having the same thickness with each other.

In this embodiment, the quantum dot layer 50 may be formed using the same mask as the mask for forming the first conductive organic layer 30, but the quantum dot layer 50 may be formed in the organic layer to form the quantum dot layer 50. It is effective to prevent the phenomenon in which the conductive layers 20 and 70 are short-circuited.

Referring to FIG. 13, a second conductive organic material layer 60 is formed on the first conductive organic material layer 30 on which the quantum dot layer 50 is formed.

In order to form the second conductive organic material layer 60, the substrate 10 on which the quantum dot layer 50 is formed is loaded into a chamber for organic material deposition. The first conductive organic layer 30 on which the quantum dot layer 50 is formed is exposed using a second shadow mask for depositing the first conductive organic layer 30. Thereafter, the pressure inside the chamber was 10 ⁻⁵ to 10 ⁻³ Pa, and the quantum dot layer 50 was exposed by evaporating the organic material at a temperature of 150 to 200 degrees Celsius while maintaining the deposition rate at 0.2 to 0.8 Pa / s. ) To form a second conductive organic layer 60. In the present embodiment, it is preferable to use AlDCN as the organic material layer, and it is effective that the thickness of the second conductive organic material layer 60 is 10 to 100 nm. As such, the quantum dot layer 50 is formed on a portion of the first conductive organic material 30, and the second conductive organic material layer 60 forms the quantum dot layer 50 by depositing the second conductive organic material layer 60 thereon. It is formed in a wrapping shape. As described above, the second conductive organic material layer 60 may be formed in a shape surrounding the quantum dot layer 50, and may be formed to have the same thickness as the first conductive organic material 30, or may have a smaller thickness.

Referring to FIG. 14, the upper conductive layer 70 is formed on the substrate 10 including the second conductive organic layer 60. In this case, the upper conductive layer 70 may be formed in a straight line shape extending in a direction perpendicular to the lower conductive layer 30.

To this end, first, the substrate 10 formed up to the second conductive organic layer 60 is loaded into a chamber for metal deposition, and then a region where the upper conductive layer 70 is to be formed is exposed using a fourth shadow mask. That is, a portion of the upper portion of the second conductive organic layer 50 and a portion of the substrate 10 are exposed. In this case, a portion of the quantum dot layer 50 under the second conductive organic layer 60 and the upper conductive layer 70 may be formed to overlap each other. Most preferably, it is effective to adjust the exposed area so that the quantum dot layer 50 is disposed between the overlapping area of the lower conductive layer 30 and the upper conductive layer 70. Then, the second conductive organic material layer exposed by evaporating the metal material at a temperature of 1000 to 1500 degrees Celsius while maintaining a pressure of 10 ^-5 to 10 ^-3 Pa and maintaining a deposition rate of 2 to 7 Pa / s. 60 and a conductive layer of metal are formed in the region of the substrate 10. At this time, in the present embodiment, it is preferable to use Al as the upper conductive layer 70, and it is effective that the thickness of the conductive layer is 60 to 100 nm. The upper conductive layer 70 is preferably manufactured in a straight line shape extending in the horizontal direction.

Thereafter, a separate metal wiring process may be performed to connect the upper conductive layer 70 and the lower conductive layer 30 to the external electrode.

In addition, the lower and upper conductive layers 30 and 70, the first and second conductive organic layers 20 and 60, and the quantum dot layer 50 may be in-situ in a vacuum atmosphere. . That is, in the above description, the chamber for forming the conductive layer, the conductive organic layer, and the quantum dot layer may be deposited in a single deposition system.

For example, a chamber for conducting conductive layer deposition, a chamber for conducting conductive organic layer deposition, a plasma generating chamber for oxidation, a cooling chamber, a load lock chamber, and a shadow mask chamber are connected to a single transfer module. Deposition can be made within the system. When the substrate is transferred from the chamber for conductive layer deposition to the chamber for organic layer deposition, the substrate is not exposed to the air, but can be moved in the vacuum transfer module. Of course, the present invention is not limited thereto, and the chambers may be connected to different systems.

In the above description, the non-volatile memory device according to the present embodiment is manufactured by using a shadow mask and vacuum evaporation without performing an etching process, but the present invention is not limited thereto and may be manufactured through various memory device manufacturing methods. Can be. The conductive layer, the organic material layer, and the quantum dot layer may be formed through an E-beam deposition process, a sputtering process, a CVD process, a MOCVD process, an MBE process, a PVD process, an ALD process, and the like in addition to a thermal evaporation process. The conductive layer and the organic material layer may be formed on the entire structure, and then the shape may be manufactured through a patterning process. That is, the conductive layer may be formed by forming a conductive material on the substrate, and then removing the conductive material except for the conductive layer through an etching process using a mask. The oxidation process may also be carried out using wet and dry oxidation methods.

16A to 16C are graphs of results obtained by analyzing a nonvolatile memory device including a multilayer quantum dot layer using Auger electron spectroscopy.

16A to 16C illustrate the results of analyzing the nonvolatile memory device of the present invention using five Auger electron spectroscopy, in which a quantum dot layer having five layers of about 10 nm thickness is formed by repeating the deposition and oxidation processes of the metal layer described above five times. Is a graph showing the distribution of Auger electrons from the top layer to the quantum dot layer. In this case, a represents a distribution of oxygen (O), b represents a distribution of aluminum (Al), and c represents a distribution of carbon (C).

16B and 16C are graphs showing magnification of Auger electron distribution results in the quantum dot layer, respectively, showing distributions of oxygen and aluminum, respectively. Here, it can be seen that oxygen and aluminum each have about five peak distribution change intervals, through which γ-Al ₂ O ₃ crystals are disadvantageous by Al _x O _y amorphous material and exist in five layers sequentially. It can be seen. That is, the deposition and oxidation processes of the metal layer according to the present invention may be repeated to sequentially stack the quantum dot layer by the number of target layers.

As described above, the present invention can provide a memory device having low power consumption, high processing speed, and high integration through a device having a conductive organic layer and a quantum dot layer formed therebetween.

In addition, the bistable conductive properties of the organic material may be used to repeatedly perform read, write, and erase operations, and maintain data stored in the cell even when power is not applied.

In addition, by depositing a metal layer and oxidizing it to form a quantum dot layer of 20 nm or less, and in particular, the shape of the quantum dot can be made uniform, it is possible to expect a uniform threshold voltage and Ion / Ioff during non-volatile memory operation.

In addition, the energy bend gap of the quantum dot layer may be increased by reducing the size of the quantum dot, thereby improving the data storage capacity of the device.

In addition, since the quantum dot layer can be formed in multiple layers, the threshold voltage of the device can be lowered, the Ion / Ioff ratio can be increased, and device power consumption can be reduced.

Claims (12)

Upper and lower conductive layers; A conductive organic material layer having bistable conductive properties formed between the upper and lower conductive layers; And At least one or more quantum dot layer in the conductive organic layer, The quantum dot layer of one layer is a nonvolatile memory device having a thickness of 1 to 20nm. The method according to claim 1, The thickness of the quantum dot layer of the one layer is 5 to 10nm nonvolatile memory device. The method according to claim 1, The quantum dot layer is a nonvolatile memory device formed of 1 to 10 layers. The method according to claim 1, The quantum dot layer is at least one of Al, Mg, Zn, Fe, Ni and alloys thereof. The method according to claim 4, The quantum dot layer includes a crystalline material of γ-Al ₂ O ₃ . The method according to claim 1, Non-volatile memory device using a conductive organic material of at least one of IDCN, α-NPD and Alq ₃ as the conductive organic layer. The method according to claim 1, A nonvolatile memory device which performs a read operation within a range of 0.5 or more and less than 2V, a write operation in a range of 2 to 10V or more, and performs an erase operation below 0V. Forming a lower conductive layer on the substrate; Forming a first conductive organic material layer on the substrate on which the lower conductive layer is formed; Forming a metal layer on the first conductive organic material layer so as to overlap a portion of the lower conductive layer; Oxidizing the metal layer to form a quantum dot layer through an oxidation process; Forming a second conductive organic material on the first conductive organic material on which the quantum dot layer is formed; And And forming an upper conductive layer on the second conductive organic material such that the quantum dot layer and a portion thereof overlap each other. The method of claim 8, wherein the forming of the metal layer, Under a pressure of 10 ^-5 to 10 ^-3 Pa and a temperature of 800 to 1500 degrees Celsius, the metal material is evaporated at a deposition rate of 1 to 7.0 kW / s to form a metal layer having a thickness of 1 to 30 nm on the first conductive organic material layer. Method of manufacturing a nonvolatile memory device. The method according to claim 8, The oxidation process is an oxidation process using an O ₃ plasma. The method of claim 10, wherein the oxidation process A method of manufacturing a nonvolatile memory device, which is performed for 50 to 500 seconds by injecting O ₂ gas at a pressure of 0.5 to 3.0 pa under an atmosphere of an RF power of 50 to 300 W and an AC bias of 100 to 200 V. The method according to any one of claims 7 to 11, The conductive layer and the conductive organic material layer is formed by a vacuum evaporation method of manufacturing a nonvolatile memory device.

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